JPS63104343A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS63104343A
JPS63104343A JP61250974A JP25097486A JPS63104343A JP S63104343 A JPS63104343 A JP S63104343A JP 61250974 A JP61250974 A JP 61250974A JP 25097486 A JP25097486 A JP 25097486A JP S63104343 A JPS63104343 A JP S63104343A
Authority
JP
Japan
Prior art keywords
chips
chip
stacked
semiconductor device
circuit section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61250974A
Other languages
English (en)
Inventor
Hiroshi Kuranaga
蔵永　寛
Takeo Nakabayashi
中林　竹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61250974A priority Critical patent/JPS63104343A/ja
Publication of JPS63104343A publication Critical patent/JPS63104343A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体集積回路チップを積み上げ、高機能
化、高集積化をはかった半導体装置に関するものである
。
［従来の技術Ｊ 第２図、第３図は、従来の半導体装置を示す平面図及び
その■−■断面図であり、図において（１）は第一層目
の集積回路チップ、（２）は第二層目の集積回路チップ
、（３）は（１）の回路部分を保護し、（１）と（２）
を固定する層、（４）は（１）と（２）の回路を電気的
に接続するワイヤーであり　、（５）はワイヤーボンデ
ィング用パッドである。
従来の半導体装置は上記のように構成され、上記の要順
で、何層にも重ね合せ回路の集積度を上げ、また高機能
化をはかることができる。
〔発明が解決しようとする問題点〕
上記のような従来の半導体装置では、積み上げる二つの
チップの問にチップ同志を固定し、下のチップの回路部
分を保護するための層（３〕を、非導電性で、熱などの
要因による変形がきわめて小さい物質で作る必要があり
、また、上下のチップを電気的に接続するためには、チ
ップの周辺ｔて設けたパッド（５）をワイヤーボンディ
ングで結ぶしかなく回路の設計にあ之っての制約が多い
という問題点があった。
この発明はかかる問題点を解決するためになされたもの
で、前記保護層を必要とせず、また、積み逼ねられたチ
ップ間の信号のやりとりをワイヤ−ポンデイング以外の
方法で行える半導体装置を得ることを目的とする。
〔問題点を解決するための手段〕
この発側に係る半導体装置は、二枚以上のチップを回路
面を向い合せ、回路面上に作られた電極同志を接続する
ことによって電気的に接続し、固定した重ね合せチップ
、前記重ね合せチップを積み上げ、ワイヤーボンディン
グにより電気的に接続したものである。
〔作用〕
この発明においては、前記重ね合せチップ内のチップ間
では、任意の場所に設けられた’４　ＴＪｉをにより固
定し、また、電気信号のやりとりを行い、他の前記重ね
合せチップとは、チップの裏面同志をけり合せ、固定し
、ワイヤーボンディングにより、電気信号のやりとシを
おこなっている。
〔実施例Ｊ 第１図はこの発明の一実施例を示す断面図であり、前記
重ね合せチップを２つ積み重ねたものである。（ｌａ）
、（２ａ）はともに、その上面に回路部分をもつチップ
、　　（ｌｂ）　、　　（２ｂ）はともに、その下面に
回路部分をもつチップ、（６）は前記重ね合せチップ内
で電気的接続をとり、チップを固定する模型結合手段で
本実施例ではバンプを用いており、（７）はこのバンプ
用バンドを示し、（１０）は、下段の重ね合せチップ、
　　（２０）は上段の重ね合せチップを示しており、（
１０）と（２０）／／ｉ、ワイヤー（４）Ｋより電気的
に接続され、グイボンドと同様の技術でチップの裏面同
志をはり合せ固定されている。そのため従来の装置には
必要だった保護層（３）を必要としない。
前記重ね合せチップを構成するチップ間は、バンプによ
り電気的に接続されているので、従来の半導体装置に比
べ設計がより容易になっている。
なお、上記実施例では、前記重ね合せチップを２段重ね
たものを示したが、３段以上槓み蒐ねることによってよ
り高い集積度を得ることが’２ＩＩｌｉＢである。
また、前記重ね合せチップは３枚以上のチップを用いて
構成することができ、第４図に、前記重ね合せチップを
３枚のチップで構成した場合の一実施例の断面図を示す
。
また、前記重ね合せチップを構成するチップは、同一の
プロセスを用いて作る必要がない次め、多種類のプロセ
スで作られたチップを組み合せ、構成することによって
高機能化をはかることができる別の効果もある。
上記実施例では、バンプ（６）を用いる場合であったが
、チップ（１ａ）、（１ｂ）のいずれかチップ（２ａ）
　（２ｂ）のいずれかのパッド（７）上に成長した企な
どの厚いメッキ層を用いてもよい。
なお上記で説明を省略したがチップ（ｌｂ）　（２ａ）
間の接続方法としては通常のグイボンディング時の方法
を採用した。
〔発明の効果］ この発明は以上説明したとおり、二枚以上のチップを回
路面を向い合せ、バンプ等を用いて電気的に接続し、固
定した重ね合せチップを槓み上げることにより、高集積
化をはかり、従来装置に必要だった保護層をなくす効果
がある。
【図面の簡単な説明】
第１図、第４図は、この発明の一実施例を示す断面図、
第２図、第３図はそれぞれ、従来の半導体装置を示す平
面図、断面図である。 図において、（ｌａ）　Ｑｂ）　（２ａ）　（２ｂ）は
集積回路チップ、（４）はワイヤー、（６）＃″１′機
電結模型段、（１０）　（２０）はともに重ね合せチッ
プである。 なお、各図中同一符号は同一または相当部分を示す。 代　理　人　　大　　岩　　　増　　雄第１図 ７ａ、ｌｂ、２ａ、２ｂ　：　ナッグ 手　゛　ワイヤー に：鐵電結合＋段 ｌＯ゛　下段型ね冶−ヒチソグ ２０、上段重ね今でチップ 第２図 第３図 第４図 手続補正書（自発） 特許庁長官殿　　　　　　　　　０ １、事件の表示　　　特願昭６１−２５０９７４号２、
発明の名称 半導体装置 ３、補正をする者 事件との関係　特許出願人 住　所　　　　　東京都千代田区丸の内二丁目２番３号
名　称　　（６０１）三菱電機株式会社代表者志岐守哉 ４、代理人 住　所　　　　東京都千代田区丸の内二丁目２番３号５
、補正の対欧 （１）明細書の発明の詳細な説明の欄 （２）図面 ６、補正の内容 （１）明細書をつぎのとおり訂正する。 （２）図面の第１図を別紙のとおり訂正する。 ７．添付書類の目録 （１）図面（第１図）　　　　　　　１通以　　上 第１図 ｈ ４：ワイヤー ６：檄也轄８１投 ｌＯ：　下４災堡鞄し午せ令・ンフ・ ２θ　：　上民１　ね８文七ケ・ンフ。

Claims (1)

    【特許請求の範囲】
  1. （１）いずれも、機電結合手段により素子を形成された
    互の活性面を向い合せに結合された２枚以上のチップか
    らなり、それぞれの前記チップの前記活性面の反対側の
    面同志で接着して、積み上げられている複数の重ね合せ
    チップと 前記重ね合せチップ間を結合するワイヤとを備えた半導
    体装置。
JP61250974A 1986-10-21 1986-10-21 半導体装置 Pending JPS63104343A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61250974A JPS63104343A (ja) 1986-10-21 1986-10-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61250974A JPS63104343A (ja) 1986-10-21 1986-10-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS63104343A true JPS63104343A (ja) 1988-05-09

Family

ID=17215795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61250974A Pending JPS63104343A (ja) 1986-10-21 1986-10-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS63104343A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6157080A (en) * 1997-11-06 2000-12-05 Sharp Kabushiki Kaisha Semiconductor device using a chip scale package
US6208018B1 (en) 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US6407456B1 (en) 1996-02-20 2002-06-18 Micron Technology, Inc. Multi-chip device utilizing a flip chip and wire bond assembly
US6593647B2 (en) * 2001-06-15 2003-07-15 Oki Electric Industry Co., Ltd. Semiconductor device
US6682954B1 (en) * 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6951774B2 (en) * 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US7109059B2 (en) 1996-11-20 2006-09-19 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6337227B1 (en) 1996-02-20 2002-01-08 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6407456B1 (en) 1996-02-20 2002-06-18 Micron Technology, Inc. Multi-chip device utilizing a flip chip and wire bond assembly
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7371612B2 (en) 1996-05-20 2008-05-13 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6989285B2 (en) 1996-05-20 2006-01-24 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6682954B1 (en) * 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
US7402902B2 (en) 1996-11-20 2008-07-22 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7812436B2 (en) 1996-11-20 2010-10-12 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7776652B2 (en) 1996-11-20 2010-08-17 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7109059B2 (en) 1996-11-20 2006-09-19 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7423339B2 (en) 1996-11-20 2008-09-09 Mircon Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7423338B2 (en) 1996-11-20 2008-09-09 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7282792B2 (en) 1996-11-20 2007-10-16 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US7411286B2 (en) 1996-11-20 2008-08-12 Micron Technology, Inc. Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6208018B1 (en) 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US6157080A (en) * 1997-11-06 2000-12-05 Sharp Kabushiki Kaisha Semiconductor device using a chip scale package
US6951774B2 (en) * 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US6593647B2 (en) * 2001-06-15 2003-07-15 Oki Electric Industry Co., Ltd. Semiconductor device
US7375419B2 (en) 2001-06-21 2008-05-20 Micron Technology, Inc. Stacked mass storage flash memory package
US7262506B2 (en) 2001-06-21 2007-08-28 Micron Technology, Inc. Stacked mass storage flash memory package
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US7704794B2 (en) 2001-06-21 2010-04-27 Micron Technology, Inc. Method of forming a semiconductor device
US7998792B2 (en) 2001-06-21 2011-08-16 Round Rock Research, Llc Semiconductor device assemblies, electronic devices including the same and assembly methods
US7999378B2 (en) 2001-06-21 2011-08-16 Round Rock Research, Llc Semiconductor devices including semiconductor dice in laterally offset stacked arrangement
US8049342B2 (en) 2001-06-21 2011-11-01 Round Rock Research, Llc Semiconductor device and method of fabrication thereof

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