JPS63100755A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63100755A JPS63100755A JP24682986A JP24682986A JPS63100755A JP S63100755 A JPS63100755 A JP S63100755A JP 24682986 A JP24682986 A JP 24682986A JP 24682986 A JP24682986 A JP 24682986A JP S63100755 A JPS63100755 A JP S63100755A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- semiconductor chip
- heat
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 230000017525 heat dissipation Effects 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract description 8
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000005855 radiation Effects 0.000 description 8
- 238000003780 insertion Methods 0.000 description 6
- 230000037431 insertion Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、放熱性に優れた絶縁型の半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an insulated semiconductor device with excellent heat dissipation.
（従来の技術）
従来、半導体装置は、例えば、第６図および第７図に示
すように、放熱板ａと外部リードｂとが一体に形成され
たリードフレームＣの表面に、半導体チップｄが直接載
置されるとともに、この半導体チップｄが載置された周
辺部分をモールド用樹脂ｅによって樹脂封止したものが
ある。そして、この半導体装置は、第８図に示すように
、取付ビスｇを放熱板ａに設けられたビス挿通孔ｉに挿
通して外付は放熱フィンｆの雌ネジ部に螺入することに
より外付は放熱フィンｆに取付けられる。その際、放熱
板ａに直接載置された半導体チップｄと外付は放熱フィ
ンｆとを絶縁するために、放熱板ａの裏面と外付は放熱
フィンｆとの間、および取付ビスｇの頭部とビス挿通孔
ｉの周縁部との間に絶縁体り、、ｈ、がそれぞれ介装さ
れる。(Prior Art) Conventionally, in a semiconductor device, a semiconductor chip d is mounted on the surface of a lead frame C in which a heat sink a and an external lead b are integrally formed, as shown in FIGS. 6 and 7, for example. There is one in which the semiconductor chip d is placed directly and the peripheral portion on which the semiconductor chip d is placed is sealed with a molding resin e. As shown in FIG. 8, this semiconductor device is assembled by inserting a mounting screw g into a screw insertion hole i provided in a heat sink plate a, and screwing the external screw into a female threaded portion of a heat sink f. The external part is attached to the heat radiation fin f. At this time, in order to insulate the semiconductor chip d placed directly on the heat sink a and the external heat sink f, the back surface of the heat sink a and the external heat sink are connected between the heat sink f and the mounting screw g. Insulators, h, are interposed between the head and the peripheral edge of the screw insertion hole i, respectively.
また、第９図および第１θ図に示すように、モールド樹
脂による樹脂封止の際にビス挿通孔ｉの周囲をも被覆し
、放熱板ａの裏面のみを露出させ、外付は放熱フィンｆ
への取付時に取付ビスｇの頭部とビス挿通孔ｉの周縁部
との間に介装されていた絶縁体ｈ８を不要にした半導体
装置があるが、放熱板ａの裏面が露出しているので、放
熱板ａの裏面と外付は放熱フィンｆとの間に絶縁体ｈ１
が介装される（第１１図参照）。In addition, as shown in FIG. 9 and FIG.
There is a semiconductor device that eliminates the need for the insulator h8 that was interposed between the head of the mounting screw g and the peripheral edge of the screw insertion hole i when it was attached to the device, but the back side of the heat sink a is exposed. Therefore, there is an insulator h1 between the back side of the heat sink a and the external heat sink f.
is inserted (see Figure 11).
さらに、近時、モールド用樹脂の熱伝導性の改良および
トランスファモールド技術の進歩によって、第１２図乃
至第１４図に示すように、放熱板ａの裏面も適宜厚さに
モールド樹脂ｅによって樹脂封止し、外付は放熱フィン
ｒへの取付けにあたって前述した絶縁体り、、ｈ、を廃
した半導体装置が提案されている。Furthermore, with recent improvements in the thermal conductivity of molding resins and advances in transfer molding technology, as shown in FIGS. A semiconductor device has been proposed in which the above-described insulators, h, and the like are eliminated when attaching the external heat dissipating fin r.
（発明が解決しようとする問題点）
しかしながら、第１２図乃至第１４図に示した半導体装
置において、放熱性を向上させる、すなわち外付は放熱
フィンへの熱伝導性を良くするためには、高熱伝導性樹
脂によって放熱板の裏面を被覆する樹脂の肉厚をできる
限り薄く形成すればよいが、高熱伝導性樹脂は成型性が
悪くなる傾向にあるため、トランスファモールド等にお
ける金型設計および成型方法に高度の技術が要求される
とともに、放熱板の裏面を被覆する樹脂の肉厚を薄くす
るには、機械的強度を維持する必要があるので成型技術
による限界があり、したがって熱伝導性の向上を図るに
も限界がある。(Problems to be Solved by the Invention) However, in the semiconductor device shown in FIGS. 12 to 14, in order to improve heat dissipation, that is, to improve heat conductivity to the external heat dissipation fins, It is best to make the resin that covers the back side of the heat sink with high thermal conductivity resin as thin as possible, but since high thermal conductivity resin tends to have poor moldability, mold design and molding in transfer molding, etc. The method requires advanced technology, and in order to reduce the thickness of the resin coating the back side of the heat sink, it is necessary to maintain mechanical strength, so there are limits to molding technology. There are limits to how much we can improve.
（問題点を解決するための手段）
本発明の半導体装置は、放熱性を有する金属板の上面に
絶縁層および回路形成用の導電層を順次ｔａ層してなる
基板上に半導体チップおよび外部リードが配設され、こ
れら導電層、半導体チップ、および外部リードが金属線
によって接続されるとともに前記基板の裏面のみが露出
するように樹脂封止されたものである。(Means for Solving the Problems) The semiconductor device of the present invention has a semiconductor chip and external leads on a substrate formed by sequentially forming an insulating layer and a conductive layer for forming a circuit on the upper surface of a metal plate having heat dissipation properties. The conductive layer, semiconductor chip, and external leads are connected by metal wires and sealed with resin so that only the back surface of the substrate is exposed.
（作用）
基板の表面に積層された絶縁層によって、基板を放熱フ
ィンに取付る際に、基板の裏面と放熱フィンとが当接し
ても、半導体チップと放熱フィンとは絶縁されており、
しかも、この絶縁層は積層基板として生成されることか
ら、従来の絶縁体や樹脂の肉厚に比べてはるかに薄く、
このため熱抵抗が低減される。(Function) Due to the insulating layer laminated on the surface of the substrate, even when the back surface of the substrate and the radiation fin come into contact when the substrate is attached to the radiation fin, the semiconductor chip and the radiation fin are insulated.
Moreover, since this insulating layer is produced as a laminated substrate, it is much thinner than conventional insulators or resins.
Therefore, thermal resistance is reduced.
（実施例）
以下、本発明の実施例について図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図および第２図は本発明の半導体装置を示している
。1 and 2 show a semiconductor device of the present invention.
基板ｌは、例えばアルミニウム等の金属板２の表面に絶
縁層３およびエツチング加工等により適宜な回路パター
ンに形成された導電層４を順次積層したものであり、こ
の基板ｌにはビス挿通孔１ａが形成されている。基板１
の導電１ｉ４上には半導体チップ５および予めリードフ
レーム状に形成された電極引出し用の外部リード６がろ
う付けされ、金属線７によって必要な配線が施されると
ともに樹脂により基板１の裏面のみが露出するように樹
脂封止されて外囲器８が形成されている。この外囲器８
には、ビス挿通孔１ａの周囲を被覆してなる通孔８ａが
形成されている。この樹脂封止は、例えばトランスファ
成型によって行われ、基板の裏面が露出するように形成
されており、金型設計および成型方法に高度の技術を要
求する必要がな（、容易に形成することができる。The substrate 1 is made by sequentially laminating an insulating layer 3 and a conductive layer 4 formed into an appropriate circuit pattern by etching or the like on the surface of a metal plate 2 made of, for example, aluminum.The substrate 1 has screw insertion holes 1a. is formed. Board 1
A semiconductor chip 5 and an external lead 6 for leading out electrodes formed in advance in the shape of a lead frame are brazed onto the conductive layer 1i4, and the necessary wiring is provided with metal wires 7, and only the back surface of the substrate 1 is covered with resin. An envelope 8 is formed by being sealed with resin so as to be exposed. This envelope 8
A through hole 8a is formed by covering the periphery of the screw insertion hole 1a. This resin sealing is performed, for example, by transfer molding, and is formed so that the back side of the substrate is exposed, and does not require advanced technology in mold design or molding method (it is easy to form). can.
上記のように構成された半導体装置は、第３図に示すよ
うに、ビスｌＯを挿通孔８ａに挿通し、放熱フィン１１
に形成された雌ネジ部１２に螺入することによって金属
板２の裏面が放熱フィン１１に当接した状態で取付固定
される。As shown in FIG. 3, in the semiconductor device configured as described above, the screw lO is inserted into the insertion hole 8a,
By screwing into the female screw portion 12 formed in the metal plate 2, the metal plate 2 is attached and fixed with the back side of the metal plate 2 in contact with the radiation fins 11.
これによって、半導体チップ５および外部リード６は金
属板２上に積層された絶縁層３を介して載置されている
ため、半導体チップ５と放熱フィン１１とは絶縁された
状態となる。As a result, since the semiconductor chip 5 and the external leads 6 are placed on the metal plate 2 with the insulating layer 3 interposed therebetween, the semiconductor chip 5 and the heat dissipation fins 11 are in an insulated state.
また、前記導電層３はエツチング加工により自由に回路
形成できるため、第４図に示すように、放熱を必要とす
る絶縁型ハイブリッド回路のパンケージにも適用できる
。なお、前記実施例と同部材には同符号を付している。Furthermore, since the conductive layer 3 can be freely etched to form a circuit, it can also be applied to a pancage of an insulated hybrid circuit that requires heat dissipation, as shown in FIG. Note that the same members as those in the above embodiment are given the same reference numerals.
（発明の効果）
以上述べたように、本発明の半導体装置は放熱フィンへ
の取付けにあたって従来必要であった絶縁体が全く不要
となり、熱伝導性に優れている。(Effects of the Invention) As described above, the semiconductor device of the present invention completely eliminates the need for an insulator, which was conventionally necessary, when attached to a radiation fin, and has excellent thermal conductivity.
しかも、半導体チップと放熱フィンとを絶縁する絶縁層
の厚さは積層基板として生成されるため、従来のように
、半導体チップと放熱フィンとを絶縁していた絶縁体や
樹脂に比べはるかに薄く形成することができ、放熱フィ
ンへの熱伝導性に優れている。Moreover, the thickness of the insulating layer that insulates the semiconductor chip and the heat dissipation fin is much thinner than the insulator or resin that insulates the semiconductor chip and the heat dissipation fin as in the past because it is produced as a laminated substrate. It has excellent thermal conductivity to the radiation fins.
第１図乃至第３図は本発明の半導体装置の一実施例を示
し、第１図は半導体装置の平面図、第２図は同断面図、
第３図は半導体装置を放熱フィンに取付けた状態を示す
断面図、第４図および第５図は本発明に係る半導体装置
の他の実施例を示し、第４図は樹脂封止前の半導体装置
の概略を示す平面図、第５図は同断面図、第６図乃至第
１４図は従来の半導体装置を示し、第６図は平面図、第
７図は断面図、第８図は放熱フィンへの取付状態を示す
断面図、第９図乃至第１１図は従来の他の半導体装置を
示し、第９図は平面図、第１Ｏ図は断面図、第１１図は
放熱フィンへの取付状態を示す断面図、第１２図乃至第
１４図は従来のさらに他の半導体装置を示し、第１２図
は平面図、第１３図は断面図、第１４図は放熱フィンへ
の取付状態を示す断面図である。
１・・・基板 ２・・・金属板３・・・絶
縁層 ４・・・導電層５・・・半導体チップ
６・・・外部リード８・・・外囲器1 to 3 show an embodiment of the semiconductor device of the present invention, FIG. 1 is a plan view of the semiconductor device, FIG. 2 is a sectional view thereof,
FIG. 3 is a sectional view showing a semiconductor device attached to a heat dissipation fin, FIGS. 4 and 5 show other embodiments of the semiconductor device according to the present invention, and FIG. 4 shows a semiconductor device before being sealed with resin. A plan view schematically showing the device, FIG. 5 is a sectional view of the same, FIGS. 6 to 14 show a conventional semiconductor device, FIG. 6 is a plan view, FIG. 7 is a sectional view, and FIG. 8 is a heat dissipation diagram. 9 to 11 show other conventional semiconductor devices, FIG. 9 is a plan view, FIG. 12 to 14 show still another conventional semiconductor device, FIG. 12 is a plan view, FIG. 13 is a sectional view, and FIG. 14 shows a state in which it is attached to a radiation fin. FIG. 1... Substrate 2... Metal plate 3... Insulating layer 4... Conductive layer 5... Semiconductor chip 6... External lead 8... Envelope
Claims (1)
成用の導電層を順次積層してなる基板上に半導体チップ
および外部リードが配設され、これら導電層、半導体チ
ップ、および外部リードが金属線によって接続されると
ともに前記基板の裏面のみが露出するように樹脂封止さ
れたことを特徴とする半導体装置。1) A semiconductor chip and external leads are arranged on a substrate formed by sequentially laminating an insulating layer and a conductive layer for forming a circuit on the upper surface of a metal plate having heat dissipation properties, and these conductive layers, semiconductor chip, and external leads are arranged on a substrate. 1. A semiconductor device, characterized in that the semiconductor device is connected by metal wires and is sealed with resin so that only the back surface of the substrate is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24682986A JPS63100755A (en) | 1986-10-16 | 1986-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24682986A JPS63100755A (en) | 1986-10-16 | 1986-10-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63100755A true JPS63100755A (en) | 1988-05-02 |
Family
ID=17154314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24682986A Pending JPS63100755A (en) | 1986-10-16 | 1986-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63100755A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0336753A (en) * | 1989-07-03 | 1991-02-18 | Sharp Corp | Semiconductor device |
-
1986
- 1986-10-16 JP JP24682986A patent/JPS63100755A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0336753A (en) * | 1989-07-03 | 1991-02-18 | Sharp Corp | Semiconductor device |
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