JP2002076259A - Power module - Google Patents

Power module

Info

Publication number
JP2002076259A
JP2002076259A JP2000256787A JP2000256787A JP2002076259A JP 2002076259 A JP2002076259 A JP 2002076259A JP 2000256787 A JP2000256787 A JP 2000256787A JP 2000256787 A JP2000256787 A JP 2000256787A JP 2002076259 A JP2002076259 A JP 2002076259A
Authority
JP
Japan
Prior art keywords
semiconductor chip
power module
electrode terminal
insulating case
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000256787A
Other languages
Japanese (ja)
Inventor
Mitsuharu Tabata
光晴 田畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000256787A priority Critical patent/JP2002076259A/en
Publication of JP2002076259A publication Critical patent/JP2002076259A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PROBLEM TO BE SOLVED: To realize a thin and lightweight power module, having low inductance in which an electrode terminal and a semiconductor chip can be connected in a short time and a fine structure formed on one side of the semiconductor chip will not be destructed. SOLUTION: A semiconductor chip 1 is bonded on the side provided with a fine structure to the lower surface of an electrode terminal 13a through solders 6a and 6b. The other side of the semiconductor chip 1 is bonded by compression to a conductor pattern 5a on the upper surface of an insulating substrate 4. Since the semiconductor chip 1 and the electrode terminal 13a can be connected, without having to use a bonding wire, connection can be made in a short time. When the bonding face between the semiconductor chip 1 and the electrode terminal 13a is enlarged, a thin and light-weight power module having a low inductance can be realized. Since solder bonding is employed, stresses hardly concentrate, even if a fine structure is formed on the upper surface of the semiconductor chip 1 and the fine structure is less likely to be destructed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、ＩＧＢＴ（Insu
lated Gate Bipolar Transistor）やパワーＭＯＳＦＥ
Ｔ（Metal Oxide Semiconductor Field Effect Transis
tor）などのように多数の微細構造（ゲート電極等）を
チップ片面に有する電力用半導体装置が形成された半導
体チップを実装したパワーモジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT (Insu
lated Gate Bipolar Transistor) and power MOSFE
T (Metal Oxide Semiconductor Field Effect Transis
The present invention relates to a power module mounted with a semiconductor chip on which a power semiconductor device having a large number of microstructures (gate electrodes and the like) on one side of the chip, such as tor).

【０００２】[0002]

【従来の技術】図３に従来のパワーモジュールの一例を
示す。このパワーモジュールにおいては、絶縁基板４上
に半導体チップ１が配置されている。半導体チップ１内
には、ＩＧＢＴやパワーＭＯＳＦＥＴ等の電力用半導体
装置が形成されている。例えば半導体チップ１内にＩＧ
ＢＴを形成する場合、半導体チップ１の下面にはコレク
タ電極が形成され、半導体チップ１の上面にはゲート電
極とエミッタ電極とが形成されることがある。その場
合、オン抵抗の低減を図るなどの目的で、上面のゲート
電極およびエミッタ電極は微細構造とされ、複数設けら
れることが多い。一方、コレクタ電極は各ゲート電極お
よび各エミッタ電極に対して共通とされ、下面全体が一
つの電極とされることが多い。2. Description of the Related Art FIG. 3 shows an example of a conventional power module. In this power module, a semiconductor chip 1 is arranged on an insulating substrate 4. In the semiconductor chip 1, a power semiconductor device such as an IGBT or a power MOSFET is formed. For example, in the semiconductor chip 1 IG
When the BT is formed, a collector electrode may be formed on the lower surface of the semiconductor chip 1, and a gate electrode and an emitter electrode may be formed on the upper surface of the semiconductor chip 1. In such a case, the gate electrode and the emitter electrode on the upper surface have a fine structure and are often provided in plural for the purpose of reducing the on-resistance and the like. On the other hand, the collector electrode is common to each gate electrode and each emitter electrode, and the entire lower surface is often one electrode.

【０００３】さて、絶縁基板４の上面および下面にはそ
れぞれ導体パターン５ａ，５ｂが形成されている。そし
て、半導体チップ１の下面がハンダ６ｄにより導体パタ
ーン５ａ上に固着される。また、導体パターン５ｂは絶
縁基板４の下面全面に形成され、ハンダ６ｃにより放熱
用の剛体熱伝導板７上に固着されている。剛体熱伝導板
７は、樹脂等を型に流し込んで形成した絶縁性ケース８
ｃにネジ１５により固着される。なお、剛体熱伝導板７
には、熱伝導性の高い金属板などを用いればよいが、板
状のものに限らず放熱フィンタイプのものを用いてもよ
い。[0003] On the upper and lower surfaces of the insulating substrate 4, conductor patterns 5a and 5b are formed, respectively. Then, the lower surface of the semiconductor chip 1 is fixed on the conductor pattern 5a by the solder 6d. The conductor pattern 5b is formed on the entire lower surface of the insulating substrate 4 and is fixed on the rigid heat-conducting plate 7 for heat dissipation by solder 6c. The rigid heat conductive plate 7 is made of an insulating case 8 formed by pouring a resin or the like into a mold.
and c. The rigid heat conductive plate 7
For example, a metal plate having high heat conductivity may be used, but not limited to a plate-shaped one, and a radiation fin type may be used.

【０００４】絶縁性ケース８ｃには、一枚の導体板から
打ち抜かれ適当に曲げられた電極端子１３ｂが固定され
ている。なお、電極端子１３ｂの一端は絶縁性ケース８
ｃの上部外壁部分に露出し、他端は絶縁性ケース８ｃの
内壁部分に露出している。また、ナット１２が絶縁性ケ
ース８ｃ内に固定され、電極端子１３ｂの一端に接続さ
れている。電極端子１３ｂの一端にはネジ穴１４が設け
られており、ネジ穴１４はナット１２のネジ穴に連通し
ている。このネジ穴１４に外部からネジ（図示せず）が
挿入され、ナット１２に螺合されることで、外部機器の
端子（図示せず）が電極端子１３ｂに接続、固定され
る。An electrode case 13b punched out of a single conductive plate and bent appropriately is fixed to the insulating case 8c. One end of the electrode terminal 13b is connected to the insulating case 8
c is exposed to the upper outer wall portion, and the other end is exposed to the inner wall portion of the insulating case 8c. Further, the nut 12 is fixed in the insulating case 8c, and is connected to one end of the electrode terminal 13b. A screw hole 14 is provided at one end of the electrode terminal 13b, and the screw hole 14 communicates with a screw hole of the nut 12. A screw (not shown) is externally inserted into the screw hole 14 and screwed into the nut 12, whereby a terminal (not shown) of the external device is connected to and fixed to the electrode terminal 13b.

【０００５】一方、電極端子１３ｂの他端には、ボンデ
ィングワイヤ１８を介して半導体チップ１の上面の一部
（例えばＩＧＢＴのゲート電極）が接続されている。On the other hand, a part of the upper surface of the semiconductor chip 1 (for example, an IGBT gate electrode) is connected to the other end of the electrode terminal 13b via a bonding wire 18.

【０００６】[0006]

【発明が解決しようとする課題】図３に示した従来のパ
ワーモジュールにおいては、半導体チップ１の上面と電
極端子１３ｂとの接続にボンディングワイヤ１８を用い
ている。パワーモジュールの動作時に剛体熱伝導板７と
絶縁性ケース８ｃとがそれぞれの熱膨張率で熱膨張し、
電極端子１３ｂと半導体チップ１との間の距離に変化が
生じたとしても、ボンディングワイヤ１８を用いること
により、確実に電極端子１３ｂと半導体チップ１との接
続を維持することができる。In the conventional power module shown in FIG. 3, bonding wires 18 are used to connect the upper surface of the semiconductor chip 1 to the electrode terminals 13b. During operation of the power module, the rigid thermal conductive plate 7 and the insulating case 8c thermally expand at respective thermal expansion coefficients,
Even when the distance between the electrode terminal 13b and the semiconductor chip 1 changes, the connection between the electrode terminal 13b and the semiconductor chip 1 can be reliably maintained by using the bonding wire 18.

【０００７】しかし、このようにボンディングワイヤを
採用する構造では、ボンディングワイヤの断面積が小さ
いためにボンディングワイヤ１８の自己インダクタンス
の値が大きくなり、電流を短時間で停止させることが困
難になるという問題が生じる。However, in such a structure employing a bonding wire, the value of the self-inductance of the bonding wire 18 increases because the cross-sectional area of the bonding wire is small, and it is difficult to stop the current in a short time. Problems arise.

【０００８】ボンディングワイヤ１８の断面積を大きく
すれば自己インダクタンスの値を低く抑えることが可能
となるが、その場合、単位応力あたりの弾性変形量が小
さくなり、ボンディングワイヤ１８が曲がりにくくな
る。すると、電極端子１３ｂと半導体チップ１との接続
を確実に維持することが困難となる場合がある。If the cross-sectional area of the bonding wire 18 is increased, the value of the self-inductance can be reduced. In this case, however, the amount of elastic deformation per unit stress is reduced, and the bonding wire 18 is hardly bent. Then, it may be difficult to reliably maintain the connection between the electrode terminals 13b and the semiconductor chip 1.

【０００９】よって、断面積を大きくしつつ単位応力あ
たりの弾性変形量を大きく保つためには、ボンディング
ワイヤ１８を長くしなくてはならない。すると、例えば
図３において、ボンディングワイヤ１８の形状がより大
きな山形のカーブを描く必要が生じる。そのため、パワ
ーモジュールの厚み方向のコンパクトさが損なわれやす
い。Accordingly, in order to increase the amount of elastic deformation per unit stress while increasing the cross-sectional area, the bonding wire 18 must be lengthened. Then, for example, in FIG. 3, the shape of the bonding wire 18 needs to draw a larger chevron curve. Therefore, the compactness of the power module in the thickness direction is easily damaged.

【００１０】また、パワーモジュール用のボンディング
ワイヤには導電性およびコストに優れるＡｌが採用され
ることが多いが、Ａｌワイヤボンディングの場合、金線
ワイヤボンディングの場合と異なり溶融接着に時間がか
かり（１箇所の接合につき１秒程度）、製造に要する時
間が多大であった。In addition, Al, which is excellent in conductivity and cost, is often used for bonding wires for power modules. However, in the case of Al wire bonding, unlike the case of gold wire bonding, it takes a long time to melt and bond ( About 1 second per one joint), the time required for manufacturing was enormous.

【００１１】そこで、絶縁性ケース内の電極端子と半導
体チップとの接続が短時間で済み、しかもインダクタン
スの値が小さい軽量薄型のパワーモジュールの実現が望
まれる。Therefore, it is desired to realize a lightweight and thin power module that requires only a short connection between the electrode terminals in the insulating case and the semiconductor chip and has a small inductance value.

【００１２】そのようなパワーモジュールとして例え
ば、半導体チップの上下面にそれぞれ電極端子や絶縁基
板を圧接して、絶縁性ケースおよび剛体熱伝導板で保持
するタイプのものが存在する。このタイプの場合、半導
体チップは圧接されるので、圧接面積を大きくすること
でインダクタンスの低減を図ることができる。また、ワ
イヤボンディングを行わないので、軽量薄型となり、製
造に要する時間も少なくてすむ。As such a power module, for example, there is a type in which electrode terminals and an insulating substrate are pressed against upper and lower surfaces of a semiconductor chip, respectively, and held by an insulating case and a rigid heat conductive plate. In this type, since the semiconductor chip is pressed, the inductance can be reduced by increasing the pressed area. Further, since wire bonding is not performed, the weight and thickness are reduced, and the time required for manufacturing is reduced.

【００１３】ところが、このような圧接の場合には、パ
ワーモジュール動作時に剛体熱伝導板と絶縁性ケースと
がそれぞれの熱膨張率で熱膨張して、半導体チップと電
極端子等との圧接面に水平方向の応力が生じた際に、圧
接面の位置ずれが生じやすい。この位置ずれは、圧接力
を増加させることで抑制しうるが、パワーモジュールに
おいて圧接力を増加させることは困難である。上述のよ
うに、半導体チップの片面にはＩＧＢＴのゲート電極お
よびエミッタ電極のような微細構造が形成されているこ
とが多く、これら微細構造を破壊しないように厚み方向
の圧接力に制限が加わるからである。However, in the case of such a pressure contact, the rigid heat conductive plate and the insulating case thermally expand at the respective thermal expansion coefficients during the operation of the power module, so that the pressure contact surface between the semiconductor chip and the electrode terminal or the like is formed. When horizontal stress is generated, displacement of the press contact surface is likely to occur. This displacement can be suppressed by increasing the pressing force, but it is difficult to increase the pressing force in the power module. As described above, a fine structure such as an IGBT gate electrode and an emitter electrode is often formed on one surface of a semiconductor chip, and the pressing force in the thickness direction is limited so as not to destroy these fine structures. It is.

【００１４】したがって、圧接型のパワーモジュールに
おいては水平方向の応力を充分に抑制することができな
い。圧接面の位置ずれが生じると、例えばＩＧＢＴのゲ
ート電極およびエミッタ電極のような各電極への導通が
正しく行われなくなる可能性がある。また、圧接力が弱
いと圧接面における電気抵抗を十分に低減することがで
きないという問題もある。Therefore, in the pressure welding type power module, horizontal stress cannot be sufficiently suppressed. When the displacement of the press contact surface occurs, there is a possibility that conduction to each electrode such as the gate electrode and the emitter electrode of the IGBT may not be performed properly. In addition, there is also a problem that if the pressing force is weak, the electric resistance on the pressing surface cannot be sufficiently reduced.

【００１５】これらの問題の解決を目的として圧接力を
増大させるためには、半導体チップ表面の微細構造を破
壊に耐えうるよう大きくすることが必要となるが、それ
では半導体チップの電気特性を犠牲にすることになる。In order to increase the pressure contact force for the purpose of solving these problems, it is necessary to increase the fine structure on the surface of the semiconductor chip so as to withstand destruction, but at the expense of the electrical characteristics of the semiconductor chip. Will do.

【００１６】そこで、この発明の課題は、電極端子と半
導体チップとの接続が短時間で済み、しかもインダクタ
ンスの値が小さい軽量薄型のパワーモジュールであっ
て、かつ、半導体チップの片面に形成された微細構造を
破壊しないものを実現することにある。Accordingly, an object of the present invention is to provide a lightweight and thin power module that requires only a short connection between the electrode terminals and the semiconductor chip, has a small inductance value, and is formed on one surface of the semiconductor chip. An object of the present invention is to realize a structure that does not destroy a fine structure.

【００１７】[0017]

【課題を解決するための手段】請求項１に記載の発明
は、上面と下面とを有し、電力用半導体装置が形成され
た半導体チップと、前記半導体チップを収容する絶縁性
ケースと、前記絶縁性ケースに固定され、前記絶縁性ケ
ース外に露出した一端と前記絶縁性ケース内に露出した
他端とを有する電極端子と、前記絶縁性ケースに接合さ
れる放熱用部材と、前記半導体チップの前記下面が載置
される導体パターンが形成された上面、および前記放熱
用部材上に載置される下面を有する絶縁基板とを備え、
前記電極端子の前記他端は上面と下面とを有し、その上
面および下面が前記絶縁基板の前記上面および下面に対
して平行に前記絶縁性ケース内に延在しており、前記半
導体チップの前記上面の少なくとも一部が導電性接着剤
により前記電極端子の前記他端の前記下面に接合され、
前記半導体チップの前記下面と前記絶縁基板の前記導体
パターンとが、および／または、前記絶縁基板の前記下
面と前記放熱用部材とが圧接されたパワーモジュールで
ある。According to a first aspect of the present invention, there is provided a semiconductor chip having an upper surface and a lower surface, on which a power semiconductor device is formed, an insulating case for housing the semiconductor chip, An electrode terminal fixed to the insulating case and having one end exposed outside the insulating case and the other end exposed inside the insulating case; a heat dissipating member joined to the insulating case; and the semiconductor chip Comprising an upper surface on which a conductor pattern on which the lower surface is mounted is formed, and an insulating substrate having a lower surface mounted on the heat dissipation member,
The other end of the electrode terminal has an upper surface and a lower surface, and the upper surface and the lower surface extend in the insulating case in parallel to the upper surface and the lower surface of the insulating substrate, and At least a portion of the upper surface is joined to the lower surface of the other end of the electrode terminal by a conductive adhesive,
A power module in which the lower surface of the semiconductor chip and the conductor pattern of the insulating substrate and / or the lower surface of the insulating substrate and the heat dissipation member are pressed against each other.

【００１８】請求項２に記載の発明は、請求項１に記載
のパワーモジュールであって、前記電極端子の前記他端
はその前記上面および下面の垂直方向に弾性変形するパ
ワーモジュールである。According to a second aspect of the present invention, there is provided the power module according to the first aspect, wherein the other end of the electrode terminal is elastically deformed in a vertical direction of the upper surface and the lower surface thereof.

【００１９】請求項３に記載の発明は、請求項１に記載
のパワーモジュールであって、前記半導体チップの前記
上面の少なくとも一部と前記電極端子の前記他端の前記
下面との間に介在する導電性のスペーサと、前記電極端
子の前記他端の前記下面のうち前記スペーサの介在する
部分の周囲に形成された絶縁膜とをさらに備えるパワー
モジュールである。The invention according to claim 3 is the power module according to claim 1, wherein the power module is interposed between at least a part of the upper surface of the semiconductor chip and the lower surface of the other end of the electrode terminal. A power module further comprising: a conductive spacer to be formed; and an insulating film formed around a portion of the lower surface of the other end of the electrode terminal where the spacer intervenes.

【００２０】請求項４に記載の発明は、請求項１に記載
のパワーモジュールであって、前記電極端子の前記他端
の前記下面のうち前記半導体チップの前記上面が接合さ
れた部分に対向する前記他端の前記上面と前記絶縁性ケ
ースとの間に介在する弾性体をさらに備えるパワーモジ
ュールである。According to a fourth aspect of the present invention, in the power module according to the first aspect, the lower surface of the other end of the electrode terminal is opposed to a portion where the upper surface of the semiconductor chip is joined. The power module further includes an elastic body interposed between the upper surface of the other end and the insulating case.

【００２１】請求項５に記載の発明は、請求項４に記載
のパワーモジュールであって、前記絶縁性ケースのうち
前記弾性体の介在する部分は、着脱可能な蓋状部分とな
っているパワーモジュールである。According to a fifth aspect of the present invention, there is provided the power module according to the fourth aspect, wherein a portion of the insulating case where the elastic body is interposed is a detachable lid-like portion. Module.

【００２２】[0022]

【発明の実施の形態】＜実施の形態１＞図１は、この発
明の実施の形態１に係るパワーモジュールを示す図であ
る。図１に示すように、このパワーモジュールは、図３
に示した従来の技術と同様、ＩＧＢＴやパワーＭＯＳＦ
ＥＴ等の電力用半導体装置が形成された半導体チップ１
と、上面および下面にそれぞれ導体パターン５ａ，５ｂ
が形成された絶縁基板４と、放熱用の剛体熱伝導板７と
を備えている。そして、導体パターン５ｂが絶縁基板４
の下面全面に形成され、ハンダ６ｃにより放熱用の剛体
熱伝導板７上に固着されている。<First Embodiment> FIG. 1 is a diagram showing a power module according to a first embodiment of the present invention. As shown in FIG. 1, this power module
IGBT and power MOSF as in the prior art shown in FIG.
Semiconductor chip 1 on which a power semiconductor device such as ET is formed
And conductor patterns 5a and 5b on the upper and lower surfaces, respectively.
Are provided, and a rigid heat conducting plate 7 for heat dissipation is provided. Then, the conductor pattern 5b is
And is fixed on a rigid heat conducting plate 7 for heat radiation by solder 6c.

【００２３】なお、剛体熱伝導板７には、熱伝導性の高
い金属板などを用いればよいが、板状のものに限らず放
熱フィンタイプのものを用いてもよい。The rigid heat conductive plate 7 may be a metal plate or the like having high heat conductivity, but is not limited to a plate-shaped one and may be a radiating fin type.

【００２４】また、半導体チップ１の上面には、図３に
示した従来の技術と同様、例えばＩＧＢＴのゲート電極
およびエミッタ電極のような微細構造が設けられてい
る。一方、半導体チップ１の下面は、図３に示した従来
の技術と同様、例えばＩＧＢＴのコレクタ電極のように
全体として一つの電極となっている。On the upper surface of the semiconductor chip 1, a fine structure such as a gate electrode and an emitter electrode of an IGBT is provided, as in the conventional technique shown in FIG. On the other hand, the lower surface of the semiconductor chip 1 is one electrode as a whole, for example, a collector electrode of an IGBT, as in the conventional technique shown in FIG.

【００２５】ただし、このパワーモジュールにおいて
は、図３に示した従来の技術と異なり、半導体チップ１
の下面は絶縁基板４上面の導体パターン５ａにハンダ付
けされていない。半導体チップ１の下面と絶縁基板４の
上面とは、圧接により接合される。However, in this power module, unlike the prior art shown in FIG.
Is not soldered to the conductor pattern 5a on the upper surface of the insulating substrate 4. The lower surface of the semiconductor chip 1 and the upper surface of the insulating substrate 4 are joined by pressure welding.

【００２６】さて、本実施の形態に係るパワーモジュー
ルは、樹脂等を型に流し込んで形成した絶縁性ケース８
ａを備える。この絶縁性ケース８ａは、半導体チップ１
を収容する箱型形状となっており、その上部には着脱可
能な蓋状部分１１が設けられている。そして、剛体熱伝
導板７および絶縁性ケース８ａに設けられたネジ穴９
ａ，９ｂにネジ１５が螺合されることで、剛体熱伝導板
７が絶縁性ケース８ａに固着される。The power module according to the present embodiment has an insulating case 8 formed by pouring resin or the like into a mold.
a. This insulating case 8a is used for the semiconductor chip 1
And a removable lid-like portion 11 is provided on the upper part thereof. Screw holes 9 provided in the rigid heat conductive plate 7 and the insulating case 8a
The screw 15 is screwed into the a and 9b, whereby the rigid heat conductive plate 7 is fixed to the insulating case 8a.

【００２７】絶縁性ケース８ａには、一枚の導体板から
打ち抜かれ適当に曲げられた電極端子１３ａが固定され
ている。なお、電極端子１３ａの一端は絶縁性ケース８
ａの上部外壁部分に露出し、他端は絶縁性ケース８ａの
内壁部分に露出している。そして、電極端子１３ａの他
端は、その上面および下面が絶縁基板４の上面および下
面に対して平行に絶縁性ケース８ａ内に延在している。
なお、電極端子１３ａの他端が、その上面および下面の
垂直方向に弾性変形するよう、電極端子１３ａの材料と
して適当なものを選んでおくことが望ましい。An electrode case 13a punched out of one conductor plate and bent appropriately is fixed to the insulating case 8a. One end of the electrode terminal 13a is connected to the insulating case 8
a is exposed to the upper outer wall portion, and the other end is exposed to the inner wall portion of the insulating case 8a. The other end of the electrode terminal 13a has an upper surface and a lower surface extending in the insulating case 8a in parallel with the upper surface and the lower surface of the insulating substrate 4.
It is desirable to select an appropriate material for the electrode terminal 13a so that the other end of the electrode terminal 13a is elastically deformed in the vertical direction of the upper and lower surfaces thereof.

【００２８】また、ナット１２が絶縁性ケース８ａ内に
固定され、電極端子１３ａの一端に接続されている。電
極端子１３ａの一端にはネジ穴１４が設けられており、
ネジ穴１４はナット１２のネジ穴に連通している。この
ネジ穴１４に外部からネジ（図示せず）が挿入され、ナ
ット１２に螺合されることで、外部機器の端子（図示せ
ず）が電極端子１３ａに接続、固定される。The nut 12 is fixed in the insulating case 8a and connected to one end of the electrode terminal 13a. A screw hole 14 is provided at one end of the electrode terminal 13a,
The screw hole 14 communicates with the screw hole of the nut 12. A screw (not shown) is inserted into the screw hole 14 from the outside, and screwed to the nut 12, whereby a terminal (not shown) of the external device is connected to and fixed to the electrode terminal 13a.

【００２９】一方、電極端子１３ａの他端の下面には、
ハンダ６ａ，６ｂのような導電性接着剤を介して半導体
チップ１の上面の一部（例えばＩＧＢＴのゲート電極）
が接合される。なお、半導体チップ１の上面および下面
には、接着や圧接を行うための導体箔２ａ，２ｂが形成
されている。On the other hand, on the lower surface of the other end of the electrode terminal 13a,
Part of the upper surface of the semiconductor chip 1 (for example, an IGBT gate electrode) via a conductive adhesive such as solder 6a, 6b
Are joined. Note that conductive foils 2a and 2b for performing bonding and pressure contact are formed on the upper and lower surfaces of the semiconductor chip 1, respectively.

【００３０】また、ここでは、電極端子１３ａの他端と
半導体チップ１との間に導電性のスペーサ３を介在させ
ている。そのため、導体箔２ｂとスペーサ３とがハンダ
６ａにより接合され、スペーサ３と電極端子１３ａとが
ハンダ６ｂにより接合されている。なお、スペーサ３の
機能については後述する。Here, a conductive spacer 3 is interposed between the other end of the electrode terminal 13a and the semiconductor chip 1. Therefore, the conductor foil 2b and the spacer 3 are joined by the solder 6a, and the spacer 3 and the electrode terminal 13a are joined by the solder 6b. The function of the spacer 3 will be described later.

【００３１】さらに、電極端子１３ａ他端の下面のうち
スペーサ３の介在する部分の周囲には、絶縁膜１６が形
成されている。この絶縁膜１６の機能についても後述す
る。Further, an insulating film 16 is formed on the lower surface of the other end of the electrode terminal 13a around the portion where the spacer 3 is interposed. The function of the insulating film 16 will also be described later.

【００３２】また、電極端子１３ａ他端の下面のうち半
導体チップ１の上面が接合された部分に対向する電極端
子１３ａ他端の上面と絶縁性ケース８ａの蓋状部分１１
との間には弾性体１０を介在させている。The lower surface of the other end of the electrode terminal 13a is opposed to the upper surface of the other end of the electrode terminal 13a opposite to the portion to which the upper surface of the semiconductor chip 1 is joined.
And an elastic body 10 is interposed between them.

【００３３】なお、半導体チップ１に形成する電力用半
導体装置としてパワーダイオード等の２端子素子を採用
する場合は、半導体チップ１の上面全体が一方の電極を
構成し、下面全体が他方の電極を構成するので、半導体
チップ１の上面の全部を電極端子１３ａの他端の下面に
接合するようにしてもよい。When a two-terminal element such as a power diode is used as a power semiconductor device formed on the semiconductor chip 1, the entire upper surface of the semiconductor chip 1 constitutes one electrode and the entire lower surface constitutes the other electrode. With this configuration, the entire upper surface of the semiconductor chip 1 may be joined to the lower surface of the other end of the electrode terminal 13a.

【００３４】また、半導体チップ１の上面の他の一部
（例えばＩＧＢＴのエミッタ電極）についても、上記と
同様に、絶縁ケース８ａに固定された他の電極端子（図
示せず）に接合するようにすればよい。Further, another part of the upper surface of the semiconductor chip 1 (for example, an emitter electrode of an IGBT) is joined to another electrode terminal (not shown) fixed to the insulating case 8a in the same manner as described above. What should I do?

【００３５】本実施の形態に係るパワーモジュールにお
いては、剛体熱伝導板７をネジ１５によって絶縁性ケー
ス８ａに接合するときの圧接力を利用して、絶縁基板４
上の導体パターン５ａと半導体チップ１の下面の導体箔
２ａとの圧接を行う。なお、半導体チップ１と絶縁基板
４上の導体パターン５ａとが圧接されるように、各部の
厚みは予め設計されている。In the power module according to the present embodiment, the insulating substrate 4 is utilized by utilizing the pressing force when the rigid heat conductive plate 7 is joined to the insulating case 8a by the screw 15.
The upper conductor pattern 5a and the conductor foil 2a on the lower surface of the semiconductor chip 1 are pressed. The thickness of each part is designed in advance so that the semiconductor chip 1 and the conductor pattern 5a on the insulating substrate 4 are pressed against each other.

【００３６】このように半導体チップ１の上面がハンダ
等の導電性接着剤により電極端子１３ａの他端の下面に
接合され、半導体チップ１の下面と絶縁基板４の導体パ
ターン５ａとが圧接されるので、ボンディングワイヤを
用いることなく半導体チップ１と電極端子１３ａとを接
続でき、軽量薄型のパワーモジュールを実現できる。As described above, the upper surface of the semiconductor chip 1 is joined to the lower surface of the other end of the electrode terminal 13a by a conductive adhesive such as solder, and the lower surface of the semiconductor chip 1 is pressed against the conductor pattern 5a of the insulating substrate 4. Therefore, the semiconductor chip 1 and the electrode terminals 13a can be connected without using a bonding wire, and a light and thin power module can be realized.

【００３７】また、ボンディングワイヤを用いないこと
から、電極端子１３ａと半導体チップ１との接続が短時
間で済む。Since no bonding wire is used, the connection between the electrode terminals 13a and the semiconductor chip 1 can be completed in a short time.

【００３８】また、半導体チップ１と電極端子１３ａと
の接合面を大きくとることで、インダクタンスの値が小
さいパワーモジュールを実現できる。Further, by increasing the bonding surface between the semiconductor chip 1 and the electrode terminals 13a, a power module having a small inductance value can be realized.

【００３９】さらに、パワーモジュール動作時に剛体熱
伝導板７と絶縁性ケース８ａとがそれぞれの熱膨張率で
熱膨張して、半導体チップ１に水平方向の応力が生じた
としても、半導体チップ１の上面についてはハンダ６
ａ，６ｂにより（スペーサ３を介在させつつ）電極端子
１３ａの他端に接合されているので、ハンダ６ａが半導
体チップ１の上面と電極端子１３ａの他端の下面との間
の隙間を充填して半導体チップ１の上面に集中応力を発
生させにくい。よって、半導体チップ１の上面に微細構
造を形成しておけば、微細構造の破壊が起こりにくく、
半導体チップ１の微細構造への制約を軽減できる。Further, even when the rigid thermal conductive plate 7 and the insulating case 8a thermally expand at the respective thermal expansion rates during the operation of the power module, and horizontal stress is generated in the semiconductor chip 1, Solder 6 on top
The solder 6a fills the gap between the upper surface of the semiconductor chip 1 and the lower surface of the other end of the electrode terminal 13a because it is joined to the other end of the electrode terminal 13a (with the spacer 3 interposed) by a and 6b. Therefore, concentrated stress is not easily generated on the upper surface of the semiconductor chip 1. Therefore, if a fine structure is formed on the upper surface of the semiconductor chip 1, the fine structure is less likely to break down,
Restrictions on the fine structure of the semiconductor chip 1 can be reduced.

【００４０】また、水平方向の応力は、半導体チップ１
の下面の圧接部分が受けることになるが、ＩＧＢＴのコ
レクタ電極のように半導体チップ１の下面に微細構造が
形成されていなければ、半導体チップ１の下面と導体パ
ターン５ａとの間で多少の位置ずれが生じたとしても問
題はない。The horizontal stress is applied to the semiconductor chip 1.
Of the lower surface of the semiconductor chip 1 such that the fine structure is not formed on the lower surface of the semiconductor chip 1 like the collector electrode of the IGBT. There is no problem even if the displacement occurs.

【００４１】また、半導体チップ１のうち圧接されるの
は下面だけであるので、半導体チップ１の上下面共に圧
接する従来の場合に比べ、圧接数を減らしたことにより
比較的少ない圧接力でも圧接面での電気抵抗を低くする
ことができる。またさらに、圧接力を得るための絶縁性
ケース８ａの剛性を少なく見積もることも可能となる。Further, since only the lower surface of the semiconductor chip 1 is pressed against the semiconductor chip 1, compared with the conventional case where both the upper and lower surfaces of the semiconductor chip 1 are pressed against each other, the number of press-contacts is reduced, so that a relatively small pressing force is applied. Surface electrical resistance can be reduced. Further, it is possible to estimate the rigidity of the insulating case 8a for obtaining the pressure contact force with a small value.

【００４２】さらに電極端子１３ａの他端がその上面お
よび下面の垂直方向に弾性変形するので、半導体チップ
１の下面と絶縁基板４の導体パターン５ａとの圧接の際
に、半導体チップ１にかかる圧接力を電極端子１３ａに
逃がすことができ、半導体チップ１に形成された微細構
造の破壊がより起こりにくく、半導体チップ１の微細構
造への制約を軽減できる。Further, since the other end of the electrode terminal 13a is elastically deformed in the vertical direction of the upper and lower surfaces thereof, when the lower surface of the semiconductor chip 1 is pressed against the conductor pattern 5a of the insulating substrate 4, the pressure applied to the semiconductor chip 1 is reduced. The force can be released to the electrode terminals 13a, and the fine structure formed on the semiconductor chip 1 is less likely to be broken, and the restriction on the fine structure of the semiconductor chip 1 can be reduced.

【００４３】また、本実施の形態に係るパワーモジュー
ルにおいては、電極端子１３ａの他端と半導体チップ１
との間に導電性のスペーサ３を介在させ、さらに、電極
端子１３ａ他端の下面のうちスペーサ３の介在する部分
の周囲に絶縁膜１６を形成している。この理由について
以下に述べる。In the power module according to this embodiment, the other end of the electrode terminal 13a and the semiconductor chip 1
And a conductive spacer 3 is interposed therebetween, and an insulating film 16 is formed on the lower surface of the other end of the electrode terminal 13a around the portion where the spacer 3 is interposed. The reason will be described below.

【００４４】半導体チップ１に電力用半導体装置を形成
すると、半導体チップ１の側面近傍は高電圧となりやす
い。特にＩＧＢＴやパワーＭＯＳＦＥＴ等を形成する場
合は、半導体チップ１の上面のゲート電極およびエミッ
タ電極（またはソース電極）は低電圧であるが、半導体
チップ１の下面のコレクタ電極（またはドレイン電極）
は高電圧となる（ＮＭＯＳ型の場合、なおＰＭＯＳ型の
場合はマイナス方向に高電圧となる）。この半導体チッ
プ１の下面の高電圧が、半導体チップ１の側面や半導体
チップ１の上面の外周部分近傍の電界に影響を与え、こ
れらの部分を高電圧にしてしまう。この場合、半導体チ
ップ１の側面にシリコンゴム製のリングを設けたり、半
導体チップ１の上面の外周部分に酸化膜を設けるなどし
て、電極端子１３ａの他端との間での耐圧を確保する
（絶縁距離を確保する）。When a power semiconductor device is formed on the semiconductor chip 1, the vicinity of the side surface of the semiconductor chip 1 tends to have a high voltage. In particular, when an IGBT, a power MOSFET, or the like is formed, the gate electrode and the emitter electrode (or source electrode) on the upper surface of the semiconductor chip 1 have a low voltage, but the collector electrode (or drain electrode) on the lower surface of the semiconductor chip 1.
Becomes a high voltage (in the case of the NMOS type, in the case of the PMOS type, the voltage becomes high in the negative direction). The high voltage on the lower surface of the semiconductor chip 1 affects the electric field in the vicinity of the side surface of the semiconductor chip 1 and the outer peripheral portion of the upper surface of the semiconductor chip 1, so that these portions are made high voltage. In this case, a silicon rubber ring is provided on the side surface of the semiconductor chip 1 or an oxide film is provided on the outer peripheral portion of the upper surface of the semiconductor chip 1 to secure a withstand voltage between the other end of the electrode terminal 13a. (Ensure insulation distance).

【００４５】しかし、半導体チップ１の下面に与える電
圧が非常に高い電圧になると、これらの対策だけでは充
分ではない場合も考えられる。そこで、スペーサ３およ
び絶縁膜１６を形成するのである。スペーサ３を設ける
ことで、半導体チップ１と電極端子１３ａとの間の距離
を増加させることができ、絶縁距離を大きくすることが
できる。また、絶縁膜１６を形成することで、半導体チ
ップ１の側面や上面外周部分と電極端子１３ａとの間の
耐圧性を高めることができる。However, if the voltage applied to the lower surface of the semiconductor chip 1 becomes a very high voltage, it may be considered that these measures alone are not sufficient. Therefore, the spacer 3 and the insulating film 16 are formed. By providing the spacer 3, the distance between the semiconductor chip 1 and the electrode terminal 13a can be increased, and the insulation distance can be increased. In addition, by forming the insulating film 16, the withstand voltage between the electrode terminal 13a and the outer peripheral portion of the side surface or the upper surface of the semiconductor chip 1 can be increased.

【００４６】このように、本実施の形態に係るパワーモ
ジュールはスペーサ３と絶縁膜１６とをさらに備えるの
で、半導体チップ１の上面に低圧となる部分が形成さ
れ、半導体チップ１の下面に高圧となる部分が形成され
た場合に、高圧となりやすい半導体チップ１の側面近傍
と電極端子１３ａとの間の絶縁距離を増加させることが
でき、耐電圧に優れたパワーモジュールを実現できる。As described above, since the power module according to the present embodiment further includes the spacer 3 and the insulating film 16, a low voltage portion is formed on the upper surface of the semiconductor chip 1, and the high voltage portion is formed on the lower surface of the semiconductor chip 1. When such a portion is formed, it is possible to increase the insulation distance between the vicinity of the side surface of the semiconductor chip 1, which is likely to be high in voltage, and the electrode terminal 13 a, thereby realizing a power module having excellent withstand voltage.

【００４７】また、本実施の形態に係るパワーモジュー
ルは弾性体１０をさらに備えるので、半導体チップ１の
下面と絶縁基板４の導体パターン５ａとの圧接に用いら
れる圧接力が大きい場合であっても、半導体チップ１に
かかる圧接力を弾性体１０に逃がすことができ、半導体
チップ１に形成された微細構造の破壊がより起こりにく
く、半導体チップ１の微細構造への制約を軽減できる。Further, since the power module according to the present embodiment further includes elastic body 10, even when the pressure contact force used for pressure contact between the lower surface of semiconductor chip 1 and conductive pattern 5a of insulating substrate 4 is large. In addition, the pressing force applied to the semiconductor chip 1 can be released to the elastic body 10, and the fine structure formed on the semiconductor chip 1 is less likely to be broken, and the restriction on the fine structure of the semiconductor chip 1 can be reduced.

【００４８】また、絶縁性ケース８ａのうち弾性体１０
の介在する部分を着脱可能な蓋状部分１１とした利点に
ついて以下に述べる。The elastic body 10 of the insulating case 8a
The advantage of using the removable lid-like portion 11 as the intervening portion will be described below.

【００４９】電極端子１３ａは外部から絶縁性ケース８
ａに差し込むことで絶縁性ケース８ａに固定してもよい
が、その場合、電極端子１３ａの位置精度が低くなる可
能性がある。圧接を考慮すれば各部の位置精度を高く保
つ必要があるので、電極端子１３ａと絶縁性ケース８ａ
とは一体成形されることが望ましい。The electrode terminal 13a is connected to the insulating case 8 from the outside.
a, it may be fixed to the insulating case 8a, but in that case, the positional accuracy of the electrode terminal 13a may be reduced. Considering the pressure contact, it is necessary to keep the position accuracy of each part high, so that the electrode terminal 13a and the insulating case 8a
Is desirably integrally molded.

【００５０】しかし、このように電極端子１３ａと絶縁
性ケース８ａとを一体成形すると、製造工程において、
弾性体１０を電極端子１３ａ他端の上面と絶縁性ケース
８ａとの間に介在させることが困難となる。However, when the electrode terminal 13a and the insulating case 8a are integrally formed as described above, in the manufacturing process,
It is difficult to interpose the elastic body 10 between the upper surface of the other end of the electrode terminal 13a and the insulating case 8a.

【００５１】そこで、絶縁性ケース８ａのうち弾性体１
０の介在する部分を着脱可能な蓋状部分１１としておけ
ば、製造時に、蓋状部分１１を外した状態で、弾性体１
０を電極端子１３ａの他端の上面に配置し、その後、蓋
状部分１１を絶縁性ケース８ａに装着すれば、容易に本
実施の形態に係るパワーモジュールを製造することがで
きるようになる。Therefore, the elastic member 1 of the insulating case 8a is
If the intervening portion 0 is provided as a detachable lid 11, the elastic body 1 can be removed in a state where the lid 11 is removed during manufacturing.
By disposing 0 on the upper surface of the other end of the electrode terminal 13a, and then attaching the lid-like portion 11 to the insulating case 8a, the power module according to the present embodiment can be easily manufactured.

【００５２】＜実施の形態２＞本実施の形態は、実施の
形態１に係るパワーモジュールの変形例である。<Embodiment 2> This embodiment is a modification of the power module according to Embodiment 1.

【００５３】図２は、本実施の形態に係るパワーモジュ
ールを示す図である。図２に示すように、このパワーモ
ジュールは、図１に示した実施の形態１に係るパワーモ
ジュールと同様、電力用半導体装置が形成された半導体
チップ１と、スペーサ３と、導体パターン５ａ，５ｂが
形成された絶縁基板４と、放熱用の剛体熱伝導板７と、
蓋状部分１１を有する絶縁性ケース８ｂと、弾性体１０
と、ナット１２と、電極端子１３ａと、絶縁膜１６とを
備えている。なお、図２においては、絶縁性ケース８ｂ
の形状が絶縁性ケース８ａの形状と比べ若干異なってい
るが、発明の本質に関わるものではないので、絶縁性ケ
ース８ｂは絶縁性ケース８ａと同視してよい。また、図
２においてはネジ１５の図示を省略しているが、実施の
形態１と同様、剛体熱伝導板７は、絶縁性ケース８ｂに
ネジ止めされる。FIG. 2 is a diagram showing a power module according to the present embodiment. As shown in FIG. 2, this power module, like the power module according to the first embodiment shown in FIG. 1, has a semiconductor chip 1 on which a power semiconductor device is formed, a spacer 3, and conductor patterns 5a and 5b. Formed on the insulating substrate 4, a rigid heat conducting plate 7 for heat dissipation,
An insulating case 8b having a lid portion 11;
, A nut 12, an electrode terminal 13a, and an insulating film 16. In FIG. 2, the insulating case 8b
Is slightly different from the shape of the insulating case 8a, but does not relate to the essence of the present invention. Therefore, the insulating case 8b may be regarded as the same as the insulating case 8a. Although the screw 15 is not shown in FIG. 2, the rigid heat conductive plate 7 is screwed to the insulating case 8b as in the first embodiment.

【００５４】さて、本実施の形態においては、半導体チ
ップ１の下面の導体箔２ａと絶縁基板４上の導体パター
ン５ａとがハンダ６ｄにより接合され、一方、絶縁基板
４の導体パターン５ｂと剛体熱伝導板７とが圧接により
接合される点で、実施の形態１と異なっている。なお、
剛体熱伝導板７が絶縁性ケース８ｂにネジ止めされたと
きに、絶縁基板４と剛体熱伝導板７とが圧接されるよ
う、各部の厚みは予め設計されている。In the present embodiment, the conductor foil 2a on the lower surface of the semiconductor chip 1 and the conductor pattern 5a on the insulating substrate 4 are joined by solder 6d, while the conductor pattern 5b on the insulating substrate 4 is connected to the rigid body. Embodiment 4 is different from Embodiment 1 in that the conductive plate 7 is joined by pressure welding. In addition,
The thickness of each part is designed in advance so that the insulating substrate 4 and the rigid heat conductive plate 7 are pressed against each other when the rigid heat conductive plate 7 is screwed to the insulating case 8b.

【００５５】その他の構成は実施の形態１と同様のた
め、説明を省略する。The other configuration is the same as that of the first embodiment, and the description is omitted.

【００５６】本実施の形態に係るパワーモジュールにお
いても、半導体チップ１の上面がハンダ等の導電性接着
剤により電極端子１３ａの他端の下面に接合されるの
で、ボンディングワイヤを用いることなく半導体チップ
１と電極端子１３ａとを接続でき、軽量薄型のパワーモ
ジュールを実現できる。Also in the power module according to the present embodiment, since the upper surface of semiconductor chip 1 is joined to the lower surface of the other end of electrode terminal 13a by a conductive adhesive such as solder, the semiconductor chip 1 can be used without using bonding wires. 1 can be connected to the electrode terminal 13a, and a light and thin power module can be realized.

【００５７】また、実施の形態１において述べた各種の
効果を、本実施の形態に係るパワーモジュールも有す
る。ただし、本実施の形態においては、絶縁基板４の下
面と剛体熱伝導板７とが圧接面となっているので、水平
方向の応力は、半導体チップ１の下面ではなく、絶縁基
板４の下面が受けることになる。しかし、絶縁基板４の
下面と剛体熱伝導板７との間で多少の位置ずれが生じた
としても問題はない。The power module according to the present embodiment also has the various effects described in the first embodiment. However, in the present embodiment, since the lower surface of the insulating substrate 4 and the rigid heat conductive plate 7 are in pressure contact with each other, the horizontal stress is applied not to the lower surface of the semiconductor chip 1 but to the lower surface of the insulating substrate 4. Will receive it. However, there is no problem even if a slight displacement occurs between the lower surface of the insulating substrate 4 and the rigid heat conductive plate 7.

【００５８】＜変形例＞上記実施の形態以外にも、実施
の形態１と実施の形態２とを混合したような構造にして
もよい。すなわち、図１に示したパワーモジュールから
ハンダ６ｃを省略して、絶縁基板４と剛体熱伝導板７
と、および、半導体チップ１と絶縁基板４との両方を圧
接により接合するようにしてもよい。その場合も、上記
と同様の効果が得られる。<Modification> In addition to the above-described embodiment, a structure in which the first and second embodiments are mixed may be adopted. That is, the solder 6c is omitted from the power module shown in FIG.
And both the semiconductor chip 1 and the insulating substrate 4 may be joined by pressure welding. In this case, the same effect as above can be obtained.

【００５９】[0059]

【発明の効果】請求項１に記載の発明によれば、半導体
チップの上面の少なくとも一部が導電性接着剤により電
極端子の他端の下面に接合され、半導体チップの下面と
絶縁基板の導体パターンとが、および／または、絶縁基
板の下面と放熱用部材とが圧接されるので、ボンディン
グワイヤを用いることなく半導体チップと電極端子とを
接続でき、軽量薄型のパワーモジュールを実現できる。
また、電極端子と半導体チップとの接続が短時間で済
む。また、半導体チップと電極端子との接合面を大きく
とることで、インダクタンスの値が小さいパワーモジュ
ールを実現できる。さらに、パワーモジュール動作時に
半導体チップに水平方向の応力が生じたとしても、半導
体チップの上面については導電性接着剤により電極端子
の他端に接合されているので、導電性接着剤が半導体チ
ップの上面と電極端子の他端の下面との間の隙間を充填
して半導体チップの上面に集中応力が発生しにくい。よ
って、半導体チップの上面に微細構造を形成しておけ
ば、微細構造の破壊が起こりにくく、半導体チップの微
細構造への制約を軽減できる。また、水平方向の応力
は、半導体チップの下面および／または絶縁基板の下面
の圧接部分が受けることになるが、ＩＧＢＴのコレクタ
電極のように半導体チップの下面に微細構造が形成され
ていなければ、半導体チップの下面と絶縁基板の導体パ
ターンとの間で、または、絶縁基板の下面と放熱用部材
との間で多少の位置ずれが生じたとしても問題はない。
また、半導体チップのうち圧接されるのは下面だけであ
るので、半導体チップの上下面共に圧接する従来の場合
に比べ、圧接数を減らしたことにより比較的少ない圧接
力でも圧接面での電気抵抗を低くすることができる。ま
たさらに、圧接力を得るための絶縁性ケースの剛性を少
なく見積もることも可能となる。According to the first aspect of the present invention, at least a part of the upper surface of the semiconductor chip is joined to the lower surface of the other end of the electrode terminal by the conductive adhesive, and the lower surface of the semiconductor chip and the conductor of the insulating substrate are connected. Since the pattern and / or the lower surface of the insulating substrate and the heat dissipation member are pressed against each other, the semiconductor chip and the electrode terminals can be connected without using a bonding wire, and a lightweight and thin power module can be realized.
Further, the connection between the electrode terminals and the semiconductor chip can be completed in a short time. In addition, by increasing the bonding surface between the semiconductor chip and the electrode terminals, a power module with a small inductance value can be realized. Furthermore, even if a horizontal stress is applied to the semiconductor chip during operation of the power module, the conductive adhesive is bonded to the other end of the electrode terminal on the upper surface of the semiconductor chip by the conductive adhesive, so that the conductive adhesive is The gap between the upper surface and the lower surface at the other end of the electrode terminal is filled, so that concentrated stress is hardly generated on the upper surface of the semiconductor chip. Therefore, if the fine structure is formed on the upper surface of the semiconductor chip, the fine structure is less likely to be broken, and the restriction on the fine structure of the semiconductor chip can be reduced. The horizontal stress is applied to the press-contact portion of the lower surface of the semiconductor chip and / or the lower surface of the insulating substrate. However, if a fine structure is not formed on the lower surface of the semiconductor chip like a collector electrode of an IGBT, There is no problem even if a slight displacement occurs between the lower surface of the semiconductor chip and the conductor pattern of the insulating substrate or between the lower surface of the insulating substrate and the heat dissipation member.
In addition, since only the lower surface of the semiconductor chip is pressed against the semiconductor chip, compared to the conventional case where both the upper and lower surfaces of the semiconductor chip are pressed against each other, the number of press-contacts is reduced so that the electric resistance at the press-contact surface can be reduced even with a relatively small pressing force. Can be lowered. Further, the rigidity of the insulating case for obtaining the press contact force can be estimated with a small value.

【００６０】請求項２に記載の発明によれば、電極端子
の他端がその上面および下面の垂直方向に弾性変形する
ので、半導体チップの下面と絶縁基板の導体パターンと
の圧接、および／または、絶縁基板の下面と放熱用部材
との圧接の際に、半導体チップにかかる圧接力を電極端
子に逃がすことができ、半導体チップに形成された微細
構造の破壊がより起こりにくく、半導体チップの微細構
造への制約を軽減できる。According to the second aspect of the present invention, the other end of the electrode terminal is elastically deformed in the vertical direction of the upper surface and the lower surface, so that the lower surface of the semiconductor chip is pressed against the conductor pattern of the insulating substrate and / or When pressing the lower surface of the insulating substrate and the heat dissipating member, the pressing force applied to the semiconductor chip can be released to the electrode terminals, and the fine structure formed on the semiconductor chip is less likely to be destroyed. Restrictions on the structure can be reduced.

【００６１】請求項３に記載の発明によれば、スペーサ
と絶縁膜とをさらに備えるので、半導体チップの上面に
低圧となる部分が形成され、半導体チップの下面に高圧
となる部分が形成された場合に、高圧となりやすい半導
体チップの側面近傍と電極端子との間の絶縁距離を増加
させることができ、耐電圧に優れたパワーモジュールを
実現できる。According to the third aspect of the present invention, since the semiconductor device further includes a spacer and an insulating film, a low voltage portion is formed on the upper surface of the semiconductor chip, and a high voltage portion is formed on the lower surface of the semiconductor chip. In this case, the insulation distance between the vicinity of the side surface of the semiconductor chip, which is likely to be high in voltage, and the electrode terminals can be increased, and a power module with excellent withstand voltage can be realized.

【００６２】請求項４に記載の発明によれば、弾性体を
さらに備えるので、半導体チップの下面と絶縁基板の導
体パターンとの圧接、および／または、絶縁基板の下面
と放熱用部材との圧接に用いられる圧接力が大きい場合
であっても、半導体チップにかかる圧接力を弾性体に逃
がすことができ、半導体チップに形成された微細構造の
破壊がより起こりにくく、半導体チップの微細構造への
制約を軽減できる。According to the fourth aspect of the present invention, since the elastic body is further provided, the pressure contact between the lower surface of the semiconductor chip and the conductor pattern of the insulating substrate and / or the pressure contact between the lower surface of the insulating substrate and the heat dissipation member. Even when the pressing force used for the semiconductor chip is large, the pressing force applied to the semiconductor chip can be released to the elastic body, and the fine structure formed on the semiconductor chip is less likely to be broken, so that the semiconductor chip may be damaged. Restrictions can be reduced.

【００６３】請求項５に記載の発明によれば、絶縁性ケ
ースのうち弾性体の介在する部分が着脱可能な蓋状部分
となっているので、製造時に弾性体を電極端子の他端の
上面と絶縁性ケースとの間に介在させる工程が行いやす
い。According to the fifth aspect of the present invention, since the portion of the insulating case where the elastic body is interposed is a detachable lid-like portion, the elastic body is connected to the upper surface of the other end of the electrode terminal during manufacturing. The process of interposing between the insulating case and the insulating case is easy to perform.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 実施の形態１に係るパワーモジュールを示す
断面図である。FIG. 1 is a sectional view showing a power module according to a first embodiment.

【図２】 実施の形態２に係るパワーモジュールを示す
断面図である。FIG. 2 is a sectional view showing a power module according to a second embodiment.

【図３】 従来のパワーモジュールを示す断面図であ
る。FIG. 3 is a cross-sectional view illustrating a conventional power module.

【符号の説明】[Explanation of symbols]

１ 半導体チップ、２ａ，２ｂ 導体箔、３ 導電性ス
ペーサ、４ 絶縁基板、５ａ，５ｂ 導体パターン、６
ａ〜６ｄ ハンダ、７ 剛体熱伝導板、８ａ〜８ｃ 絶
縁性ケース、１０ 弾性体、１１ 蓋状部分、１２ ナ
ット、１３ａ，１３ｂ 電極端子、１４ ネジ穴、１６
絶縁膜。Reference Signs List 1 semiconductor chip, 2a, 2b conductive foil, 3 conductive spacer, 4 insulating substrate, 5a, 5b conductive pattern, 6
a to 6d solder, 7 rigid heat conductive plate, 8a to 8c insulating case, 10 elastic body, 11 lid part, 12 nut, 13a, 13b electrode terminal, 14 screw hole, 16
Insulating film.

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 上面と下面とを有し、電力用半導体装置
が形成された半導体チップと、 前記半導体チップを収容する絶縁性ケースと、 前記絶縁性ケースに固定され、前記絶縁性ケース外に露
出した一端と前記絶縁性ケース内に露出した他端とを有
する電極端子と、 前記絶縁性ケースに接合される放熱用部材と、 前記半導体チップの前記下面が載置される導体パターン
が形成された上面、および前記放熱用部材上に載置され
る下面を有する絶縁基板とを備え、 前記電極端子の前記他端は上面と下面とを有し、その上
面および下面が前記絶縁基板の前記上面および下面に対
して平行に前記絶縁性ケース内に延在しており、 前記半導体チップの前記上面の少なくとも一部が導電性
接着剤により前記電極端子の前記他端の前記下面に接合
され、 前記半導体チップの前記下面と前記絶縁基板の前記導体
パターンとが、および／または、前記絶縁基板の前記下
面と前記放熱用部材とが圧接されたパワーモジュール。A semiconductor chip having an upper surface and a lower surface on which a power semiconductor device is formed; an insulating case for housing the semiconductor chip; a semiconductor chip fixed to the insulating case; An electrode terminal having an exposed one end and an exposed other end in the insulating case; a heat dissipation member joined to the insulating case; and a conductor pattern on which the lower surface of the semiconductor chip is mounted. And an insulating substrate having a lower surface mounted on the heat-dissipating member. The other end of the electrode terminal has an upper surface and a lower surface, and the upper and lower surfaces are the upper surface of the insulating substrate. And at least a portion of the upper surface of the semiconductor chip is joined to the lower surface of the other end of the electrode terminal by a conductive adhesive, And the lower surface of the semiconductor chip and the conductive pattern of the insulating substrate, and / or the power module and the lower surface and the heat radiating member of the insulating substrate is pressed. 【請求項２】 請求項１に記載のパワーモジュールであ
って、 前記電極端子の前記他端はその前記上面および下面の垂
直方向に弾性変形するパワーモジュール。2. The power module according to claim 1, wherein the other end of the electrode terminal is elastically deformed in a direction perpendicular to the upper and lower surfaces thereof. 【請求項３】 請求項１に記載のパワーモジュールであ
って、 前記半導体チップの前記上面の少なくとも一部と前記電
極端子の前記他端の前記下面との間に介在する導電性の
スペーサと、 前記電極端子の前記他端の前記下面のうち前記スペーサ
の介在する部分の周囲に形成された絶縁膜とをさらに備
えるパワーモジュール。3. The power module according to claim 1, wherein: a conductive spacer interposed between at least a part of the upper surface of the semiconductor chip and the lower surface of the other end of the electrode terminal; A power module further comprising: an insulating film formed around a portion of the lower surface at the other end of the electrode terminal where the spacer intervenes. 【請求項４】 請求項１に記載のパワーモジュールであ
って、 前記電極端子の前記他端の前記下面のうち前記半導体チ
ップの前記上面が接合された部分に対向する前記他端の
前記上面と前記絶縁性ケースとの間に介在する弾性体を
さらに備えるパワーモジュール。4. The power module according to claim 1, wherein, of the lower surface of the other end of the electrode terminal, the upper surface of the other end facing a portion where the upper surface of the semiconductor chip is joined. A power module further comprising an elastic body interposed between the power module and the insulating case. 【請求項５】 請求項４に記載のパワーモジュールであ
って、 前記絶縁性ケースのうち前記弾性体の介在する部分は、
着脱可能な蓋状部分となっているパワーモジュール。5. The power module according to claim 4, wherein a portion of the insulating case where the elastic body is interposed is provided.
Power module with removable lid.
JP2000256787A 2000-08-28 2000-08-28 Power module Pending JP2002076259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000256787A JP2002076259A (en) 2000-08-28 2000-08-28 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000256787A JP2002076259A (en) 2000-08-28 2000-08-28 Power module

Publications (1)

Publication Number Publication Date
JP2002076259A true JP2002076259A (en) 2002-03-15

Family

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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004032371A1 (en) * 2004-06-30 2006-01-26 Robert Bosch Gmbh Electronic circuit unit
JP2007221127A (en) * 2006-02-13 2007-08-30 Semikron Elektronik Gmbh & Co Kg Power semiconductor module and related manufacturing method
JP2009105267A (en) * 2007-10-24 2009-05-14 Fuji Electric Device Technology Co Ltd Semiconductor apparatus, and method of manufacturing the same
US7541670B2 (en) 2006-06-29 2009-06-02 Mitsubishi Electric Corporation Semiconductor device having terminals
WO2017208430A1 (en) * 2016-06-03 2017-12-07 三菱電機株式会社 Semiconductor device module

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004032371A1 (en) * 2004-06-30 2006-01-26 Robert Bosch Gmbh Electronic circuit unit
US7772688B2 (en) 2004-06-30 2010-08-10 Robert Bosch Gmbh Electronic circuit unit
JP2007221127A (en) * 2006-02-13 2007-08-30 Semikron Elektronik Gmbh & Co Kg Power semiconductor module and related manufacturing method
US7541670B2 (en) 2006-06-29 2009-06-02 Mitsubishi Electric Corporation Semiconductor device having terminals
JP2009105267A (en) * 2007-10-24 2009-05-14 Fuji Electric Device Technology Co Ltd Semiconductor apparatus, and method of manufacturing the same
WO2017208430A1 (en) * 2016-06-03 2017-12-07 三菱電機株式会社 Semiconductor device module
JPWO2017208430A1 (en) * 2016-06-03 2018-08-09 三菱電機株式会社 Semiconductor device module
CN109196641A (en) * 2016-06-03 2019-01-11 三菱电机株式会社 Semiconductor apparatus mould
CN109196641B (en) * 2016-06-03 2021-10-29 三菱电机株式会社 Semiconductor device module

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