JPS6262581A - Manufacture of semiconductor light emitting device - Google Patents
Manufacture of semiconductor light emitting deviceInfo
- Publication number
- JPS6262581A JPS6262581A JP60202394A JP20239485A JPS6262581A JP S6262581 A JPS6262581 A JP S6262581A JP 60202394 A JP60202394 A JP 60202394A JP 20239485 A JP20239485 A JP 20239485A JP S6262581 A JPS6262581 A JP S6262581A
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Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は半導体発光装置の製造方法に関し、特に埋込み
層の形成工程を改良した半導体発光装置の製造方法に係
わる。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly to a method for manufacturing a semiconductor light emitting device in which the process of forming a buried layer is improved.
半導体発光装置は、小形、高効率、軽量、機械的振動に
強い等半導体素子に共通な特長の他に、高速の直接変調
が可能、光ファイバとの高効率結合が可能等の特長を持
つことから、近年、オプトエレクトロニクス用光源とし
て実用化が進んできているが、その利用分野を更に拡大
するためには、製造工程の改良による大幅なコストダウ
ンが必要である。Semiconductor light emitting devices have features common to semiconductor devices such as small size, high efficiency, light weight, and resistance to mechanical vibration, as well as features such as high-speed direct modulation and high efficiency coupling with optical fibers. Therefore, in recent years, it has been put into practical use as a light source for optoelectronics, but in order to further expand its field of use, it is necessary to significantly reduce costs by improving the manufacturing process.
ところで、半導体発光装置の一つとして、Ｉ［［−Ｖ族
化合物半導体の結晶でダブルヘテロ接合構造とし、かつ
導波路をストライブ状にするために活性層より屈折率の
低い■−Ｖ族化合物半導体で埋込み、更に結晶を男開し
て得られる接合面に対して垂直な男開面を反射面とする
埋込み型半導体レーザが知られている。かかる半導体レ
ーザは、例えば従来より以下に説明する方法により製造
されている。By the way, as one of the semiconductor light emitting devices, a double heterojunction structure is formed using a crystal of an I[[-V group compound semiconductor, and a ■-V group compound semiconductor having a lower refractive index than the active layer is used to form a waveguide in a stripe shape. A buried type semiconductor laser is known in which a semiconductor laser is buried with a semiconductor and a crystal is opened, and the opening surface is perpendicular to the junction surface and serves as a reflective surface. Such semiconductor lasers have been conventionally manufactured, for example, by the method described below.
まず、■−ｖ族化合物半導体からなる半導体基板上に■
−ｖ族化合物半導体からなるバッファ層、クラッド層、
活性層、クラッド層及びキャップ層を順次積層してダブ
ルヘテロ接合を形成した後、該キャップ層上にＳｉＯ２
パターンを選択的に形成する。つづいて、該５ｉ０２パ
ターンをマスクとしてダブルヘテロ接合を所定深さまで
エツチング除去する。ひきつづき、液相成長法によりエ
ツチング部に■−Ｖ族化合物半導体を選択的に成長させ
る。次いで、ＳｉＯ２パターンを除去し、キャップ層と
基板裏面に正負の電極を形成した後、ダブルヘテロ接合
に対して垂直方向に襞間して、反射面となる男開面を形
成して埋込み型半導体レーザを製造する。First, on a semiconductor substrate made of a ■-v group compound semiconductor,
- A buffer layer and a cladding layer made of a V group compound semiconductor,
After sequentially stacking an active layer, a cladding layer, and a cap layer to form a double heterojunction, SiO2 is deposited on the cap layer.
Selectively form a pattern. Subsequently, using the 5i02 pattern as a mask, the double heterojunction is removed by etching to a predetermined depth. Subsequently, a -V group compound semiconductor is selectively grown in the etched portion by a liquid phase growth method. Next, after removing the SiO2 pattern and forming positive and negative electrodes on the cap layer and the back surface of the substrate, folds are formed perpendicularly to the double heterojunction to form a male open surface that will serve as a reflective surface to form a buried semiconductor. Manufacture lasers.
上述した製造方法によれば、エツチング部にｍ−Ｖ族化
合物半導体からなる埋込み層を選択的に形成できる。し
かしながら、かかる液相成長法は量産性に欠け、しかも
膜厚制御性が低いという問題があった。According to the above-described manufacturing method, a buried layer made of an m-V group compound semiconductor can be selectively formed in the etched portion. However, such a liquid phase growth method lacks mass productivity and has problems in that film thickness controllability is low.
本発明は、上記問題点を解決するためになされたもので
、ダブルヘテロ接合に形成したエツチング部にｍ−ＶＭ
化合物半導体の結晶を選択的に、効率よく、かつ制御性
よく埋込むことが可能な半導体発光装置の製造方法を提
供しようとするものである。〔問題点を解決するための
手段と作用〕本発明は、ダブルヘテロ構造を有する■−
Ｖ族化合物半導体上に４０μｍ以下の幅又は直径を有す
る１ｉｊｌ１体パターンを形成する工程と、このｉｔ体
パターンをマスクとして前記半導体を所望深さ選択的に
エツチングする工程と、１Ｑ Ｑ ｔｏｒｒ以下の減圧
気相エピタキシャル成長により前記半導体のエツチング
部に■−ｖ族化合物半導体を選択的に結晶成長させる工
程とを具備したことを特徴とするものである。かかる本
発明によれば、既述の如くダブルヘテロ接合に形成した
エツチング部に■−ｖ族化合物半導体の結晶を選択的に
、効率よく、かつ制御性よく埋込むことが可能で、量産
性の優れた半導体発光装置を得ることができる。The present invention has been made in order to solve the above-mentioned problems.
The object of the present invention is to provide a method for manufacturing a semiconductor light emitting device in which compound semiconductor crystals can be selectively embedded efficiently and with good controllability. [Means and effects for solving the problems] The present invention has a double heterostructure.
A step of forming a 1 ijl 1-body pattern having a width or diameter of 40 μm or less on a V group compound semiconductor, a step of selectively etching the semiconductor to a desired depth using this IT-body pattern as a mask, and a reduced pressure of 1Q Q torr or less. The present invention is characterized by comprising a step of selectively growing crystals of a 1-V group compound semiconductor in the etched portion of the semiconductor by vapor phase epitaxial growth. According to the present invention, it is possible to selectively, efficiently, and controllably embed crystals of the ■-V group compound semiconductor in the etched portion formed in the double heterojunction as described above, and it is possible to easily embed crystals in mass production. An excellent semiconductor light emitting device can be obtained.
上記減圧気相エピタキシャル成長時の真空度を限定した
理由は、その真空度が１００ ｔｏｒｒを越えると、半
導体のエツチング部への選択的な結晶成長が困難となる
からである。特に、量産性等を考慮すると、前記減圧気
相エピタキシャル成長の真空度を０．１〜５ Ｑ ｔｏ
ｒｒの範囲することが望ましい。The reason for limiting the degree of vacuum during the above-mentioned reduced pressure vapor phase epitaxial growth is that if the degree of vacuum exceeds 100 torr, selective crystal growth on the etched portion of the semiconductor becomes difficult. In particular, considering mass productivity, etc., the degree of vacuum in the reduced pressure vapor phase epitaxial growth is set to 0.1 to 5 Q to
It is desirable that the range be within rr.
以下、本発明をＧａＡＳ系の埋込み型半導体レーザに適
用した例について第１図（ａ）〜（ｄ）及び第２図を参
照して詳細に説明する。Hereinafter, an example in which the present invention is applied to a GaAS-based buried semiconductor laser will be described in detail with reference to FIGS. 1(a) to (d) and FIG. 2.
まず、ｎ型のＧａＡＳ基板（ＧａＡＳウェハ）１上に厚
さ０．５μｍのｎ型ＧａＡＳからなるバッファＷＪ２、
厚さ１．５μｍのｎ型Ａ ４ｏ、ａ Ｇ ａｏ７Ａｓか
らなるクラッド層３、厚さ０．１μｍのノンドープＧａ
ＡＳからなる活性層４、厚さ１．５μｍのｐ型Ａ Ｊ２
ｏ、ａ Ｇ ａｏ７△Ｓからなるクラッド層５及び厚さ
０．２μｍのｐ＋型ＧａＡＳからなるキャップ層６を順
次積層した後、該キャップ層６上にスパッタリング法に
より厚さ０．２μｍのＳｉＯ２膜７を蒸着した（第１図
（ａ）図示）。First, a buffer WJ2 made of n-type GaAS with a thickness of 0.5 μm is placed on an n-type GaAS substrate (GaAS wafer) 1;
Cladding layer 3 made of n-type A4o, aGao7As with a thickness of 1.5 μm, non-doped Ga with a thickness of 0.1 μm
Active layer 4 made of AS, p-type A J2 with a thickness of 1.5 μm
o, a After sequentially laminating a cladding layer 5 made of G ao7ΔS and a cap layer 6 made of p + type GaAS with a thickness of 0.2 μm, a SiO 2 film with a thickness of 0.2 μm is deposited on the cap layer 6 by sputtering. 7 was deposited (as shown in FIG. 1(a)).
つづいて、３ｉ０２膜７をパターニングして４０μｍ以
下の幅を有するストライブ状のＳｉＯ２パターン８を形
成した後、該パターン８をマスクとしてキャップ層６か
らクラッド層３の途中まで選択的にエツチング除去して
エツチング部９を形成した（同図（ｂ）図示）。Subsequently, the 3i02 film 7 is patterned to form a striped SiO2 pattern 8 having a width of 40 μm or less, and then, using the pattern 8 as a mask, the cap layer 6 to the middle of the cladding layer 3 is selectively etched away. An etched portion 9 was formed (as shown in FIG. 3(b)).
次いで、水素（キャリアガス） １０００．ｓｃｃｍ、
トリメチルガリウム６５ｃｃＬ トリメチルアルミニウ
ム８ ｓｅｃｍ及びアルシン３ Ｑ Ｑ ｓｃｃｍの原
料ガスを真空度４０ ｔｏｒｒＳ温度６７０℃の条件に
て分解させる減圧気相エピタキシャル成長法により高抵
抗のＡβｏ、ａ Ｇ ａａ、ｑ Ａ Ｓ結晶を成長させ
た。この時、真空度を４ Ｑ ｔｏｒｒに保持すること
によって、Ａ ｆｆ１ｏ、ａ Ｇ ａｏ７Ａ Ｓ結晶は
、同図（Ｃ）に示すようにマスクとしてのＳｉＯ２パタ
ーン８には全く成長せず、エツチング部９のみに選択的
に成長して、前記パターン８表面と同レベルの
Ａ ｆｆ１ｏ、ａ Ｇ ａｏ７Ａ Ｓ結晶からなる埋込
み層１０が形成された。Next, hydrogen (carrier gas) 1000. sccm,
High-resistance Aβo, aG aa, q A S crystals are produced by a low-pressure vapor phase epitaxial growth method in which raw material gases of 65 ccL of trimethyl gallium, 8 secm of trimethylaluminum, and 3 Q Q sccm of arsine are decomposed under conditions of a degree of vacuum of 40 torr S and a temperature of 670°C. Made it grow. At this time, by maintaining the degree of vacuum at 4 Q torr, the Aff1o, aGao7A S crystal does not grow at all on the SiO2 pattern 8 serving as a mask, as shown in FIG. A buried layer 10 made of A ff1o, a Gao7A S crystal at the same level as the surface of the pattern 8 was formed.
次いで、前記５１０２パターン８を除去した後、該パタ
ーン８の除去部分を含む埋込みｉ１０上にＡｕ−Ｚｎ合
金からなる正電極１１を形成した。Next, after removing the 5102 pattern 8, a positive electrode 11 made of an Au-Zn alloy was formed on the buried portion i10 including the removed portion of the pattern 8.
つづいて、基板１裏面を所望の厚さ研磨した後、Ａｕ−
Ｇｅ−Ｎｉの合金からなる負電極１２を形成し、更に該
基板（ウェハ）１のダイシング、埋込み層１０の長さ方
向に対して直交する方向への襞間を行なって、共振器と
しての襞間面（反射面）１３ａ、１３ｂを有する半導体
レーザを製造した（同図（ｄ）及び第２図図示）。なお
、第２図は第１図（ｄ）の斜視図である。Subsequently, after polishing the back surface of the substrate 1 to a desired thickness, Au-
A negative electrode 12 made of a Ge-Ni alloy is formed, and the substrate (wafer) 1 is diced and the buried layer 10 is folded in a direction perpendicular to the length direction to form the folds as a resonator. A semiconductor laser having intermediate surfaces (reflecting surfaces) 13a and 13b was manufactured (as shown in FIG. 2(d) and FIG. 2). Note that FIG. 2 is a perspective view of FIG. 1(d).
しかして、本発明によればキャップ層６上に４０μｍ以
下の幅を有するＳｉＯ２（誘電体）からなるストライブ
状のパターン８を形成し、該パターン８をマスクとして
キャップ層６からクラッド層３の中間までに亙って選択
的にエツチング除去してエツチング部９を形成した後、
１００ ｔｏｒ以下（実施例では４０ ｔｏｒｒ）の減
圧気相エピタキシャル成長を行うことによって、該パタ
ーン８上に高抵抗のＡ （ｌｏ、ｓ Ｇ ａｏ７Ａ Ｓ
結晶が成長されることなく、エツチング部９のみに同
Ａβｏ、ａ Ｇ ａｏ、ｑ Ａ Ｓ結晶を選択的に成長
でき、埋込み層１０を形成できる。従って、エツチング
部９に埋込み５＠１０を制御性よく形成できるため、高
性能の半導体レーザを量産的に得ることが可能となる。According to the present invention, a striped pattern 8 made of SiO2 (dielectric material) having a width of 40 μm or less is formed on the cap layer 6, and the stripes from the cap layer 6 to the cladding layer 3 are formed using the pattern 8 as a mask. After selectively etching away the middle part to form the etched portion 9,
A high resistance A (lo,s Gao7A S
The Aβo, aGao, and qAS crystals can be selectively grown only in the etched portion 9 without crystal growth, and the buried layer 10 can be formed. Therefore, the buried portion 5@10 can be formed in the etched portion 9 with good controllability, making it possible to mass-produce a high-performance semiconductor laser.
なお、上記実施例では誘電体としてＳｉＯ２を用いたが
、窒化シリコン、アルミナ等の他の誘電体を使用しても
よい。Although SiO2 was used as the dielectric in the above embodiment, other dielectrics such as silicon nitride and alumina may be used.
上記実施例では、活性領域がＧａＡＳ、それを囲む領域
がＧ ａｏ、ａ ＡλＯ，？ＡＳを用いたが、これらは
Ｇ ａｘ−ｘＡ １．ｘ Ａ ｓ （０＜ ｘ≦１）で
あっても勿論よい。In the above embodiment, the active region is GaAS, and the surrounding region is Gao, a AλO, ? AS was used, but these are G ax-xA 1. Of course, it may be x A s (0<x≦1).
上記実施例においては、再現性等の点で良好な結果が得
られることが多いので、ｎ型ＧａＡＳバッファ層２、ｐ
＋型ＧａＡＳキャップ層６を成長されているが、場合に
よってはこれらを省略することも可能である。In the above embodiments, good results are often obtained in terms of reproducibility, so the n-type GaAS buffer layer 2, p
Although the +-type GaAS cap layer 6 is grown, it is possible to omit this depending on the case.
上記実施例において、選択的な気相エピタキシャル成長
を行う前のエツチング部の深さは、任意でよく、例えば
基板に達する深いエツチング部を形成してもよいし、或
いは活性層まで達しない浅いエツチング部を形成しても
実施例と同様な効果を発揮できる。In the above embodiments, the depth of the etched portion before performing selective vapor phase epitaxial growth may be arbitrary; for example, a deep etched portion that reaches the substrate may be formed, or a shallow etched portion that does not reach the active layer may be formed. Even if it is formed, the same effect as in the embodiment can be achieved.
上記実施例ではＧａＡＳ系の半導体レーザについて説明
したが、４０μｍ以下の幅又は直径を有する誘電体パタ
ーンは、■族及び■族を含む有機金属化合物又は水素化
物を使用する１ ００ ｔｏｒｒ以下の減圧気相エピタ
キシャル成長において同様な選択性を示すので、ＩｎＰ
を始めとする他の■−Ｖ族化合物半導体基板を使用した
発光装置にも適用できる。また、半導体レーザ（面発光
型を含む）のみならず、埋込み構造を有する発光ダイオ
ードにも同様に適用できる。In the above embodiment, a GaAS-based semiconductor laser was described, but a dielectric pattern having a width or diameter of 40 μm or less can be produced using a reduced pressure of 100 torr or less using an organometallic compound or hydride containing group Ⅰ and group ①. InP exhibits similar selectivity in phase epitaxial growth.
The present invention can also be applied to light emitting devices using other ■-V group compound semiconductor substrates such as . Further, the present invention can be applied not only to semiconductor lasers (including surface-emitting type) but also to light-emitting diodes having a buried structure.
〔発明の効果］
以上詳述した如く、本発明によればダブルヘテロ接合に
形成したエツチング部に■−ｖ族化合物半導体の結晶を
選択的に、効率よく、かつ制御性よく埋込むことが可能
で、高性能の半導体発光装置を量産的に製造し得る方法
を提供できるものである。[Effects of the Invention] As detailed above, according to the present invention, it is possible to selectively, efficiently, and controllably embed crystals of the ■-V group compound semiconductor into the etched portion formed in the double heterojunction. Accordingly, it is possible to provide a method for mass-producing high-performance semiconductor light emitting devices.
第１図（ａ）〜（ｄ）は本発明の実施例における埋込み
型半導体レーザの製造工程を示す断面図、第２図は第１
図（ｄ）の斜視図である。
１・・・ｎ型ＧａＡＳ基板（ウェハ）、２・・・ｎ型Ｇ
ａＡＳのバッファ層、
３・・・ｎ型Ａ Ｑｏ、ｓ Ｇ ａＯ，？ Ａ ｓのク
ラッド層、４・・・ノンドープＧａＡＳの活性層、
５・・・ｐ型ＡＲ８，Ｇａｏ７ＡＳのクラッド層、６・
・・ｐ＋型ＧａＡＳのキャップ層、８・・・Ｓ ｉ ０
２パターン、９・・・エツチング部、
１０・・・高抵抗Ａ １０４ Ｇ ａａ、ｑ Ａ Ｓか
らなる埋込み層、１１・・・ＡＬＩ−２ｎ合金からなる
正電極、１２−Ａｕ−Ｇｅ−Ｎ ｉからなる負電極、１
３ａ、１３ｂ・・・舅開面（反射面）。
出願人代理人 弁理士 鈴江武彦
第１図
第１図
第２図1(a) to 1(d) are cross-sectional views showing the manufacturing process of a buried semiconductor laser according to an embodiment of the present invention, and FIG.
It is a perspective view of figure (d). 1...n-type GaAS substrate (wafer), 2...n-type G
aAS buffer layer, 3...n-type A Qo, s GaO,? cladding layer of As, 4... active layer of non-doped GaAS, 5... cladding layer of p-type AR8, Gao7AS, 6...
...p+ type GaAS cap layer, 8...S i 0
2 patterns, 9... Etched part, 10... Buried layer made of high resistance A 104 Gaa, q AS, 11... Positive electrode made of ALI-2n alloy, 12-Au-Ge-N i a negative electrode consisting of 1
3a, 13b... calf opening surface (reflection surface). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 1 Figure 2
Claims (1)
４０μｍ以下の幅又は直径を有する誘電体パターンを形
成する工程と、この誘電体パターンをマスクとして前記
半導体を所望深さ選択的にエツチングする工程と、１０
０ｔｏｒｒ以下の減圧気相エピタキシャル成長により前
記半導体のエッチング部にIII−Ｖ族化合物半導体を選
択的に結晶成長させる工程とを具備したことを特徴とす
る半導体発光装置の製造方法。A step of forming a dielectric pattern having a width or diameter of 40 μm or less on a III-V group compound semiconductor having a double heterostructure, and a step of selectively etching the semiconductor to a desired depth using the dielectric pattern as a mask. , 10
1. A method for manufacturing a semiconductor light emitting device, comprising the step of selectively growing crystals of a III-V group compound semiconductor in the etched portion of the semiconductor by low pressure vapor phase epitaxial growth at a pressure of 0 torr or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60202394A JPS6262581A (en) | 1985-09-12 | 1985-09-12 | Manufacture of semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60202394A JPS6262581A (en) | 1985-09-12 | 1985-09-12 | Manufacture of semiconductor light emitting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6262581A true JPS6262581A (en) | 1987-03-19 |
Family
ID=16456764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60202394A Pending JPS6262581A (en) | 1985-09-12 | 1985-09-12 | Manufacture of semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6262581A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237517A (en) * | 1987-03-26 | 1988-10-04 | Canon Inc | Selective formation of iii-v compound film |
| JPS63237533A (en) * | 1987-03-26 | 1988-10-04 | Canon Inc | Selective formation of ii-vi compound film |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143596A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of compound semiconductor device |
-
1985
- 1985-09-12 JP JP60202394A patent/JPS6262581A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143596A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of compound semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237517A (en) * | 1987-03-26 | 1988-10-04 | Canon Inc | Selective formation of iii-v compound film |
| JPS63237533A (en) * | 1987-03-26 | 1988-10-04 | Canon Inc | Selective formation of ii-vi compound film |
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