JPS58143596A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

Info

Publication number
JPS58143596A
JPS58143596A JP2701082A JP2701082A JPS58143596A JP S58143596 A JPS58143596 A JP S58143596A JP 2701082 A JP2701082 A JP 2701082A JP 2701082 A JP2701082 A JP 2701082A JP S58143596 A JPS58143596 A JP S58143596A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
gas
semiconductor
container
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2701082A
Other languages
Japanese (ja)
Inventor
Naoto Mogi
茂木　直人
Hiroko Asai
浅井　博子
Masasue Okajima
岡島　正季
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2701082A priority Critical patent/JPS58143596A/en
Publication of JPS58143596A publication Critical patent/JPS58143596A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/04—MOCVD or MOVPE

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To manufacture the embedded semiconductor laser with high precision making evenness and reproducibility of crystal growth excellent by a method wherein both mesa-etching and crystal growth by MO-CVD process are continuously performed without exposing semiconductor wafer to atmosphere at all. CONSTITUTION:The stainless steel made vacuum container 1 is provided so that one of the parallel plate type electrodes 2, 3 comprises a part of the container 1. Both Cl2 gas and CCl4 gas are mixed and charged from gas inlets 4, 5 and high frequency power of 300 W is impressed to mesa-etch semiconductor wafer 10. Then after substituting the gas in the container, trimethylgallium, trimethylaluminium and arsine diluted with H2 gas are introduced respectively at specified pressure to make embedded layer 30 grow in the mesa-etched part of the semiconductor wafer 10 by means of the thermal decomposing reaction of said gases. Then the semiconductor wafer 10 is taken out of the container to remove Ga0.4Al0.6As layer forming insulated layer 31 on the embedded layer 30 further forming electrodes 32, 33 by means of vacuum evaporation to constitute the embedded semiconductor laser.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、化合−半導体装置の製造方法に係ＤＳ４１に
半導体ウェハのエツチングと引き枕く結晶成長工１！！
Ｏ改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a compound semiconductor device. !
Regarding O improvement.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体レーデの構造に壌め込み構造レーデと呼ばれるも
のがある。堀め込み＊ａレーザにおいては、活性層は、
結晶基板面に垂直・平行の両方向共に屈折率の低い層に
埋め込まれた構造になっている。かかる構造によって埋
め込み構造レーデの横モードは極めて安定なものとなっ
ている。There is a type of semiconductor RADE structure called a recessed RADE structure. In the digging*a laser, the active layer is
It has a structure in which it is embedded in a layer with a low refractive index in both directions perpendicular and parallel to the crystal substrate surface. This structure makes the transverse mode of the embedded structure Radhe extremely stable.

活性層が埋め込まれた構造は、牛導俸し−ずのみならず
、先導波路を用いた光集積回路やあるいは、電気的集積
回路においても広く用いられる。光導波路の構造として
埋め込＋構造が最適であるのは半導体レーデの場合と同
じ理由によっている。璽−ｖｗ＆化合物半導体を用いた
為遍の集積回路を構成する一方法として、ＭＪｍ縦の人
声い、バンドイヤ、ゾの狭い半導体層を、・ぐンドンヤ
ツデの広い半導体層で取り囲む構造とする方法があり、
この場合には一次元的な電気伝導が達成されるために高
速な動作が期待できることになる。The structure in which the active layer is embedded is widely used not only in guiding devices but also in optical integrated circuits using guided waveguides or electrical integrated circuits. The reason why a buried + structure is optimal as an optical waveguide structure is the same as that for semiconductor radars. One method of constructing an integrated circuit using compound semiconductors is to create a structure in which narrow semiconductor layers with vertical MJm, band ears, and zo are surrounded by wide semiconductor layers with a wide width. can be,
In this case, high-speed operation can be expected because one-dimensional electrical conduction is achieved.

上記のような活性層の壊め込み構造を実現するには、通
常、基板結晶上にダブルへテロ接合４１１造のようなヘ
テロ接合構造となるように結晶成長を行い、しかる後に
結晶成長基板をメサエッチング等の遇択工、チングをし
、次にエツチング除去した部分に、活性層よりバンドギ
ヤ。In order to realize the collapsed structure of the active layer as described above, a crystal is usually grown on a substrate crystal to form a heterojunction structure such as a double heterojunction 411 structure, and then the crystal growth substrate is grown. Selective etching such as mesa etching is performed, and then the band gear is removed from the active layer in the area where the etching has been removed.

ｌの広い１−を結晶成長させる方法がとられる。A method of growing 1- crystals with a wide l is used.

この一連の工程においては、エツチング工程後の結晶成
長工程がとりわけＩＩ！な問題となる。In this series of steps, especially the crystal growth step after the etching step is II! This becomes a problem.

通常、エツチング工程と結晶成長工程とは互いに異なる
装置が用いられてきた。結晶表面にエピ′タギシャル結
晶成長を実現するためには、結晶成長開始に完全に清浄
表面になっていることが必要である。ところが、エツチ
ングを行った結晶成長基板の基板表面は清浄表面になっ
ていると思われるが、エツチング装置から結晶成長装置
に基板を装着しようとする際に、基板表向が空気中にさ
らされた９すると、表面はもはや清浄表面とはいいがた
くなり、この基板表面に結晶成長開始わしめる丸めには
、結晶成長開始までに何らかの基板表面浄化を行う必要
が生じる。Usually, different apparatuses have been used for the etching process and the crystal growth process. In order to realize epitaxial crystal growth on a crystal surface, it is necessary that the surface be completely clean at the beginning of crystal growth. However, although the surface of the etched crystal growth substrate is thought to be a clean surface, when trying to attach the substrate from the etching device to the crystal growth device, the surface of the substrate was exposed to the air. 9, the surface can no longer be called a clean surface, and in order to round the substrate surface to start crystal growth, it becomes necessary to perform some kind of substrate surface cleaning before crystal growth starts.

エツチングした基板表面がＧａＡａのような比較的不活
性な半導体である場合には、その表面の清浄化は比較的
容易で、例えばＨ２１ｆスＷｄ気下８００℃で５時間程
ｆＯ熱処理を行うことで、表面の活性化が実現する。し
かるに基板表面が（ＧａＡＪ　）ム多のようにＡノを含
む活性な半導体により構成され゛ている場合には、一旦
空気中に取り出した基板を清浄化することは容易でなく
なる。If the etched substrate surface is a relatively inactive semiconductor such as GaAa, cleaning the surface is relatively easy, for example by performing fO heat treatment at 800°C for about 5 hours under H21F/Wd atmosphere. , surface activation is achieved. However, if the surface of the substrate is made of an active semiconductor containing A such as (GaAJ), it is not easy to clean the substrate once it is taken out into the air.

（ＧａＡＪ）ム尋のような活性な半導体層の表面の清浄
化の困難さは結晶成長法により異なる。液相エピメキシ
ャル結晶成長法と呼ばれる浴融ＧａメルトからのＧａＡ
ｊムー結晶の析出を利用する方法では、結晶成長メルト
のメルトバック効果を利用することで、また、ＧａＣ１
やＡｌＣ１，等の金属ノ・ライドとアルシン等の水素化
物の反応を利用したノーライド法に、よる気相結晶成長
法の場合にはハロダン化物による表面酸化物エツチング
効果によって（ＧａＡｌ）Ａｓ結晶表面の清浄化が比較
的容易にイー■われる。しかし、ＭＯ−ＣＶＤ法と呼ば
れる有機−属化合物ガスとアルシン等の水素化物ガスと
の熱分解反応を利用した結晶成長法の場合には、基板表
面酸化物の除去効果が期待できない、したがってＭＯ−
ＣＶＤ法を用いる場合には、（ｃａＡｌ）Ａ＠を用いて
は堀め込み構造の実現は峻しい。The difficulty of cleaning the surface of an active semiconductor layer such as (GaAJ) varies depending on the crystal growth method. GaA from bath melt Ga melt called liquid phase epimexical crystal growth method
In the method that utilizes the precipitation of J-Mu crystals, by utilizing the melt-back effect of the crystal growth melt, GaC1
In the case of the vapor phase crystal growth method, which utilizes the reaction between metal hydride such as chloride or AlCl, and hydride such as arsine, the (GaAl)As crystal surface is Cleaning is relatively easy. However, in the case of the MO-CVD method, which is a crystal growth method that utilizes a thermal decomposition reaction between an organic compound gas and a hydride gas such as arsine, it cannot be expected to be effective in removing oxides on the substrate surface.
When using the CVD method, it is difficult to realize a trenched structure using (caAl)A@.

！、た、メサエッチング等を行った（ＧａＡｊりＡｓＡ
ｓ結晶表面結晶成長を行わしめるために液相エピタキ７
ヤル結晶成長法を用り箋メルトバックをかけるｈ法では
、基板表向の清浄化が行われるとはいえ、結晶表面に生
成した酸化膜を均一に除去することは極めて離しい、即
ち結晶表面の酸化膜が除去された部分からはメルトバッ
クの条ｉ＋−トでｒｒｉ結晶が溶は込むために、一般に
、メトルパ、りされた基板表面は不均一になる。しかも
基板表面の全ての部分について酸化ＭＶ除去するために
は、少くとも１μｍ以上結晶をメルトバックすることが
要求された。１μｍと非常に深くメルトバックする必要
があること、また、不均一にメルトパ、りされることが
ら、従来の技術では、２ｊＩ＠といりた非常に輸狭い活
性）−１１１ｉｉをもり先生導体レーデを再挑性良く作
成することはほとんど不可能であり喪。! , mesa etching, etc. (GaAj, AsA
Liquid phase epitaxy 7 to achieve crystal growth on the s-crystal surface.
Although the surface of the substrate is cleaned in the H method, which uses the normal crystal growth method and applies meltback, it is extremely difficult to uniformly remove the oxide film formed on the crystal surface. Since rri crystals are infiltrated by the melt-back strips from the portion where the oxide film has been removed, the surface of the substrate after melting is generally non-uniform. Furthermore, in order to remove the oxidized MV from all parts of the substrate surface, it was required to melt back the crystal by at least 1 μm or more. Due to the need for very deep meltback of 1 μm and the non-uniform melt-back, conventional technology has a very narrow meltback such as 2jI@-111ii. It is almost impossible to create a defiant mourning.

〔発明の目的〕[Purpose of the invention]

本発明は従来技術の欠点に鑑みなされたものであｆｉ、
ＭＯ−ＣＶＤ法により活性層の埋め込み構造を形成すゐ
場合に有用な、基板表面清浄化工程を特に必要としない
化合物半導体装置の製造方法を提供することを目的とす
る。The present invention has been made in view of the drawbacks of the prior art.
It is an object of the present invention to provide a method for manufacturing a compound semiconductor device that does not particularly require a substrate surface cleaning step and is useful when forming a buried structure of an active layer by MO-CVD.

〔発明の截置〕[Description of the invention]

本発明は、エツチングには反応性イオンエ。 The present invention uses reactive ion etching for etching.

チンダ等のドライエツチングを用い、結晶成長法には有
機金属を用い九気相結晶成長法（ＭＯ−ＣＶＤ法）を用
いて、エツチングと結晶成長とｔ１Ｂ＋−１Ｆ１Ｂ内に
おいて半導体ウエノ・を外気にさらすことなく連続し比
重１として行うことを４Ｉ徴とする。Using dry etching such as cinda, using an organic metal for the crystal growth method, and using the nine vapor phase crystal growth method (MO-CVD method), the semiconductor wafer is exposed to the outside air in the etching, crystal growth, and t1B+-1F1B. It is considered to be a 4I feature to perform consecutively with a specific gravity of 1 without any interruption.

（Ｇａムｌ）ムＳのような厘−Ｖ族化合物半導体の場合
、反応性イオンエツチング（ＲＩＢ）等Ｑｆラズマエッ
チングにはＣＦ、ＣＩ２．　ＣＨＣｊ、　、　ＣＣｊ４
．ＣＩ２等の・・口ｒンもしくはノ・ａｒン化物を用い
ゐが通常である。こうし九ノ、　ａ　ｆン化吻の低圧ガ
スに１３、５６　ｈａｓの高周波電力を加え、プラズマ
を生成する。　ＲＩｌｅ法の場合、プラズマにより生成
しＩＦ−ＣＩ＋イオン勢によシ、基板表面はエツチング
される。選択エツチングマスクを彫威した基板音用いて
メサエッチング勢を行い、しかるＩＩＫ％工、チンダさ
れ九基板を加熱し、元素周期律表１〜■族の有機金属化
合物ガスとｙ〜■族の水嵩化物ガスまたは有機金属化合
物ガスを流し、連続して結晶成長工ａｔ行う。この一連
の１椙は完全に同一チェンバ内において行うことが可能
である。In the case of a RI-V compound semiconductor such as (Gamul) S, Qf plasma etching such as reactive ion etching (RIB) is performed using CF, CI2. CHCj, , CCj4
．． Usually, a compound such as CI2 is used. In this case, high-frequency power of 13.56 has is applied to the low-pressure gas of the afonization proboscis to generate plasma. In the case of the RIle method, the substrate surface is etched by a force of IF-CI+ ions generated by plasma. A mesa etching process was performed using a substrate etched with a selective etching mask, and then a IIK% process was performed, a tinned substrate was heated, and an organometallic compound gas of groups 1 to 2 of the periodic table of elements and a water volume of groups y to 2 of the periodic table were heated. A crystal growth process is performed continuously by flowing a compound gas or an organometallic compound gas. This series of tests can be performed completely within the same chamber.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、エツチングされた結晶基板特別な基板
清浄工程を含ませることなく、ＭＯ−ＣＶＤ法により均
一な結晶成長が可能となる。従って活性層の壊め込み構
造をもつ化合物半導体レーデや導波路等を再現性よく、
かつ尚梢度に実現することができる。According to the present invention, uniform crystal growth is possible using the MO-CVD method without including a special substrate cleaning process for etched crystal substrates. Therefore, compound semiconductor radars and waveguides with a collapsed structure of the active layer can be fabricated with good reproducibility.
Moreover, it can be realized to the highest degree.

〔発明の実施例〕[Embodiments of the invention]

第１図は、（ＧｍＡｊ）ム１堀め込み構造半導体レーデ
の製造に用いた本発明の一笑施例の装置でめる。１はス
テンレス類の真空容器本体で、半行平ａｍ電極２．３が
、その一方が容器の一部を構成するように設けられてい
る。４，５はガス導入口、Ｃは排気口であり、７はパル
プである。FIG. 1 shows an apparatus according to one embodiment of the present invention used for manufacturing a semiconductor radar with a (GmAj) 1-hole trench structure. Reference numeral 1 denotes a vacuum container body made of stainless steel, on which half-parallel am electrodes 2.3 are provided such that one of them constitutes a part of the container. 4 and 5 are gas inlet ports, C is an exhaust port, and 7 is pulp.

電極！、Ｊはテフロン轡の絶縁物８により容器本体１と
は絶縁されており、これに外部の面絢波電源９から例え
ば１２．５６　ＭＨＩの尚周波電力が印加されるように
なっている。またｉｋ憔２．３の＃に極−に半導体ウエ
ノ・１０をおき、これをヒータ１ノ、電源１２により加
熱できるようになっている。electrode! , J are insulated from the container body 1 by a Teflon-lined insulator 8, and a still frequency power of, for example, 12.56 MHI is applied thereto from an external power source 9. Further, a semiconductor wafer 10 is placed at the # pole of the ik 2.3, and this can be heated by the heater 1 and the power source 12.

纂２図は半導体ウェハ１０の構造例であシ、ＧａＡｍ基
板２ノに、Ｇａ（１，４５Ａ７ｏ＃５５ＡＩ層２２、Ｇ
ａ　ｏ、　ａｊＬｌｏ、ｚＡ　ｍ層２３、”Ｏ，？？！
”’０．００５Ａ１層２４、Ｇａ０４ＡＧ４ＡＭ層２５
、”（ｌｊｉ”０４５人’層２６、Ｑ＆Ａ１１〕１１２
１、Ｇａｏ、４膜７ｇ、ｉＡｓ／ｅｌ　Ｊ　ａを連続的
にエピタキシャル成長してダブルへテロ接合を構成した
ものである。このような半導体ウニ八１００表向に、第
３図に示すように例えば８　ｌ　、Ｎ４膜によるストラ
イプ状マスク２ｇを形成した状態で４１図の装置に装着
される。そしてまず、ガス導入口４．５からＣ１２ガス
とＣＣｌ４ガスをそれぞれ０．０２　Ｔｏｒｒ、　ＯＤ
５　Ｔｏｒｒの圧力で混合して流入させ、高周波電力３
００Ｗを印加して半導体ウェハ１０をメサエッチングし
、纂４図の構造を得る。その後、容器内のガスを置換し
、Ｈ２ガスで希釈したトリメチルガリウム、トリメチル
アルイニウムおよびアルシンをそれぞれ所定圧で導入し
、これらのガスの熱分解反応によって半導体ウェハｌ＃
のメサエッチングした部分に第５図に示すように埋め込
み層３０を成長させる。Figure 2 shows an example of the structure of the semiconductor wafer 10, in which Ga(1,45A7o#55AI layer 22, G
a o, ajLlo, zA m layer 23, “O,????!
``'0.005A1 layer 24, Ga04AG4AM layer 25
, "(lji" 045 people' layer 26, Q&A 11] 112
A double heterojunction was constructed by epitaxially growing 1, Gao, 4 films, 7 g, and iAs/el Ja in a continuous manner. As shown in FIG. 3, a striped mask 2g made of, for example, an 8 l N4 film is formed on the surface of the semiconductor urchin 8 100, and then it is mounted in the apparatus shown in FIG. 41. First, C12 gas and CCl4 gas were introduced from gas inlet 4.5 at 0.02 Torr, OD.
Mix at a pressure of 5 Torr and let it flow, and use high frequency power 3
00W is applied to mesa-etch the semiconductor wafer 10 to obtain the structure shown in Fig. 4. Thereafter, the gas in the container is replaced, and trimethylgallium, trimethylalinium, and arsine diluted with H2 gas are introduced at predetermined pressures, and a thermal decomposition reaction of these gases causes the semiconductor wafer l#
A buried layer 30 is grown on the mesa-etched portion as shown in FIG.

そして容器から半導体ウェハを取り出し、Ｇａｏ、４ム
！。、４ムＳ層２１を除去して、埋め込み層３０上に絶
縁層３１を形成し、真空蒸着により電極ｓｚ、ｓｘを形
成して堀め込み構造半導体レーデが構成される。Then, take out the semiconductor wafer from the container, Gao, 4m! . , the S layer 21 is removed, an insulating layer 31 is formed on the buried layer 30, and electrodes sz and sx are formed by vacuum evaporation to form a trenched semiconductor radar.

こうしてこの実施例によれば、メサエッチングとＭＯ−
ＣＶＤ法による結晶成長とを、半導体ウェハを外気にさ
らす仁となく連続的に行うため、均一性、Ｆ！現性のす
ぐれ九結晶成長が可能とな夛、高精度の堀め込み構造半
導体レーデが得られる。Thus, according to this embodiment, mesa etching and MO-
Since crystal growth using the CVD method is performed continuously without exposing the semiconductor wafer to the outside air, uniformity and F! It is possible to obtain a high-precision trenched structure semiconductor radar, which is capable of growing nine crystals.

なお、実施例では半導体ウェハのエツチング法としてＲ
ＩＥを用い九が、他の形式のプラズマエッチングやある
いはスフ４．タエツチング等のドライエツチングを用い
ることができる。また半導体ウェハの加熱手段も抵抗加
熱でなく＾周波加熱方式を利用してもよい。その他本発
明にそ０趣旨を逸脱しない範囲で種々変形実施すること
が可能である。In addition, in the example, R is used as an etching method for semiconductor wafers.
4. IE can be used for other forms of plasma etching or surface etching. Dry etching such as etching can be used. Further, the semiconductor wafer heating means may also utilize a frequency heating method instead of resistance heating. In addition, various modifications can be made to the present invention without departing from the spirit thereof.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に用いた装置を示す図、第２
図〜ｗＬ５図は同実施例の製造工程を説明するための半
導体ウェハ断面図である。 １・・・真空容器本体、２．１・・・電極、４，５・・
・ガス導入口、ｌ・・・排気口、１・・・パルプ、１・
・・絶縁物、９・・・高周波電源、１０・・・半導体ウ
ェハ、１１・・・ヒータ、１２・・・電源。 出願人代理人　　弁理士　鈴　江　武　彦第１１１Fig. 1 is a diagram showing an apparatus used in one embodiment of the present invention, Fig. 2 is a diagram showing an apparatus used in an embodiment of the present invention;
Figures to wL5 are cross-sectional views of a semiconductor wafer for explaining the manufacturing process of the same embodiment. 1... Vacuum container body, 2.1... Electrode, 4, 5...
・Gas inlet, l...exhaust port, 1...pulp, 1.
... Insulator, 9 ... High frequency power supply, 10 ... Semiconductor wafer, 11 ... Heater, 12 ... Power supply. Applicant's agent Patent attorney Takehiko Suzue No. 111

Claims (2)

【特許請求の範囲】[Claims] （１）一つの容器内で、半導体ウェハをドライエツチン
グｊる工程と、引き続き有機金属化合一ガスと水素化物
ガスまたは別の有機金属化合物ガスとの熱分解反応によ
り前記半導体ウェハに化合物半導体結晶を成長させる工
程とを、前記半導体クエハを外気にさらすことなく連続
的に行うことを％像とする化合物半導体装置の製造方法
。(1) A step of dry etching a semiconductor wafer in one container, followed by a thermal decomposition reaction between an organometallic compound gas and a hydride gas or another organometallic compound gas to form compound semiconductor crystals on the semiconductor wafer. A method for manufacturing a compound semiconductor device, characterized in that the step of growing the semiconductor wafer is continuously performed without exposing the semiconductor wafer to outside air. （２）半導体ウェハは基板上にダブルへテロ接合を構成
するように１［数層の化合愉牛導体層を積ＩＩｌ形成し
たものでＴｏ９、ドライエツチングエ４！Ｉ！は上記積
層半導体層ｔストライプ状に残してメサエッチングする
工程であり、化合物半導体結晶の成長工程は上記メサエ
ッチング部に埋め込み層を成長させる工程である特許請
求の範囲ｉ＠１項記載の化合物半導体装置の製造方法。(2) The semiconductor wafer is made by laminating several layers of composite conductor layers on the substrate to form a double heterojunction, To9, dry etching 4! I! The compound semiconductor according to claim 1, wherein is a step of mesa etching the laminated semiconductor layer while leaving it in a stripe shape, and the step of growing the compound semiconductor crystal is a step of growing a buried layer in the mesa etched portion. Method of manufacturing the device.
JP2701082A 1982-02-22 1982-02-22 Manufacture of compound semiconductor device Pending JPS58143596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2701082A JPS58143596A (en) 1982-02-22 1982-02-22 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2701082A JPS58143596A (en) 1982-02-22 1982-02-22 Manufacture of compound semiconductor device

Publications (1)

Publication Number Publication Date
JPS58143596A true JPS58143596A (en) 1983-08-26

Family

ID=12209133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2701082A Pending JPS58143596A (en) 1982-02-22 1982-02-22 Manufacture of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS58143596A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223185A (en) * 1984-04-19 1985-11-07 Nec Corp Manufacture of semiconductor laser
JPS61202488A (en) * 1985-03-06 1986-09-08 Fujitsu Ltd Manufacture of buried semiconductor laser
JPS6262581A (en) * 1985-09-12 1987-03-19 Furukawa Electric Co Ltd:The Manufacture of semiconductor light emitting device
JPS62104436U (en) * 1985-12-20 1987-07-03
JPS6392075A (en) * 1986-10-06 1988-04-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor optical device
JPS63226989A (en) * 1987-03-16 1988-09-21 Nec Corp Manufacture of buried semiconductor laser
JPH0194690A (en) * 1987-10-06 1989-04-13 Furukawa Electric Co Ltd:The Manufacture of buried type semiconductor laser device
JPH01189187A (en) * 1988-01-25 1989-07-28 Sumitomo Electric Ind Ltd Manufacture of semiconductor laser element and vapor phase epitaxy apparatus used in said manufacture
EP0562769A2 (en) * 1992-03-25 1993-09-29 AT&T Corp. Semiconductor surface emitting laser having enhanced optical confinement

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223185A (en) * 1984-04-19 1985-11-07 Nec Corp Manufacture of semiconductor laser
JPS61202488A (en) * 1985-03-06 1986-09-08 Fujitsu Ltd Manufacture of buried semiconductor laser
JPS6262581A (en) * 1985-09-12 1987-03-19 Furukawa Electric Co Ltd:The Manufacture of semiconductor light emitting device
JPS62104436U (en) * 1985-12-20 1987-07-03
JPH0530353Y2 (en) * 1985-12-20 1993-08-03
JPS6392075A (en) * 1986-10-06 1988-04-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor optical device
JPS63226989A (en) * 1987-03-16 1988-09-21 Nec Corp Manufacture of buried semiconductor laser
JPH0194690A (en) * 1987-10-06 1989-04-13 Furukawa Electric Co Ltd:The Manufacture of buried type semiconductor laser device
JPH01189187A (en) * 1988-01-25 1989-07-28 Sumitomo Electric Ind Ltd Manufacture of semiconductor laser element and vapor phase epitaxy apparatus used in said manufacture
EP0562769A2 (en) * 1992-03-25 1993-09-29 AT&T Corp. Semiconductor surface emitting laser having enhanced optical confinement

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