JPH02121362A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02121362A JPH02121362A JP27501488A JP27501488A JPH02121362A JP H02121362 A JPH02121362 A JP H02121362A JP 27501488 A JP27501488 A JP 27501488A JP 27501488 A JP27501488 A JP 27501488A JP H02121362 A JPH02121362 A JP H02121362A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum wiring
- power supply
- layer aluminum
- wiring
- functional block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 31
- 229910052782 aluminium Inorganic materials 0.000 abstract description 31
- 239000003990 capacitor Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は半導体集積回路における機能ブロック装置の低
雑音化に間する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is directed to reducing the noise of a functional block device in a semiconductor integrated circuit.
〔従来の技術１
従来の半導体集積回路では機能ブロック装置の外周に電
源供給装置だけを付加していた。そのため機能ブロック
装置から生じる電源雑音により入出力装置及び内部論理
回路部に悪影響を及ぼすおそれがあった。[Prior Art 1] In a conventional semiconductor integrated circuit, only a power supply device is added to the outer periphery of a functional block device. Therefore, the power supply noise generated from the functional block device may have a negative effect on the input/output device and the internal logic circuit section.
そこで、従来の半導体集積回路においては１機能ブロッ
ク装置の電源供給装置を入出力装置及び内部論理回路部
とは別系統にしていた。Therefore, in conventional semiconductor integrated circuits, the power supply device of one functional block device is provided in a separate system from the input/output device and the internal logic circuit section.
しかし、前述の従来技術では、入出力装置及び内部論理
回路部とは別に電源供給をしなくてはならないために一
定の面積をとり、また機能ブロック装置の配置の制約も
あるという問題点を有する。However, the above-mentioned conventional technology has the problem that it requires a certain amount of area because the power supply must be supplied separately from the input/output device and the internal logic circuit section, and there are also restrictions on the placement of the functional block device. .
そこで本発明は従来の半導体装置の問題点を解決するた
めのもので、その目的とするところは電源雑音の少ない
機能ブロック装置を提供するところにある。SUMMARY OF THE INVENTION The present invention is intended to solve the problems of conventional semiconductor devices, and its purpose is to provide a functional block device with less power supply noise.
〔課題を解決するための手段］
本発明の半導体装置は、
ａ）一定の機能動作をする機能ブロック装置を１つ以上
有する半導体集積回路において、ｂ）前記機能ブロック
装置の外周に少なくとも１つ以上の正極電源供給装置、
及び、負極電源供給装置を具備し。[Means for Solving the Problems] A semiconductor device of the present invention includes: a) a semiconductor integrated circuit having one or more functional block devices that perform certain functional operations, b) at least one functional block device on the outer periphery of the functional block device; positive power supply device,
And, it is equipped with a negative electrode power supply device.
Ｃ）前記正極電源供給装置と前記負極電源供給装置を重
ね合わせその間に容量を構成することを特徴とする。C) The positive electrode power supply device and the negative electrode power supply device are overlapped to form a capacitor therebetween.
〔実 施 例］
以下に本発明の実施例を図面に基づいて説明する。第１
図は本発明の半導体装置の平面図であり、第２図は第１
図のＡ−Ｂの断面図である。第１図において実線１で囲
まれる部分が読出し専用メモリ（ＲＯＭ）であり、第２
図において左斜線２は＋ＶＤＤ電源に接続する第１層目
のアルミニウム配線、左斜線３は−ｖＳＳ電源に接続す
る第１層目のアルミニウム配線、右斜線４は−ｖＳＳ電
源に接続する第２層目のアルミニウム配線、右斜線５は
＋ＶＤＤ電源に接続する第２層目のアルミニウム配線で
あり、実線９、ｌＯは酸化膜である。[Example] Examples of the present invention will be described below based on the drawings. 1st
The figure is a plan view of the semiconductor device of the present invention, and FIG.
It is a sectional view taken along AB in the figure. In FIG. 1, the part surrounded by the solid line 1 is the read-only memory (ROM), and the second part is the read-only memory (ROM).
In the figure, the left diagonal line 2 is the first layer aluminum wiring connected to the +VDD power supply, the left diagonal line 3 is the first layer aluminum wiring connected to the -vSS power supply, and the right diagonal line 4 is the second layer aluminum wiring connected to the -vSS power supply. The diagonal line 5 on the right is the second layer of aluminum wiring connected to the +VDD power supply, and the solid line 9 and lO are the oxide films.
前記読出し専用メモリ１の外周に第１層目のアルミニウ
ム配線２で＋ＶＤＤ電源ν線、第１層目のアルミニウム
配！Ｊ１３で−ｖＳＳ電源配線を形成し、その上に酸化
１莫９を形成し、前記酸化膜９をはさみ込む形で前記第
１層目のアルミニウム配線２上に前記第２層目のアルミ
ニウム配線４で−ＶＳＳ電源配線を形成し、また、前記
第１層目のアルミニウム配線３上に前記第２層目のアル
ミニウム配線５で＋ＶＤＤ電源配線を形成し、その上に
酸化膜１０を形成している。それにより＋ＶＤＤ電源に
接続された前記第１層目のアルミニウム配線２と−ＶＳ
Ｓ電源に接続された前記第２層目のアルミニウム配線４
の間に容量を構成することができる。また−ＶＳＳ電源
に接続された前記第１層目のアルミニウム配線３と＋Ｖ
ＤＤ電源に接続された前記第２層目のアルミニウム配線
５の間にも同様に容量を構成することができる。前記容
量により前記読出し専用メモリｌ内で発生する電源雑音
を吸収し減少することができる。またアルミニウム配線
の面積を大きくシ、アルミニウム配線間の酸化膜の膜厚
を薄くすることでより大きな容量を作ることができ効果
的である。その他前記第１層目のアルミニウム配！ｓ２
と前記第２層目のアルミニウム配線４だけでも容量を構
成し前記読出し専用メモリｌ内で発生する電源雑音を吸
収し減少することが可能である。On the outer periphery of the read-only memory 1, a first layer of aluminum wiring 2 is connected to a +VDD power supply ν line and a first layer of aluminum wiring! A −vSS power supply wiring is formed in J13, an oxide layer 9 is formed on it, and the second layer aluminum wiring 4 is placed on the first layer aluminum wiring 2 with the oxide film 9 sandwiched therebetween. -VSS power wiring is formed on the first layer aluminum wiring 3, and +VDD power wiring is formed on the second layer aluminum wiring 5, and an oxide film 10 is formed thereon. . As a result, the first layer aluminum wiring 2 connected to the +VDD power supply and the -VS
The second layer of aluminum wiring 4 connected to the S power source
Capacity can be configured between. In addition, the first layer aluminum wiring 3 connected to the -VSS power supply and +V
Similarly, a capacitor can be formed between the second layer aluminum wiring 5 connected to the DD power source. The capacitor can absorb and reduce power supply noise generated within the read-only memory l. Furthermore, it is effective to increase the area of the aluminum wiring and reduce the thickness of the oxide film between the aluminum wirings to create a larger capacitance. Other than that, the first layer of aluminum! s2
The second layer aluminum wiring 4 alone constitutes a capacitor, and can absorb and reduce power supply noise generated within the read-only memory 1.
尚１本実施例によれば電源供給装置としてアルミニウム
２層配線を使用したが、ポリシリコン配線、拡散領域等
の導電体を使用することも可能である。また１機能ブロ
ック装置として読出し専用メモリ（ＲＯＭ）を使用した
が、ＲＡＭ、ＰＬＡ等の一定機能を動作する装置を使用
することも可能である。In this embodiment, a two-layer aluminum wiring is used as the power supply device, but it is also possible to use a conductor such as a polysilicon wiring or a diffusion region. Further, although a read-only memory (ROM) is used as one functional block device, it is also possible to use a device that operates a fixed function such as a RAM or PLA.
以上の実施例はあくまでも一実施例にすぎない。The above embodiment is merely an example.
以上のような実施例において機能ブロック装置の電源雑
音を減少することができ、ＬＳＩチップ内の他の内部論
理回路等への影響を少なくすることができ、ＬＳＩチッ
プ内に自由に配置することができる。In the embodiments described above, the power supply noise of the functional block device can be reduced, the influence on other internal logic circuits in the LSI chip, etc. can be reduced, and it is possible to freely arrange the functional block device in the LSI chip. can.
［発明の効果］
本発明は以上説明したように１機能ブロック装置の外周
に電源供給装置を配置し、容量を構成することによって
機能ブロック装置での電源雑音を減少することができる
。また、電源雑音が減少するため、他の内部論理回路、
入出力装置等への悪影響も少なくなり機能ブロック装置
の配置制限もなくすことができる。[Effects of the Invention] As described above, the present invention can reduce power supply noise in a functional block device by arranging a power supply device on the outer periphery of one functional block device and configuring a capacity. Also, since power supply noise is reduced, other internal logic circuits,
The adverse effect on input/output devices, etc. is also reduced, and restrictions on the placement of functional block devices can be eliminated.
第１図は実施例を示す平面図、第２図は第１図Ａ−Ｂ間
の断面図、第３図は従来の半導体装置の平面図、第４図
は第３図Ｃ−Ｄ間の断面図、第５図はチップ概略図であ
る。
１．６・・・・・読出し専用メモリ
２．３．７．８・第１層目アルミニウム配線４．５・・
・・・第２層目アルミニウム配線９．１０．１１・酸化
膜
機能ブロンク装置
入出力装置
・内部論理回路部
以
上Fig. 1 is a plan view showing the embodiment, Fig. 2 is a sectional view taken along the line A-B in Fig. 1, Fig. 3 is a plan view of a conventional semiconductor device, and Fig. 4 is taken between Fig. 3 C-D. The cross-sectional view, FIG. 5, is a schematic diagram of the chip. 1.6... Read-only memory 2.3.7.8 First layer aluminum wiring 4.5...
・・・2nd layer aluminum wiring 9.10.11・Oxide film function bronch device input/output device・Internal logic circuit section and above
Claims (1)
つ以上有する半導体集積回路において、ｂ）前記機能ブ
ロック装置の外周に少なくとも１つ以上の正極電源供給
装置、及び、負極電源供給装置を具備し、 ｃ）前記正極電源供給装置と前記負極電源供給装置を重
ね合わせその間に容量を構成することを特徴とする半導
体装置。(1)a) 1 functional block device that performs a certain functional operation
b) at least one positive power supply device and a negative power supply device are provided on the outer periphery of the functional block device; c) the positive power supply device and the negative power supply device; A semiconductor device characterized in that a capacitance is formed between the two layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27501488A JPH02121362A (en) | 1988-10-31 | 1988-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27501488A JPH02121362A (en) | 1988-10-31 | 1988-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02121362A true JPH02121362A (en) | 1990-05-09 |
Family
ID=17549677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27501488A Pending JPH02121362A (en) | 1988-10-31 | 1988-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02121362A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0459959U (en) * | 1990-10-01 | 1992-05-22 | ||
| EP0572026A2 (en) * | 1992-05-29 | 1993-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
-
1988
- 1988-10-31 JP JP27501488A patent/JPH02121362A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0459959U (en) * | 1990-10-01 | 1992-05-22 | ||
| EP0572026A2 (en) * | 1992-05-29 | 1993-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| EP0572026A3 (en) * | 1992-05-29 | 1995-02-15 | Tokyo Shibaura Electric Co | Semiconductor memory device. |
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