JPS62128520A - Semiconductor wafer and manufacture thereof - Google Patents
Semiconductor wafer and manufacture thereofInfo
- Publication number
- JPS62128520A JPS62128520A JP26983885A JP26983885A JPS62128520A JP S62128520 A JPS62128520 A JP S62128520A JP 26983885 A JP26983885 A JP 26983885A JP 26983885 A JP26983885 A JP 26983885A JP S62128520 A JPS62128520 A JP S62128520A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- blocking film
- circumferential surface
- film
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は各種半導体装置の基板等として用いられる半導
体ウェーハ及びそのｉ遣方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer used as a substrate for various semiconductor devices and a method for using the same.
通学エピタキシャルウェーハは不純物を高濃度にドープ
してｐ型、或いはｎ型のいずれかの導電型を備えるよう
構成されることが多い。School epitaxial wafers are often doped with impurities at a high concentration to have either p-type or n-type conductivity.
例えば、導電型をｐ型とする場合には不純物としてボロ
ン（Ｂ）等が、またｎ型とする場合にはリン（Ｐ）、ア
ンチモン（Ｓｂ）、ヒ素（Ａｓ）等が夫々シリコンウェ
ーハに高濃度にドープされる。しかしこのようなドープ
されたウェーハ上にシリコンをエピタキシャル成長させ
るべくウェーハを高温（１０００〜１２００℃）に加熱
したような場合、Ｂ。For example, impurities such as boron (B) are added to the silicon wafer when the conductivity type is p-type, and phosphorus (P), antimony (Sb), arsenic (As), etc. are added to the silicon wafer when the conductivity type is n-type. Doped to a high concentration. However, when the wafer is heated to a high temperature (1000-1200° C.) in order to epitaxially grow silicon on such a doped wafer, B.
Ｐ、 Ｓｂ、 Ａｓ等が基板ウェーハから飛び出し、エ
ピタキシャル成長層中に入る、所謂オートドープ現象が
発生して電気的特性を変化させてしまうことが知られて
いる。It is known that a so-called autodoping phenomenon occurs in which P, Sb, As, etc. jump out of the substrate wafer and enter the epitaxially grown layer, changing the electrical characteristics.
ウェーハからのＢ、 Ｐ、 Ｓｂ、 Ａｓ等の飛び出
しは表面側はエピタキシャル成長層の形成によって抑制
されるので、主としてウェーハの周面及び裏面側からで
ある。そこで従来にあってはこの部分にオートドープを
防止するためにブロッキング膜として５ｉＯｚ及び／又
はＳｉ３Ｎ＋等の膜を形成する方法が採られている。B, P, Sb, As, and the like are prevented from flying out from the wafer on the front surface side by the formation of an epitaxial growth layer, and therefore mainly from the peripheral surface and back surface side of the wafer. Conventionally, therefore, a method has been adopted in which a film of 5iOz and/or Si3N+ is formed as a blocking film in this portion to prevent autodoping.
第７図は従来のウェーハにエピタキシャル層を形成する
過程の説明図であり、第７図（イ）に示す如く円板形ウ
ェーハｌの周縁部を取扱い時の欠損等を防止するため上
、下から面取りして周面を傾斜面１ａ、 ｌｂ及びこの
間の弧状部ＩＣからなるよう形成し、化学的エツチング
にてダメージ層を除去した後、常圧ＣｖＤ法、熟酸化法
にてウェーハ１にブロッキング膜を形成する。第７図（
ロ）は常圧ＣＶＤ法に依って、また第７図（口′）は熱
酸化法に依って５ｉ０２及び／又はＳｉ３Ｎ４裂のブロ
ッキング膜を１又は２層積層形成した場合を夫々示して
いる。常圧ＣＶＤ法に依った場合、ブロッキング膜はウ
ェーハｌの主面では薄くなり、熱酸化法に依った場合は
全面に亘って略一様な厚さとなる。FIG. 7 is an explanatory diagram of the conventional process of forming an epitaxial layer on a wafer. As shown in FIG. The wafer 1 is chamfered to form a peripheral surface consisting of inclined surfaces 1a and 1b and an arc-shaped portion IC between them, and after removing the damaged layer by chemical etching, blocking is performed on the wafer 1 by an atmospheric pressure CvD method and a mature oxidation method. Forms a film. Figure 7 (
B) shows a case in which one or two layers of 5i02 and/or Si3N4 blocking film are laminated by an atmospheric pressure CVD method, and FIG. 7 (a) by a thermal oxidation method. When the atmospheric pressure CVD method is used, the blocking film is thin on the main surface of the wafer l, and when the thermal oxidation method is used, the blocking film has a substantially uniform thickness over the entire surface.
ブロッキング膜２の形成が終了すると、ウェーハ１の主
面にポリッシングを施し、主面上に形成されたブロッキ
ング膜２を研磨除去すると共に主面を鏡面に仕上げる。When the formation of the blocking film 2 is completed, the main surface of the wafer 1 is polished to remove the blocking film 2 formed on the main surface and finish the main surface into a mirror surface.
これによって第７図（ハ）に示す如く裏側全面及び周面
のうち主面側の傾斜面１ａの略半分を除く部分にブロッ
キング膜２を付着させたウェーハ１を得る。このような
ウェーハ１の主面に第７図（ニ）に示す如くエピタキシ
ャル層３を形成する。As a result, as shown in FIG. 7(c), a wafer 1 is obtained in which the blocking film 2 is adhered to the entire back side and the peripheral surface except approximately half of the inclined surface 1a on the main surface side. An epitaxial layer 3 is formed on the main surface of the wafer 1 as shown in FIG. 7(d).
ところで上述の如くして得たブロッキング膜２を有する
ウェーハｌを用いてその主面上にシリコンのエピタキシ
ャル成長を行うと、た゛しかにウェーハ１の主面にエピ
タキシャル層３が形成されてゆ（過程ではウェーハ１の
周面及び裏面にはブロッキング膜２が形成されているた
め、ウェー７１１からエピタキシャルＮ３へのオートド
ープは著しく抑制され、エピタキシャル層３自体の品質
の向上は図れる。By the way, when epitaxial growth of silicon is performed on the main surface of the wafer 1 having the blocking film 2 obtained as described above, it is true that the epitaxial layer 3 is formed on the main surface of the wafer 1 (in the process). Since the blocking film 2 is formed on the circumferential surface and the back surface of the wafer 1, autodoping from the wafer 711 to the epitaxial N3 is significantly suppressed, and the quality of the epitaxial layer 3 itself can be improved.
第８図はブロッキング膜を形成した場合（実線）と形成
しない場合（破線）とにおけるオートドープの程度をＳ
Ｒ（スプレディングレジスタンス）の検査結果として示
すグラフであり、横軸にエピタキシャル層表面からの深
さを、また縦軸に不純物濃度（対数任意単位）をとって
示してあり、エピタキシャル層における不純物濃度はブ
ロッキング膜を形成することによって格段に低減せしめ
られていることが解る。Figure 8 shows the degree of autodoping S when a blocking film is formed (solid line) and when it is not formed (broken line).
This is a graph showing the test results of R (spreading resistance), where the horizontal axis shows the depth from the surface of the epitaxial layer, and the vertical axis shows the impurity concentration (logarithmic arbitrary unit), which shows the impurity concentration in the epitaxial layer. It can be seen that this is significantly reduced by forming the blocking film.
しかし反面においては第７図（ニ）からも明らかなよう
にウェーハ１の主面へのエピタキシャル成長過程で、反
応ガス中のシリコンがポリシリコンとしてブロッキング
ｌｌ１１２、特にウェーハ１の周面部上に多数塊粒状に
生成され、この塊粒状シリコン３ａが半導体デバイス（
ｊ！！品）の製造過程でブロッキング膜の表面から脱落
し、エピタキシャル層３表面等に付着して汚染の原因と
なり、歩留を低下させるという問題があった。However, on the other hand, as is clear from FIG. 7(d), during the epitaxial growth process on the main surface of the wafer 1, silicon in the reaction gas blocks as polysilicon1112, especially on the peripheral surface of the wafer 1 in the form of many lumps and grains. This lumpy and granular silicon 3a is produced in a semiconductor device (
j! ! There was a problem in that during the manufacturing process of the blocking film, it fell off from the surface of the blocking film and adhered to the surface of the epitaxial layer 3, causing contamination and reducing the yield.
第９図（イ）は第７図（ニ）の■−■線による顕微鏡写
真図、また第９図（ロ）は第７図（ニ）の■′−■′線
による顕微鏡写真図である。これかられかるように周面
のブロッキング膜表面にはＳｉの塊粒状物が多数生成さ
れている。Figure 9 (a) is a micrograph taken along the line ■-■ in Figure 7 (d), and Figure 9 (b) is a microscope photograph taken along the line ■'-■' in Figure 7 (d). . As will be seen, many lumps and particles of Si are generated on the surface of the blocking film on the peripheral surface.
本発明はかかる事情に鑑みてなされたものであって、そ
の目的とするところはＳｉの塊粒状物が周面のブロッキ
ング膜上に形成されることに着目して、ウェーハの周面
、更にはオートドープの影響が許容できる範囲内で裏面
のブロッキング膜を可及的に広範囲に除去することによ
ってＳｔ塊粒状物の生成が殆どなく、これに起因する汚
染を防止出来て、歩留の大幅な向上を図り得るようにし
た半導体ウェーハ及びその製造方法を提供するにある。The present invention has been made in view of the above circumstances, and its purpose is to focus on the fact that Si lumps and particles are formed on the blocking film on the peripheral surface of the wafer, and to By removing the blocking film on the back side as widely as possible within the allowable range of autodoping, there is almost no generation of St lumps and particles, and contamination caused by this can be prevented, resulting in a significant increase in yield. It is an object of the present invention to provide a semiconductor wafer and a method for manufacturing the same that can improve the performance of the semiconductor wafer.
本発明に係る半導体ウェーハは、その周縁部を除く裏面
にオートドープ防止用のブロッキング膜を有しているこ
とを特徴とする。The semiconductor wafer according to the present invention is characterized in that it has a blocking film for preventing autodoping on the back surface except for the peripheral portion thereof.
以下本発明をその実施例を示す図面に基づき具体的に説
明する。第１図は本発明に係る半導体ウェーハ（以下本
発明品という）の断面構造図であり、図中ｌはＳｉ製の
半導体ウェーハ（以下単にウェーハという）を示してい
る。ウェーハ１の周面は上、下から周縁部の面取りをし
て傾斜面１ａ、Ｉｂ及びこの両頭斜面１ａ、 ｌｂの外
端縁を結ぶ略円弧状をなす弧状部ＩＣからなり、また裏
面には下側の傾斜面１ｂの端縁部から数龍（３ｆｌ程度
）中心側に寄った位置までを除く裏側全面にブロッキン
グ膜２が付着せしめられている。ブロッキング膜は５ｉ
０２（又は５ｉ３Ｎ４）製であって厚さは０．１〜１μ
鰯程度である。このブロッキング膜２の形成域は必ずし
も上述の範囲に限るものではな（、Ｓｉの塊粒状物が形
成され易いウェーハの周面、即ち傾斜面１ａ＋ ｌｂ及
び弧状部ＩＣ１を除くウェーハ１の裏側であって、オー
トドープの影響が許容できる範囲であればよい。なおブ
ロッキング膜２の領域を過小にするとオートドープ現象
が発生して電気特性を変えてしまうことになるので好ま
しくない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a cross-sectional structural diagram of a semiconductor wafer according to the present invention (hereinafter referred to as a product of the present invention), and in the figure l indicates a semiconductor wafer made of Si (hereinafter simply referred to as a wafer). The circumferential surface of the wafer 1 consists of inclined surfaces 1a, Ib whose peripheral edges are chamfered from the top and bottom, and an arc-shaped portion IC forming a substantially circular arc connecting the outer edges of the double-ended inclined surfaces 1a, lb. A blocking film 2 is adhered to the entire back side of the lower inclined surface 1b except for the area from the edge to a position closer to the center by about 3 fl. The blocking film is 5i
Made of 02 (or 5i3N4) and has a thickness of 0.1 to 1μ
It's about the same size as a sardine. The formation area of the blocking film 2 is not necessarily limited to the above-mentioned range (the peripheral surface of the wafer where Si lumps and particles are likely to be formed, that is, the back side of the wafer 1 excluding the inclined surface 1a + lb and the arcuate portion IC1). The effect of autodoping may be within an allowable range. However, if the area of the blocking film 2 is made too small, an autodoping phenomenon will occur and the electrical characteristics will change, which is not preferable.
ブロッキング膜２の材質は５ｉ０２膜のみに限るもので
はなく、Ｓｉ３Ｎ４膜、或いは５ｉ０２ 、 Ｓｉ３
Ｎ４夫々を材料とする２つの膜を積層形成して構成して
もよい。The material of the blocking film 2 is not limited to 5i02 film, but may also be Si3N4 film, 5i02, Si3
It may also be constructed by laminating two films each made of N4.
第２図は上記した本発明品の製造工程を示す模式図であ
り、先ず第２図（イ）に示す如く、ウェーハ１はその周
囲を面取りして傾斜面１ａ、 ｌｂ及び弧状部１ｃを形
成しておき、これに第２図（ロ）。FIG. 2 is a schematic diagram showing the manufacturing process of the product of the present invention described above. First, as shown in FIG. Now, here is Figure 2 (b).
（口′）に示す如くブロッキング膜２を付着せしめる。A blocking film 2 is attached as shown in (portion').
例えば常圧ＣＶＤ法に依る場合はウェーハｌの主面１ｄ
を下側にして反応炉内のバンド（図示せず）上に配置し
、ウェーハ１を加熱して上側に向けた下面及び傾斜面１
ａ、 ｌｂ、弧状部１ｃを含む周面に５ｉ０２ （及
び／又は５ｉ３Ｎ４）を所要厚さく０．１〜１．０μ＋
ｗ）に付着せしめる。常圧ＣＶＤ法による場合はパッド
とウェーハ１の主面１ｄとの間には僅かであるが、隙間
が形成されるためブロッキング膜２は第２図（ロ）に示
す如くウェーハ１の裏面。For example, when using the atmospheric pressure CVD method, the main surface 1d of the wafer l
The wafer 1 is placed on a band (not shown) in the reactor with the wafer 1 facing downward, and the wafer 1 is heated to form a lower surface and an inclined surface 1 facing upward.
Apply 5i02 (and/or 5i3N4) to the required thickness of 0.1 to 1.0 μ+ on the peripheral surface including a, lb, and arcuate portion 1c.
w). In the case of atmospheric pressure CVD, a small gap is formed between the pad and the main surface 1d of the wafer 1, so the blocking film 2 is formed on the back surface of the wafer 1 as shown in FIG. 2(b).
周面ば勿論、主面１ｄにも薄く形成されることとなる。It is formed thinly not only on the peripheral surface but also on the main surface 1d.
なお、常圧ＣＶＤ法に代えて熱酸化法によって形成して
もよく、この場合は第２図（口′）に示す如くウェーハ
１の全表面にわたって略均−にブロッキング膜２が形成
されることとなる。Note that the blocking film 2 may be formed by a thermal oxidation method instead of the atmospheric pressure CVD method, and in this case, the blocking film 2 is formed approximately uniformly over the entire surface of the wafer 1 as shown in FIG. becomes.
ブロッキング膜２の形成を終了した基板１は第２図（ハ
）、（ハ′）に示す如くウェーハｌの少なくとも傾斜面
１ａ、 ｌｂ及び弧状部１ｃを含む周面、又はこれを越
えて更にウェーハ１の裏面の周縁部、即ち端縁部から中
心側にＯ〜５鶴程度迄に形成されているブロッキング膜
２を除去する。第３．４図は上述した部分のブロッキン
グ膜２の除去方法を示す模式図であり、第３図は化学エ
ツチング法、第４図は機械研磐法による場合を示してい
る。The substrate 1 on which the blocking film 2 has been formed is further coated on the circumferential surface of the wafer l including at least the inclined surfaces 1a, lb and the arcuate portion 1c, or beyond this, as shown in FIGS. 1, the blocking film 2 formed from the peripheral edge, that is, from the edge to the center, is removed. FIG. 3.4 is a schematic diagram showing a method for removing the blocking film 2 in the above-mentioned portion, with FIG. 3 showing a method using a chemical etching method and FIG. 4 showing a method using a mechanical polishing method.
第３図はウェーハ１を回転駆動軸１１のチャック１２に
固定し、駆動軸１１回りに回転させつつウェーハ１の周
面を含む除去すべきブロッキング膜２表面に、エツチン
グ液を浸み込ませた不織布１３を内蔵するヘッド１４を
押し当ててウェーハ１の周面及び一部表、裏面にわたる
ブロッキング膜２を除去し、第２図（ハ）に示す如く周
面及び周縁部を除く主面、裏面にブロッキング膜２を残
したウェーハ１を得る。In FIG. 3, the wafer 1 is fixed to the chuck 12 of the rotary drive shaft 11, and while the wafer 1 is being rotated around the drive shaft 11, the etching solution is soaked into the surface of the blocking film 2 to be removed, including the circumferential surface of the wafer 1. The head 14 containing the nonwoven fabric 13 is pressed against the blocking film 2 covering the circumferential surface and partially the front and back surfaces of the wafer 1, and the main and back surfaces excluding the circumferential surface and the peripheral edge are removed as shown in FIG. 2(c). A wafer 1 with the blocking film 2 left on is obtained.
第４図に示す機械的研磨法はウェーハ１を同じく回転駆
動軸１１のチャック１２に固定し、ウェーハｌを回転さ
せつつポリッシング砥石１５をウェーハ１の周面におけ
る傾斜面１ａ＋弧状部１ｃ、 傾斜面１ｂ。In the mechanical polishing method shown in FIG. 4, the wafer 1 is similarly fixed to the chuck 12 of the rotary drive shaft 11, and while the wafer 1 is being rotated, the polishing grindstone 15 is moved along the circumferential surface of the wafer 1 on the inclined surface 1a + the arcuate portion 1c, and the inclined surface. 1b.
更には主面、裏面の周縁部にわたるよう移動させてブロ
ッキング膜２を除去するようになっている。Furthermore, the blocking film 2 is removed by moving it over the peripheral edges of the main surface and the back surface.
次に裏面及び主面にブロッキングＩ！１ｉ１２を付着さ
せた状態のウェーハ１の主面ｌｄ側に鏡面加工を施し、
主面１ｄに形成されているブロッキング膜２を除去する
と共に、主面１ｄを鏡面に仕上げて第１図に示す如き本
発明品を得る。なお上述の実施例ではウェーハエの周面
に対するプロンキング膜の除去を行った後、主面１ｄに
対する鏡面加工を行う場合につき説明したが、先に主面
１ｄに対する鏡面加工を施すこととしてもよい。Next, blocking I on the back and main surfaces! A mirror finish is applied to the main surface ld side of the wafer 1 with 1i12 attached,
The blocking film 2 formed on the main surface 1d is removed and the main surface 1d is finished to a mirror surface to obtain the product of the present invention as shown in FIG. In the above-mentioned embodiment, the main surface 1d is mirror-finished after the pronking film is removed from the peripheral surface of the wafer, but the main surface 1d may be mirror-finished first.
第５図は上述の如くして得た第１図に示す如きｉ：ｒ−
−ハｌの主面ｌａ上にエピタキシャルＮヲＨＩＦｇ形成
した状態の模式的断面図であり、図中３はエピタキシャ
ル層を示している。他の部分は第１図に示す実施例と同
じであり、対応する部分には同じ番号を付して説明を省
略する。FIG. 5 shows i:r- as shown in FIG. 1 obtained as described above.
3 is a schematic cross-sectional view of a state in which an epitaxial NOHIFg is formed on the main surface la of the - shell 1, and 3 in the figure indicates an epitaxial layer. Other parts are the same as those in the embodiment shown in FIG. 1, and corresponding parts are given the same numbers and explanations are omitted.
第６図（イ）は第５図に示す如き本発明品の周縁部をＶ
−Ｖ線側から撮影した顕微鏡写真、第６図（ロ）は同じ
く本発明品の主面にエピタキシャル成長層を形成した状
態の周面をｖ’−ｖ’線側から撮影した顕微鏡写真を示
している。Figure 6 (a) shows the peripheral part of the product of the present invention as shown in Figure 5.
Figure 6 (b) is a micrograph taken from the v'-v' line of the peripheral surface of the product of the present invention with an epitaxial growth layer formed on the main surface. There is.
これら各写真から明らかなように、従来品にあっては第
９図（ロ）に示す如く塊粒状シリコン３ａがウェーハ周
面に多数形成されているが、本発明品には第６図（ロ）
に示す如＜Ｓｔ塊粒が全（生成されていないことが解る
。As is clear from these photographs, in the conventional product, a large number of lump-grain silicon 3a are formed on the wafer circumferential surface as shown in FIG. 9 (b), but in the product of the present invention, as shown in FIG. )
As shown in the figure, it can be seen that all the aggregates are not produced.
〔効果〕
以上の如く本発明品及び本発明方法にあってはブロッキ
ング膜をウェーハの裏面にのみ形成しであるからエピタ
キシャル成長を行う過程で反応ガスがウェーハ周面と接
触してもＳｉ塊粒が生成されることがなく、従って半導
体デバイスの製造工程において塊粒状シリコンがウェー
ハ表面から親藩しウェーハ土面に付着して汚染の原因と
なることがないという優れた効果を奏するものである。[Effect] As described above, in the product and method of the present invention, the blocking film is formed only on the back surface of the wafer, so even if the reaction gas comes into contact with the wafer peripheral surface during the epitaxial growth process, no Si lumps are formed. Therefore, in the manufacturing process of semiconductor devices, silicon granules are not generated from the wafer surface and adhere to the wafer soil surface, which is an excellent cause of contamination.
第１図は本発明品の断面図、第２図は本発明方法の製造
過程を示す説明図、第３．４図はウェーハに形成したブ
ロッキング膜の除去方法の実施状態を示す模式図、第５
図は第１図に示すウェーハ上にエピタキシャル層を形成
したときの断面図、第６図（イ）は第５図のＶ−Ｖ線方
向からみた顕微鏡写真図、第６図（ロ）は第５図のｖ’
−ｖ’線からみた顕微鏡写真図、第７図は従来品の製造
工程を示す説明図、第８図はウェーハからエピタキシャ
ル層への不純物の拡散状態を示すグラフ、第９図（イ）
は第７図（ニ）の■−■線による顕微鏡写真図、第９図
（ロ）は第７図（ニ）の■′−■′線による顕微鏡写真
図である。
１・・・ウェーハ ｌａ、 ｌｂ・・・傾斜面 １ｃ・
・・弧状部２・・・ブロッキング膜 ３・・・エピタキ
シャル層特 許 出願人 九州電子金屈株式会社代理
人 弁理士 河 野 登 夫算 １ 因
！
（イｌ ｌｂ
＄ ２ 図
算 ３ 凹
＄ ４ 図
箒 ５ 悶
図面の浄ＩＦ（内η
一−１ｏｏ、ｇ鴎−一
（ロ）
に変更なし）
（イ）
第 ９ 図
手続補正書（方式）
％式％
１、事件の表示
昭和６０年特許願第２６’１８３８号
２、発明の名称
半導体ウェーハ及びその製造方法
３、補正をする者
事件との関係 特許出願人
所在地 佐賀県杵島郡江北町大字上小田２２０１番地名
称 九州電子金属株式会社
代表者 池 島 俊 雄
４、代理人 〒５４３
住 所 大阪市天王寺区四天王寺１丁目１４番２２号
日進ビル２０７号
河畔特許事務所（電話０６−７７９−３０８８ ）昭和
６１年２月５日（発送日６１． ２．２５）「図面の簡
単な説明」の欄及び図面
７、ｉ＃正の内容
７−１「図面の簡単な説明」の欄
（１１明細書の第１２頁１３行目乃至１５行目に［第６
図（イ）は・・・顕微鏡写真図、」とあるを次のとおり
に訂正する。
「第６図（イ）は第５図のＶ−Ｖ線方向からみた模式的
部分平面図、第６図（ロ）は第５図のＶ′−ｖ’線の方
向からみた模式的部分側面図、」（２） 第１２頁１
８行目乃至２０行目に「第９図（イ）は・・・顕微鏡写
真図」とあるを、次のとおりに訂正する。
「第９図（イ）は第７図（ニ）の■−■線方向からみた
模式的部分平面図、第９図（ロ）は第７図（ニ）の■′
−■′線の方向からみた。模式的部分側面図」
７−２図面
第６，９図を別紙のとおりに訂正する。
８、 添付Ｗ頬の目録
（１） 訂正図面 １通手続
補正書（自発）
昭和６１年３月４日Fig. 1 is a sectional view of the product of the present invention, Fig. 2 is an explanatory diagram showing the manufacturing process of the method of the invention, Figs. 5
The figure is a cross-sectional view when an epitaxial layer is formed on the wafer shown in Figure 1, Figure 6 (A) is a micrograph taken from the V-V line direction in Figure 5, and Figure 6 (B) is a cross-sectional view of the epitaxial layer formed on the wafer shown in Figure 1. v' in Figure 5
A microscopic photograph seen from the -v' line, Figure 7 is an explanatory diagram showing the manufacturing process of the conventional product, Figure 8 is a graph showing the state of impurity diffusion from the wafer to the epitaxial layer, and Figure 9 (A).
7(d) is a microscopic photograph taken along the line ■-■, and FIG. 9(b) is a microscopic photograph taken along the line ■'--■' of FIG. 7(d). 1... Wafer la, lb... Inclined surface 1c.
...Arc-shaped portion 2...Blocking film 3...Epitaxial layer patent Applicant Kyushu Denshi Konku Co., Ltd. Agent Patent attorney Noboru Kono 1 Reason! (Il lb $ 2 Diagram calculation 3 Concave $ 4 Zuhoki 5 Agon drawing's clean IF (in η 1-1oo, g-1 (b) No change) (a) Part 9 Diagram procedural amendment (method) % formula % 1. Indication of the case 1985 Patent Application No. 26'1838 2. Name of the invention Semiconductor wafer and its manufacturing method 3. Person making the amendment Relationship to the case Patent applicant location Oaza, Kohoku-cho, Kishima-gun, Saga Prefecture 2201 Kamioda Name: Kyushu Electronic Metals Co., Ltd. Representative: Toshio Ikeshima 4, Agent: 543 Address: 1-14-22 Shitennoji, Tennoji-ku, Osaka City
Nisshin Building No. 207 Kawahan Patent Office (Telephone: 06-779-3088) February 5, 1985 (shipment date 61.2.25) "Brief explanation of drawings" column and drawing 7, i# positive contents 7-1 “Brief explanation of the drawings” column (page 12, lines 13 to 15 of [11 specifications] [6
The statement "Figure (a) is a microscopic photograph" should be corrected as follows. "Figure 6 (a) is a schematic partial plan view seen from the V-V line direction in Figure 5, and Figure 6 (b) is a schematic partial side view seen from the V'-v' line direction in Figure 5. Figure,” (2) Page 12 1
In lines 8 to 20, the statement ``Figure 9 (a) is a microscopic photograph'' should be corrected as follows. ``Figure 9 (a) is a schematic partial plan view of Figure 7 (d) seen from the ■-■ line direction, Figure 9 (b) is Figure 7 (d) ■''
Viewed from the direction of the −■′ line. "Schematic Partial Side View" Figures 6 and 9 of the 7-2 drawing are corrected as shown in the attached sheet. 8. Attached W Cheek Inventory (1) Corrected drawings 1 copy Procedural amendment (voluntary) March 4, 1985
Claims (1)
ッキング膜を備えることを特徴とする半導体ウェーハ。 ２、前記オートドープ防止用のブロッキング膜が、シリ
コンの酸化膜、窒化膜、又は酸化膜と窒化膜の複合二層
構造よりなる膜である特許請求の範囲第１項記載の半導
体ウェーハ。 ３、その周縁部を除く裏面にオートドープ防止用のブロ
ッキング膜を備え、主面にはエピタキシャル層を成長せ
しめてなることを特徴とする半導体ウェーハ。 ４、前記オートドープ防止用のブロッキング膜が、シリ
コンの酸化膜、窒化膜、又は酸化膜と窒化膜の複合二層
構造よりなる膜である特許請求の範囲第３項記載の半導
体ウェーハ。 ５、半導体ウェーハの主面を除く、表面の一部にオート
ドープ防止用のブロッキング膜を形成した円盤状の半導
体ウェーハを製造する方法において、少なくとも半導体
ウェーハの主面と反対側の裏側の全面及び周面に亘って
ブロッキング膜を形成する工程と、前記周面のブロッキ
ング膜を除去する工程とを有することを特徴とする半導
体ウェーハの製造方法。[Claims] 1. A semiconductor wafer, characterized in that a blocking film for preventing autodoping is provided on the back surface of the wafer except for the peripheral edge thereof. 2. The semiconductor wafer according to claim 1, wherein the blocking film for preventing autodoping is a silicon oxide film, a silicon nitride film, or a film having a composite two-layer structure of an oxide film and a nitride film. 3. A semiconductor wafer comprising a blocking film for preventing autodoping on the back surface except for the peripheral portion thereof, and an epitaxial layer grown on the main surface. 4. The semiconductor wafer according to claim 3, wherein the blocking film for preventing autodoping is a silicon oxide film, a nitride film, or a film having a composite two-layer structure of an oxide film and a nitride film. 5. In a method for manufacturing a disk-shaped semiconductor wafer in which a blocking film for preventing autodoping is formed on a part of the surface, excluding the main surface of the semiconductor wafer, at least the entire back surface of the semiconductor wafer opposite to the main surface and A method for manufacturing a semiconductor wafer, comprising the steps of forming a blocking film over the circumferential surface, and removing the blocking film from the circumferential surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60269838A JP2546986B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor wafer and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60269838A JP2546986B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor wafer and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62128520A true JPS62128520A (en) | 1987-06-10 |
| JP2546986B2 JP2546986B2 (en) | 1996-10-23 |
Family
ID=17477886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60269838A Expired - Fee Related JP2546986B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor wafer and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546986B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03145720A (en) * | 1989-10-31 | 1991-06-20 | Oki Electric Ind Co Ltd | Compound semiconductor growth method and silicon substrate to be used thereon |
| JPH05251371A (en) * | 1992-07-20 | 1993-09-28 | Rohm Co Ltd | Manufacture of semiconductor device |
| EP0826801A2 (en) * | 1996-08-27 | 1998-03-04 | Shin-Etsu Handotai Company, Limited | Silicon substrate manufacture |
| KR20030043697A (en) * | 2001-11-26 | 2003-06-02 | 가부시끼가이샤 도시바 | Method of manufacturing semiconductor device and polishing device |
| JP2004152920A (en) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Method of manufacturing semiconductor device and method of managing semiconductor manufacturing process |
| JP2008109125A (en) * | 2006-09-29 | 2008-05-08 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Silicon single-crystal substrate, and its manufacturing method |
| JP2009200501A (en) * | 2009-03-13 | 2009-09-03 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor apparatus |
| JP2011114210A (en) * | 2009-11-27 | 2011-06-09 | Sumco Corp | Method of manufacturing epitaxial wafer |
| JP2011119336A (en) * | 2009-12-01 | 2011-06-16 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device and semiconductor substrate to be used therefor |
| JP2011251855A (en) * | 2010-05-31 | 2011-12-15 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| JP2012142485A (en) * | 2011-01-05 | 2012-07-26 | Sumco Corp | Manufacturing method of epitaxial wafer and the epitaxial wafer |
| US8241423B2 (en) | 2006-09-29 | 2012-08-14 | Sumco Techxiv Corporation | Silicon single crystal substrate and manufacture thereof |
| JP2013191889A (en) * | 2013-06-21 | 2013-09-26 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer |
| JPWO2013108335A1 (en) * | 2012-01-19 | 2015-05-11 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| US9064809B2 (en) | 2012-02-29 | 2015-06-23 | Sumco Corporation | Method for removing oxide film formed on surface of silicon wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979780A (en) * | 1972-12-08 | 1974-08-01 | ||
| JPS52144269A (en) * | 1976-05-27 | 1977-12-01 | Mitsubishi Metal Corp | Method of chamfering single crystal wafers |
| JPS5895819A (en) * | 1981-12-02 | 1983-06-07 | Toshiba Corp | Semiconductor wafer |
-
1985
- 1985-11-29 JP JP60269838A patent/JP2546986B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979780A (en) * | 1972-12-08 | 1974-08-01 | ||
| JPS52144269A (en) * | 1976-05-27 | 1977-12-01 | Mitsubishi Metal Corp | Method of chamfering single crystal wafers |
| JPS5895819A (en) * | 1981-12-02 | 1983-06-07 | Toshiba Corp | Semiconductor wafer |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03145720A (en) * | 1989-10-31 | 1991-06-20 | Oki Electric Ind Co Ltd | Compound semiconductor growth method and silicon substrate to be used thereon |
| JPH05251371A (en) * | 1992-07-20 | 1993-09-28 | Rohm Co Ltd | Manufacture of semiconductor device |
| EP0826801A2 (en) * | 1996-08-27 | 1998-03-04 | Shin-Etsu Handotai Company, Limited | Silicon substrate manufacture |
| EP0826801A3 (en) * | 1996-08-27 | 1998-11-11 | Shin-Etsu Handotai Company, Limited | Silicon substrate manufacture |
| US5882401A (en) * | 1996-08-27 | 1999-03-16 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing silicon single crystal substrate for use of epitaxial layer growth |
| KR20030043697A (en) * | 2001-11-26 | 2003-06-02 | 가부시끼가이샤 도시바 | Method of manufacturing semiconductor device and polishing device |
| JP2004152920A (en) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Method of manufacturing semiconductor device and method of managing semiconductor manufacturing process |
| US8241423B2 (en) | 2006-09-29 | 2012-08-14 | Sumco Techxiv Corporation | Silicon single crystal substrate and manufacture thereof |
| JP2008109125A (en) * | 2006-09-29 | 2008-05-08 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Silicon single-crystal substrate, and its manufacturing method |
| JP2009200501A (en) * | 2009-03-13 | 2009-09-03 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor apparatus |
| JP2011114210A (en) * | 2009-11-27 | 2011-06-09 | Sumco Corp | Method of manufacturing epitaxial wafer |
| JP2011119336A (en) * | 2009-12-01 | 2011-06-16 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device and semiconductor substrate to be used therefor |
| JP2011251855A (en) * | 2010-05-31 | 2011-12-15 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| JP2012142485A (en) * | 2011-01-05 | 2012-07-26 | Sumco Corp | Manufacturing method of epitaxial wafer and the epitaxial wafer |
| JPWO2013108335A1 (en) * | 2012-01-19 | 2015-05-11 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| US9064809B2 (en) | 2012-02-29 | 2015-06-23 | Sumco Corporation | Method for removing oxide film formed on surface of silicon wafer |
| JP2013191889A (en) * | 2013-06-21 | 2013-09-26 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer |
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| Publication number | Publication date |
|---|---|
| JP2546986B2 (en) | 1996-10-23 |
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