JP2001113459A - Polishing method of semiconductor substrate with protective film - Google Patents
Polishing method of semiconductor substrate with protective filmInfo
- Publication number
- JP2001113459A JP2001113459A JP29242699A JP29242699A JP2001113459A JP 2001113459 A JP2001113459 A JP 2001113459A JP 29242699 A JP29242699 A JP 29242699A JP 29242699 A JP29242699 A JP 29242699A JP 2001113459 A JP2001113459 A JP 2001113459A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- semiconductor substrate
- protective film
- silicon wafer
- surface plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は保護膜付半導体基板
の研磨方法に係わり、特に、保護膜を損傷することなく
高平坦度の保護膜付半導体基板が得られる保護膜付半導
体基板の研磨方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a semiconductor substrate with a protective film, and more particularly, to a method for polishing a semiconductor substrate with a protective film that can obtain a semiconductor substrate with a high flatness without damaging the protective film. About.
【０００２】[0002]
【従来の技術】半導体製造技術において、個別回路素
子、集積回路素子等の各種の回路素子を形成する場合、
Ｐ型またはＮ型シリコンウェーハ上にＰ−またはＮ＋の
エピタキシャル（以下エピという）層を形成したエピウ
ェーハが用いられ、このエピウェーハのエピ層に各種の
回路素子を形成する。このエピ層を形成する際、主とし
てシリコンウェーハの裏面から不純物（ドーパント）が
エピタキシャル層表面に拡散され、エピ層の抵抗分布に
バラツキを生じ、所望の不純物濃度のエピ層が得られな
くなるいわゆるオートドープ現象が問題になる。2. Description of the Related Art In semiconductor manufacturing technology, when various circuit elements such as individual circuit elements and integrated circuit elements are formed,
On the P-type or N-type silicon wafer P - or N + epitaxial epitaxial wafer was formed (hereinafter referred to as epi) layer is used for to form the various circuit elements in the epitaxial layer of the epitaxial wafer. When this epi layer is formed, impurities (dopants) are diffused mainly from the back surface of the silicon wafer to the surface of the epitaxial layer, causing variations in the resistance distribution of the epi layer, and so-called auto-doping that makes it impossible to obtain an epi layer having a desired impurity concentration. The phenomenon becomes a problem.
【０００３】この問題を回避するため、エピ層を形成す
る前にシリコンウェーハの裏面にＳｉＯ２の保護膜を形
成した保護膜付シリコンウェーハが製造され用いられて
いる。In order to avoid this problem, a silicon wafer with a protective film, in which a protective film of SiO 2 is formed on the back surface of the silicon wafer before forming the epi layer, has been manufactured and used.
【０００４】従来の保護膜付シリコンウェーハの製造方
法は、図１（ｂ）に示すような研磨工程を含む製造工程
により行う。A conventional method for manufacturing a silicon wafer with a protective film is performed by a manufacturing process including a polishing process as shown in FIG.
【０００５】例えば、シリコン単結晶から厚めに切出し
たシリコンウェーハをラップ処理、エッチング処理し、
厚さｔを有する厚めで基材がＳｉのシリコンウェーハｗ
０を用意する。[0005] For example, a silicon wafer cut thicker from a silicon single crystal is wrapped and etched.
A thick silicon wafer w having a thickness t and a base material of Si
Prepare 0 .
【０００６】１次研磨工程では、図２に示すような両面
研磨装置１を用い、キャリア２の外周囲に設けられたギ
ア３をインナギア４とサンギア５とに噛合させた状態
で、シリコンウェーハｗ０が収納されたキャリア２を、
研磨布６が貼付された下定盤７に載置し、研磨剤を供給
しながら、研磨布８が貼付された上定盤９をシリコンウ
ェーハｗ０に押圧し、下定盤７、上定盤９を回転させ、
シリコンウェーハｗ０を自転および公転させて、シリコ
ンウェーハｗ０の両面を研磨してシリコンウェーハｗ１
を得る。In the first polishing step, a silicon wafer w is used while a gear 3 provided on the outer periphery of the carrier 2 is meshed with an inner gear 4 and a sun gear 5 using a double-side polishing apparatus 1 as shown in FIG. 0 is stored in the carrier 2
Polishing cloth 6 is placed on the lower platen 7 affixed, while supplying a polishing agent, the upper surface plate 9 to the polishing pad 8 is affixed to press the silicon wafer w 0, the lower surface plate 7, the upper surface plate 9 Rotate
The silicon wafer w 0 by rotation and revolution, the silicon wafer w1 to polish both surfaces of the silicon wafer w 0
Get.
【０００７】次に、保護膜形成工程では、両面研磨した
シリコンウェーハｗ１を原料ガスＧが供給される４００
℃近傍の温度の常圧化学気相成長（ＣＶＤ）炉１０に導
入し、ＣＶＤによりＳｉＯ２膜ｍを一表面に形成し、保
護膜付シリコンウェーハｗ２を得る。保護膜形成工程に
おいて、回路等が形成されるエピ層形成面（他表面）ｅ
に傷等が発生するため、保護膜形成後、エピ層形成面ｅ
を２次研磨する必要がある。Next, in a protective film forming step, a silicon wafer w 1 polished on both sides is supplied with a source gas G 400.
Introduced into a normal pressure chemical vapor deposition (CVD) furnace 10 at a temperature of about 0 ° C., a SiO 2 film m is formed on one surface by CVD, and a silicon wafer w 2 with a protective film is obtained. In the protective film forming step, an epilayer forming surface (another surface) on which a circuit and the like are formed e
After the protective film is formed, the surface e where the epi layer is formed
Needs to be polished secondarily.
【０００８】２次研磨工程では、従来は図３に示すよう
な片面研磨装置１１を用いており、ワックスを用いてシ
リコンウェーハｗ２を片面研磨装置１１のプレート１２
に貼付け、研磨布１３が貼付された定盤１４を回転させ
るとともに、スラリを研磨布１３に供給し、シリコンウ
ェーハｗ２が貼付されたプレート１２を回転させながら
降下し、スラリが供給されて湿潤した研磨布１３に所定
荷重で押付けエピ層形成面ｅを研磨し、シリコンウェー
ハｗ３を得る。この２次研磨工程において、前保護膜形
成工程で発じた傷等を除去するために通常の研磨よりも
大きな研磨代を取る必要があるが、両面研磨装置に比べ
て平坦度の出しにくい片面研磨装置１１で大きな研磨代
を取って研磨するため、エピ層形成面ｅの平坦度が低下
する。[0008] In the secondary polishing step, conventionally employs a single-side polishing apparatus 11 as shown in FIG. 3, the plate 12 of the single-side polishing apparatus 11 of the silicon wafer w 2 using wax
Paste in, rotates the platen 14 polishing cloth 13 is stuck, and supplies the slurry to the polishing cloth 13, the plate 12 where the silicon wafer w 2 is attached descends while rotating, the slurry is supplied wet the polishing cloth 13 was polished epitaxial layer forming surface e pressed by predetermined load, to obtain a silicon wafer w 3. In this secondary polishing step, it is necessary to take a larger polishing allowance than normal polishing in order to remove scratches and the like generated in the pre-protection film forming step, but it is difficult to obtain a flat surface compared to a double-side polishing apparatus. Since the polishing is performed by the polishing apparatus 11 with a large polishing allowance, the flatness of the epilayer forming surface e is reduced.
【０００９】その理由としては、両面研磨装置による研
磨は、シリコンウェーハの両面に柔軟性のある研磨布を
当接、押圧するので、剛性を有する研磨基準面を持たな
いことから、シリコンウェーハの研磨面の平坦度は良好
に保持されるのに対し、両面研磨装置による片面研磨
は、剛性があり基準面となるプレートにシリコンウェー
ハを貼付け、柔軟性がある研磨布でシリコンウェーハの
他表面を研磨するため、研磨面の平坦度は両面研磨装置
により研磨した場合に比べて低下するのである。[0009] The reason is that the polishing by the double-side polishing apparatus abuts and presses a flexible polishing cloth on both sides of the silicon wafer, and therefore does not have a rigid polishing reference surface. While the flatness of the surface is kept good, single-side polishing with a double-side polishing machine sticks a silicon wafer to a rigid and reference surface plate and polishes the other surface of the silicon wafer with a flexible polishing cloth Therefore, the flatness of the polished surface is reduced as compared with the case of polishing by a double-side polishing apparatus.
【００１０】３次研磨工程では、２次研磨で得られたシ
リコンウェーハｗ３を研磨条件および研磨代を変えて多
めに研磨して、２次研磨で生じた平坦度の悪化を修正し
てエピ層形成面ｅの平坦なシリコンウェーハｗ４を得
る。[0010] 3 in the primary polishing process, was polished in generous by changing the polishing conditions and polishing allowance of the silicon wafer w 3 obtained in the secondary polishing, epi to correct the deterioration of the flatness generated in the secondary polishing obtaining a flat silicon wafer w 4 layers forming surface e.
【００１１】仕上げ研磨工程では、３次研磨で得られた
シリコンウェーハｗ４を研磨条件および研磨代を変えて
研磨し、シリコンウェーハｗを得る。上述のような工程
を経て保護膜付シリコンウェーハｗは次工程に送られ
る。[0011] In the final polishing process, the silicon wafer w 4 obtained in 3 primary polishing and polishing by changing the polishing conditions and polishing fee, obtain a silicon wafer w. The silicon wafer w with a protective film is sent to the next step through the steps described above.
【００１２】従来の２次研磨工程においては、片面研磨
装置１１を用いてシリコンウェーハｗ２の片面研磨する
ために、平坦度を出し難くく、従って、研磨代を大きく
する必要があり、また、２次研磨終了後にも１次研磨工
程において両面研磨装置を用いて研磨した研磨面よりも
平坦度げ低下しているので、３次研磨工程でも研磨代を
大きく取り、多めに研磨する必要があり、また、３次研
磨で多めに研磨しても、うねりが若干残ることが多い。[0012] In the conventional secondary polishing step, in order to single-side polishing of the silicon wafer w 2 with single-side polishing apparatus 11, Ku difficult issues flatness, therefore, it is necessary to increase the grinding allowance, also, Even after the completion of the secondary polishing, the degree of flatness is lower in the primary polishing step than in the polished surface polished using the double-side polishing apparatus. In addition, even if a large amount is polished by tertiary polishing, undulation often remains slightly.
【００１３】[0013]
【発明が解決しようとする課題】そこで、一表面に形成
された保護膜を損傷することなく、他表面が高平坦度の
保護膜付半導体基板が得られ、かつ研磨量が少なくコス
トダウンに寄与できる保護膜付半導体基板の研磨方法が
要望されている。Therefore, a semiconductor substrate with a protective film having a high flatness on the other surface can be obtained without damaging the protective film formed on one surface, and the polishing amount is small, contributing to cost reduction. There is a need for a method of polishing a semiconductor substrate with a protective film that can be performed.
【００１４】本発明は上述した事情を考慮してなされた
もので、一表面に形成された保護膜を損傷することな
く、他表面が高平坦度の保護膜付半導体基板が得られ、
かつ研磨量が少なくコストダウンに寄与できる保護膜付
半導体基板の研磨方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and provides a semiconductor substrate with a protective film having a high flatness on the other surface without damaging the protective film formed on one surface.
It is another object of the present invention to provide a method for polishing a semiconductor substrate with a protective film, which has a small polishing amount and can contribute to cost reduction.
【００１５】[0015]
【課題を解決するための手段】上記目的を達成するため
になされた本願請求項１の発明は、研磨剤を供給しなが
ら、研磨布が貼付された上定盤および下定盤間で半導体
基板を押圧、公転させて、半導体基板の両表面を研磨す
る半導体基板の両面研磨方法において、一表面に保護膜
が形成された半導体基板を上定盤および下定盤間に配置
し、前記一表面に当接する定盤を前記半導体基板の公転
速度の０．５〜１．５倍で回転させ、かつ研磨剤として
Ｐｈが１１以上の研磨液に平均粒径７０〜９０ｎｍのシ
リカ粒子を分散させたものを使用し、前記保護膜と前記
半導体基板の基材に対する研磨比率を１：１００以上に
することを特徴とする保護膜付半導体基板の研磨方法で
あることを要旨としている。Means for Solving the Problems According to the first aspect of the present invention, which has been made to achieve the above object, a semiconductor substrate is placed between an upper surface plate and a lower surface plate to which a polishing cloth is attached while supplying an abrasive. In a double-side polishing method for a semiconductor substrate, in which both surfaces of a semiconductor substrate are polished by pressing and revolving, a semiconductor substrate having a protective film formed on one surface is disposed between an upper surface plate and a lower surface plate, and the surface is contacted with the one surface. A platen in contact with was rotated at a speed of 0.5 to 1.5 times the revolution speed of the semiconductor substrate, and a polishing slurry having Ph of 11 or more and silica particles having an average particle size of 70 to 90 nm dispersed therein was used. The subject matter of the present invention is to provide a method for polishing a semiconductor substrate with a protective film, wherein a polishing ratio of the protective film to the base material of the semiconductor substrate is set to 1: 100 or more.
【００１６】本願請求項２の発明では、上記半導体基板
の基材はＳｉであることを特徴とする請求項１に記載の
保護膜付半導体基板の研磨方法であることを要旨として
いる。In the invention of claim 2 of the present application, the gist of the invention is the method of polishing a semiconductor substrate with a protective film according to claim 1, wherein the base material of the semiconductor substrate is Si.
【００１７】本願請求項３の発明では、上記保護膜はＳ
ｉＯ２であることを特徴とする請求項２に記載の保護膜
付半導体基板の研磨方法であることを要旨としている。According to the third aspect of the present invention, the protective film is made of S
It is summarized in that a method of polishing a semiconductor substrate with protective film according to claim 2, characterized in that the iO 2.
【００１８】[0018]
【発明の実施の形態】本発明に係わる保護膜付半導体基
板の研磨方法を用いた半導体基板の製造方法の実施形態
について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor substrate using a method for polishing a semiconductor substrate with a protective film according to the present invention will be described with reference to the drawings.
【００１９】本発明に係わる保護膜付半導体基板の研磨
方法を用いた半導体基板、例えばシリコンウェーハの製
造方法は、図１（ａ）に示すような研磨工程を含む製造
工程により行う。A method of manufacturing a semiconductor substrate, for example, a silicon wafer, using the method of polishing a semiconductor substrate with a protective film according to the present invention is performed by a manufacturing process including a polishing process as shown in FIG.
【００２０】シリコン単結晶から切出したシリコンウェ
ーハをラップ処理、エッチング処理し、得られた厚さＴ
を有する基材がＳｉのシリコンウェーハＷ０を用意す
る。A silicon wafer cut from a silicon single crystal is wrapped and etched to obtain a thickness T.
A substrate having to prepare a silicon wafer W 0 of Si.
【００２１】１次研磨工程では、図２に示すような両面
研磨装置１を用いて行ない、図２および図１（ａ）に示
すように、シリコンウェーハＷ０を収納したキャリア２
を、このキャリア２の外周囲に設けられたギア３をイン
ナギア４とサンギア５とに噛合させた状態で研磨布６が
貼付された下定盤７に載置し、例えば、ＮａＯＨやＫＯ
Ｈ等のアルカリ金属の水酸化物をシリカが分散したスラ
リに添加しｐＨ値を１０〜１１程度に調整した研磨剤を
供給しながら、研磨布８が貼付された上定盤９をシリコ
ンウェーハＷ０に押圧し、下定盤７、上定盤９を回転さ
せながら、シリコンウェーハＷ０を自転および公転させ
て、シリコンウェーハＷ０の両面を研磨し、シリコンウ
ェーハＷ１を得る。[0021] In the primary polishing step, performed using a double-side polishing apparatus 1 shown in FIG. 2, as shown in FIG. 2 and FIG. 1 (a), the carrier 2 housing the silicon wafer W 0
Is placed on a lower platen 7 on which a polishing cloth 6 is adhered in a state where a gear 3 provided on the outer periphery of the carrier 2 is meshed with an inner gear 4 and a sun gear 5, and for example, NaOH or KO
While an alkali metal hydroxide such as H is added to a slurry in which silica is dispersed and an abrasive whose pH value is adjusted to about 10 to 11 is supplied, the upper platen 9 on which the polishing cloth 8 is attached is moved to the silicon wafer W. 0 , and while rotating the lower surface plate 7 and the upper surface plate 9, the silicon wafer W 0 is rotated and revolved, and both surfaces of the silicon wafer W 0 are polished to obtain the silicon wafer W 1 .
【００２２】次に、保護膜形成工程では、図１（ａ）に
示すように、両面研磨したシリコンウェーハＷ１を、モ
ノシランと酸素とを一定割合で混合してなる原料ガスＧ
が供給される４００℃近傍の温度の常圧化学気相成長
（ＣＶＤ）炉１０に導入し、ＣＶＤにより２００〜１５
００ｎｍのＳｉＯ２膜ｍを一表面に形成し、保護膜付シ
リコンウェーハｗ２を得る。保護膜形成工程において、
回路等が形成されるエピ層形成面（他表面）ｅに傷等が
発生するため、保護膜形成後、エピ層形成面ｅを２次研
磨する必要がある。Next, in the protective film forming step, as shown in FIG. 1 (a), a silicon wafer W 1 to the double-side polishing, the raw material gas G made by mixing monosilane and oxygen at a constant rate
Is supplied to an atmospheric pressure chemical vapor deposition (CVD) furnace 10 at a temperature of about 400 ° C. where 200 to 15
The SiO 2 film m of 00nm was formed on one surface to obtain a protective film with a silicon wafer w 2. In the protective film forming step,
Since an epi-layer forming surface (other surface) e on which circuits and the like are formed has a flaw or the like, it is necessary to polish the epi-layer forming surface e after forming the protective film.
【００２３】２次研磨工程では、１次研磨工程と同様に
図２に示すような両面研磨装置１を用い、図２および図
１（ａ）に示すように、シリコンウェーハＷ２を収納し
たキャリア２を、このキャリア２の外周囲に設けられた
ギア３をインナギア４とサンギア５とに噛合させた状態
で研磨布６が貼付された下定盤７に載置し、研磨剤を供
給しながら、研磨布８が貼付された上定盤９をシリコン
ウェーハＷ２に押圧し、下定盤７、上定盤９を回転させ
ながら、シリコンウェーハＷ２を自転および公転させ
て、シリコンウェーハＷ２の両面を研磨し、シリコンウ
ェーハＷ３を得る。[0023] In the secondary polishing step, using a double-side polishing apparatus 1 shown in FIG. 2 similarly to the primary polishing step, as shown in FIG. 2 and FIG. 1 (a), the carrier accommodating the silicon wafer W 2 2 is placed on a lower platen 7 on which a polishing cloth 6 is adhered in a state where a gear 3 provided on the outer periphery of the carrier 2 is meshed with an inner gear 4 and a sun gear 5, while supplying an abrasive. the upper surface plate 9 to the polishing pad 8 is affixed to press the silicon wafer W 2, the lower surface plate 7, while rotating the upper polishing plate 9, a silicon wafer W 2 by rotation and revolution, both surfaces of the silicon wafer W 2 polished to obtain a silicon wafer W 3.
【００２４】この２次研磨工程において、シリコンウェ
ーハＷ２の一表面に当接する定盤、例えば上定盤９をシ
リコンウェーハの公転速度の０．５〜１．５倍で回転さ
せ、かつ研磨剤は、Ｐｈが１１以上の研磨液に平均粒径
７０〜９０ｎｍのシリカ粒子を分散させたものを使用
し、この研磨剤は保護膜のＳｉＯ２とウェーハ基材のＳ
ｉに対する研磨比率が１：１００以上になるような特性
を有する。[0024] In this secondary polishing step, contacting plate on one surface of the silicon wafer W 2, for example, the upper surface plate 9 is rotated at 0.5 to 1.5 times the revolution rate of the silicon wafer, and a polishing agent Is used in which silica particles having an average particle size of 70 to 90 nm are dispersed in a polishing liquid having a Ph of 11 or more, and this polishing agent is composed of SiO 2 for the protective film and S for the wafer substrate.
It has such characteristics that the polishing ratio to i becomes 1: 100 or more.
【００２５】上定盤９をシリコンウェーハの公転速度の
０．５〜１．５倍で回転させ、かつ研磨剤として、Ｐｈ
が１１以上の研磨液に平均粒径７０〜９０ｎｍのシリカ
粒子を分散させたものを使用するのは、研磨剤をＳｉＯ
２とＳｉに対する研磨比率で１：１００以上にし、Ｓｉ
Ｏ２膜をほとんど研磨せず、Ｓｉを十分研磨して研磨面
を平坦にするためである。The upper platen 9 is rotated at a speed of 0.5 to 1.5 times the revolution speed of the silicon wafer, and Ph is used as an abrasive.
The use of a polishing liquid in which silica particles having an average particle diameter of 70 to 90 nm are dispersed in a polishing liquid having an
The polishing ratio to 2 and Si is 1: 100 or more, and Si
This is because the O 2 film is hardly polished and the Si is sufficiently polished to make the polished surface flat.
【００２６】上定盤９の回転がシリコンウェーハの公転
速度の０．５より小さいと下定盤７の回転とのバランス
がとれないためＳｉ研磨面を平坦に研磨することができ
ず、また、１．５倍を超えるとＳｉＯ２の研磨量が増大
してＳｉＯ２を所定の厚さに維持できなくなる。さら
に、研磨剤のＳｉＯ２とＳｉに対する研磨比率が１：１
００より小さいと、Ｓｉを所定量研磨するとＳｉＯ２が
必要以上に研磨されて、所定厚さのＳｉＯ２膜が得られ
なくなる。If the rotation of the upper platen 9 is smaller than the revolving speed of the silicon wafer 0.5, the balance with the rotation of the lower platen 7 cannot be obtained, so that the Si polishing surface cannot be polished flatly. beyond fold .5 polishing amount of SiO 2 is increased can not be maintained SiO 2 to a predetermined thickness by. Further, the polishing ratio of the polishing agent to SiO 2 and Si is 1: 1.
If the value is smaller than 00, when a predetermined amount of Si is polished, SiO 2 is polished more than necessary, and a SiO 2 film having a predetermined thickness cannot be obtained.
【００２７】上記２次研磨工程の研磨では、前保護膜形
成工程で発じた傷等を除去するために通常の研磨よりも
大きな研磨代を取る必要があるが、２次研磨工程は両面
研磨装置１を用いて行うので、シリコンウェーハの両面
に柔軟性のある研磨布６、８を当接、押圧するようにな
っており、剛性を有する研磨基準面を持たないことか
ら、シリコンウェーハＷ２の研磨面の平坦度を良好に研
磨することができ、また、上定盤９をシリコンウェーハ
の公転速度の０．５〜１．５倍で回転させ、研磨剤をＳ
ｉＯ２とＳｉに対する研磨比率で１：１００以上にして
いるので、ＳｉＯ ２膜をほとんど研磨せず、平坦度のＳ
ｉ研磨面を得ることができる。In the above polishing in the secondary polishing step, the pre-protection film
Than normal polishing to remove scratches etc. generated during the forming process
It is necessary to take a large polishing allowance, but the secondary polishing process is on both sides
Since the polishing is performed using the polishing apparatus 1, both sides of the silicon wafer are
The flexible polishing cloths 6 and 8 come into contact with and press against each other.
That it does not have a rigid polishing reference surface
Et al., Silicon wafer W2Polished surface with good flatness
Can be polished, and the upper platen 9 can be
Is rotated at 0.5 to 1.5 times the revolving speed of
iO2To a polishing ratio of 1: 100 or more to Si
Because it is SiO 2The film is hardly polished and has a flatness of S
An i-polished surface can be obtained.
【００２８】要するに、２次研磨工程では片面研磨装置
に比べて高平坦度が得られる両面研磨装置１を用いて保
護膜付シリコンウェーハの両面研磨を行うが、シリコン
ウェーハに当接する定盤の回転数と、研磨剤の特性を規
制して保護膜の研磨量を減じ、実質的に片面研磨と同様
の研磨を行ない、高平坦度の保護膜付シリコンウェーハ
を得るものである。また、両面研磨装置１を用いた研磨
は、研磨代が小さくても十分な平坦度が得られるので、
研磨量、研磨時間を減少させることができ、コスト削減
に寄与できる。In short, in the secondary polishing step, the double-side polishing apparatus 1 which can obtain higher flatness than the single-side polishing apparatus is used to perform double-side polishing of the silicon wafer with the protective film. The number and characteristics of the polishing agent are regulated to reduce the amount of polishing of the protective film, and substantially the same polishing as that of single-side polishing is performed to obtain a silicon wafer with a protective film having a high flatness. In addition, in the polishing using the double-side polishing apparatus 1, a sufficient flatness can be obtained even if the polishing allowance is small.
The polishing amount and polishing time can be reduced, which can contribute to cost reduction.
【００２９】３次研磨工程では、図３に示すような片面
研磨装置１１を用い、図３および図１（ａ）に示すよう
に、ワックスを用いてシリコンウェーハＷ３を片面研磨
装置１１のプレート１２に貼付け、研磨布１３が貼付さ
れた定盤１４を回転させるとともに、スラリを研磨布１
３に供給し、シリコンウェーハＷ３が貼付されたプレー
ト１２を回転させながら降下し、スラリが供給されて湿
潤した研磨布１３に所定荷重で押付けエピ層形成面ｅを
研磨し、シリコンウェーハＷ４を得る。[0029] 3. This polishing step, using a single-side polishing apparatus 11 as shown in FIG. 3, as shown in FIG. 3 and FIG. 1 (a), the plate of single-side polishing apparatus 11 of the silicon wafer W 3 using wax 12 and rotating the platen 14 on which the polishing cloth 13 is adhered, and slurries the polishing cloth 1
Supplied to 3, the plate 12 is a silicon wafer W 3 affixed lowered while rotating to polish the epitaxial layer formed surface e pressing a predetermined load to the slurry is supplied polishing cloth 13 wet, the silicon wafer W 4 Get.
【００３０】前２次研磨工程を経た保護膜付シリコンウ
ェーハは十分な平坦度が得られるので、３次研磨工程に
おいは、研磨量、研磨時間を減少させることができ、コ
スト削減に寄与できる。Since the silicon wafer with the protective film that has undergone the pre-secondary polishing step can obtain a sufficient flatness, the amount of polishing and the polishing time can be reduced in the third polishing step, which can contribute to cost reduction.
【００３１】仕上げ研磨では、３次研磨で得られたシリ
コンウェーハＷ４を研磨条件および研磨代を変えて研磨
し、シリコンウェーハＷを得る。上述のような工程を経
て保護膜付シリコンウェーハＷは次工程に送られる。[0031] In the final polishing, the silicon wafer W 4 obtained in 3 primary polishing and polishing by changing the polishing conditions and polishing fee, obtain a silicon wafer W. The silicon wafer W with the protective film is sent to the next step through the above steps.
【００３２】[0032]
【実施例】本発明に係わる保護膜付シリコンウェーハの
研磨方法によりＳｉＯ２膜付シリコンウェーハを用いて
両面研磨を行ったときの、エピ層形成面（基材Ｓｉ面）
の研磨量とＴＴＶ劣化量を測定した。結果を図４に示
す。なお、片面研磨による従来例の結果を図５に示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Epilayer-formed surface (substrate Si surface) when double-side polishing is performed using a silicon wafer with a SiO 2 film by the method for polishing a silicon wafer with a protective film according to the present invention.
And the amount of TTV deterioration were measured. FIG. 4 shows the results. FIG. 5 shows the result of the conventional example by single-side polishing.
【００３３】・図４に示すように、実施例は、研磨量を
増大させてもＴＴＶ劣化量は小さく、研磨量を増大させ
てもエピ層形成面の平坦度は維持される。As shown in FIG. 4, in the embodiment, the TTV deterioration amount is small even if the polishing amount is increased, and the flatness of the epilayer-formed surface is maintained even if the polishing amount is increased.
【００３４】・これに対して従来例は、研磨量を増大さ
せるとＴＴＶ劣化量は著しく増大し、研磨量を増大させ
るとエピ層形成面の平坦度は保てなくなる。On the other hand, in the conventional example, when the polishing amount is increased, the TTV deterioration amount is significantly increased, and when the polishing amount is increased, the flatness of the epilayer-formed surface cannot be maintained.
【００３５】[0035]
【発明の効果】本発明に係わる保護膜付半導体基板の研
磨方法によれば、一表面に形成された保護膜を損傷する
ことなく、他表面が高平坦度の保護膜付半導体基板が得
られる保護膜付半導体基板の研磨方法を提供することが
できる。According to the method for polishing a semiconductor substrate with a protective film according to the present invention, a semiconductor substrate with a protective film having a high flatness on the other surface can be obtained without damaging the protective film formed on one surface. A method for polishing a semiconductor substrate with a protective film can be provided.
【００３６】即ち、両面研磨方法を用い保護膜面に当接
する定盤を半導体基板の公転速度の０．５〜１．５倍で
回転させ、かつ研磨剤としてＰｈが１１以上の研磨液に
平均粒径７０〜９０ｎｍのシリカ粒子を分散させたもの
を使用し、研磨剤の保護膜と半導体基板の基材に対する
研磨比率を１：１００以上にしたので、高平坦度が得ら
れる両面研磨の長所を生かし、半導体基板に当接する定
盤の回転数と、研磨剤の特性を規制して保護膜の研磨量
を減じ、実質的に片面研磨と同様の研磨を行うので、高
平坦度の保護膜付半導体基板が得られ、また、研磨代が
小さくても十分な平坦度が得られるので、研磨量、研磨
時間を減少させることができ、コスト削減に寄与でき
る。That is, the surface plate contacting the protective film surface is rotated at a speed of 0.5 to 1.5 times the revolution speed of the semiconductor substrate using a double-side polishing method. Since silica particles having a particle size of 70 to 90 nm are dispersed and the polishing ratio of the polishing agent to the protective film and the base material of the semiconductor substrate is set to 1: 100 or more, the advantage of double-side polishing to obtain high flatness is obtained. Taking advantage of this, the number of rotations of the surface plate in contact with the semiconductor substrate and the characteristics of the abrasive are regulated to reduce the amount of polishing of the protective film, and the polishing is performed substantially in the same manner as single-side polishing, so that the protective film with high flatness Since a semiconductor substrate with a substrate can be obtained and sufficient flatness can be obtained even with a small polishing allowance, the amount of polishing and the polishing time can be reduced, which can contribute to cost reduction.
【００３７】また、半導体基板の基材はＳｉで最適であ
り、確実に高平坦度の保護膜付半導体基板が得られ、ま
た、研磨代が小さくても十分な平坦度が得られるので、
研磨量、研磨時間を減少させることができ、コスト削減
に寄与できる。The substrate of the semiconductor substrate is optimally made of Si, so that a semiconductor substrate with a protective film having a high flatness can be reliably obtained, and a sufficient flatness can be obtained even with a small polishing allowance.
The polishing amount and polishing time can be reduced, which can contribute to cost reduction.
【００３８】また、半導体基板の基材がＳｉであり、保
護膜がＳｉＯ２で最適であり、より確実に高平坦度の保
護膜付半導体基板が得られ、また、研磨代が小さくても
十分な平坦度が得られるので、研磨量、研磨時間を減少
させることができ、コスト削減に寄与できる。Further, the base material of the semiconductor substrate is Si, and the protective film is optimally made of SiO 2 , so that a semiconductor substrate with a protective film having a high flatness can be obtained more reliably. Since a high degree of flatness is obtained, the polishing amount and polishing time can be reduced, which can contribute to cost reduction.
【図１】本発明に係わる保護膜付半導体基板の研磨方法
と従来例を対比した研磨工程図。FIG. 1 is a polishing process diagram comparing a method of polishing a semiconductor substrate with a protective film according to the present invention with a conventional example.
【図２】一般に用いられている両面研磨装置の説明図。FIG. 2 is an explanatory view of a commonly used double-side polishing apparatus.
【図３】一般に用いられている片面研磨装置の説明図。FIG. 3 is an explanatory diagram of a generally used single-side polishing apparatus.
【図４】本発明に係わる保護膜付半導体基板の研磨方法
を用いた研磨量とＴＴＶ劣化量の測定結果を示す図。FIG. 4 is a view showing measurement results of a polishing amount and a TTV deterioration amount using the method for polishing a semiconductor substrate with a protective film according to the present invention.
【図５】従来の保護膜付半導体基板の研磨方法を用いた
研磨量とＴＴＶ劣化量の測定結果を示す図。FIG. 5 is a diagram showing measurement results of a polishing amount and a TTV deterioration amount using a conventional polishing method for a semiconductor substrate with a protective film.
１ 両面研磨装置 ２ キャリア ３ ギア ４ インナギア ５ サンギア ６ 研磨布 ７ 下定盤 ８ 研磨布 ９ 上定盤 １０ 常圧化学気相成長（ＣＶＤ）炉 １１ 片面研磨装置 １２ プレート １３ 研磨布 １４ 定盤 Ｗ 半導体基板 DESCRIPTION OF SYMBOLS 1 Double-side polishing apparatus 2 Carrier 3 Gear 4 Inner gear 5 Sun gear 6 Polishing cloth 7 Lower surface plate 8 Polishing cloth 9 Upper surface plate 10 Atmospheric pressure chemical vapor deposition (CVD) furnace 11 Single-side polishing device 12 Plate 13 Polishing cloth 14 Surface plate W Semiconductor substrate
Claims (3)
れた上定盤および下定盤間で半導体基板を押圧、公転さ
せて、半導体基板の両表面を研磨する半導体基板の両面
研磨方法において、一表面に保護膜が形成された半導体
基板を上定盤および下定盤間に配置し、前記一表面に当
接する定盤を前記半導体基板の公転速度の０．５〜１．
５倍で回転させ、かつ研磨剤としてＰｈが１１以上の研
磨液に平均粒径７０〜９０ｎｍのシリカ粒子を分散させ
たものを使用し、前記保護膜と前記半導体基板の基材に
対する研磨比率を１：１００以上にすることを特徴とす
る保護膜付半導体基板の研磨方法。1. A double-sided polishing method for a semiconductor substrate, in which a semiconductor substrate is pressed and revolved between an upper surface plate and a lower surface plate to which a polishing cloth is attached while supplying an abrasive, thereby polishing both surfaces of the semiconductor substrate. A semiconductor substrate having a protective film formed on one surface is disposed between an upper surface plate and a lower surface plate, and the surface plate contacting the one surface is rotated at a rotation speed of 0.5 to 1.
Rotate at 5 times, and use a polishing liquid in which silica particles having an average particle diameter of 70 to 90 nm are dispersed in a polishing liquid having a Ph of 11 or more, and adjust the polishing ratio of the protective film and the semiconductor substrate to the base material. A method for polishing a semiconductor substrate with a protective film, wherein the polishing ratio is 1: 100 or more.
を特徴とする請求項１に記載の保護膜付半導体基板の研
磨方法。2. The method for polishing a semiconductor substrate with a protective film according to claim 1, wherein the base material of the semiconductor substrate is Si.
とする請求項２に記載の保護膜付半導体基板の研磨方
法。3. The method for polishing a semiconductor substrate with a protective film according to claim 2 , wherein the protective film is SiO 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29242699A JP2001113459A (en) | 1999-10-14 | 1999-10-14 | Polishing method of semiconductor substrate with protective film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29242699A JP2001113459A (en) | 1999-10-14 | 1999-10-14 | Polishing method of semiconductor substrate with protective film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001113459A true JP2001113459A (en) | 2001-04-24 |
Family
ID=17781646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29242699A Pending JP2001113459A (en) | 1999-10-14 | 1999-10-14 | Polishing method of semiconductor substrate with protective film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001113459A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002035593A1 (en) * | 2000-10-26 | 2002-05-02 | Shin-Etsu Handotai Co.,Ltd. | Wafer manufacturing method, polishing apparatus, and wafer |
| WO2012120785A1 (en) * | 2011-03-07 | 2012-09-13 | 信越半導体株式会社 | Process for producing silicon wafer |
| CN108098570A (en) * | 2017-12-15 | 2018-06-01 | 苏州新美光纳米科技有限公司 | Polishing assembly and its polishing process method |
-
1999
- 1999-10-14 JP JP29242699A patent/JP2001113459A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002035593A1 (en) * | 2000-10-26 | 2002-05-02 | Shin-Etsu Handotai Co.,Ltd. | Wafer manufacturing method, polishing apparatus, and wafer |
| WO2012120785A1 (en) * | 2011-03-07 | 2012-09-13 | 信越半導体株式会社 | Process for producing silicon wafer |
| JP2012186338A (en) * | 2011-03-07 | 2012-09-27 | Shin Etsu Handotai Co Ltd | Method of manufacturing silicon wafer |
| US9425056B2 (en) | 2011-03-07 | 2016-08-23 | Shin-Etsu Handotai Co., Ltd. | Method for producing silicon wafer |
| CN108098570A (en) * | 2017-12-15 | 2018-06-01 | 苏州新美光纳米科技有限公司 | Polishing assembly and its polishing process method |
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