JP3094312B2 - Susceptor - Google Patents
SusceptorInfo
- Publication number
- JP3094312B2 JP3094312B2 JP10849392A JP10849392A JP3094312B2 JP 3094312 B2 JP3094312 B2 JP 3094312B2 JP 10849392 A JP10849392 A JP 10849392A JP 10849392 A JP10849392 A JP 10849392A JP 3094312 B2 JP3094312 B2 JP 3094312B2
- Authority
- JP
- Japan
- Prior art keywords
- susceptor
- sic film
- polished
- wafer
- sic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、シリコンウェーハ等の
半導体ウェーハにＣＶＤ（化学蒸着）法等によりエピタ
キシャル成長を施す際等に、半導体ウェーハを載置する
サセプターに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a susceptor for mounting a semiconductor wafer such as a silicon wafer when the semiconductor wafer is epitaxially grown by a CVD (chemical vapor deposition) method or the like.
【０００２】[0002]
【従来の技術】従来、この種のサセプターは、黒鉛等の
カーボンを基材とするサセプター本体に半導体ウェーハ
を収容する円形の複数のウェーハ収容凹部を設け、かつ
サセプター本体の吸蔵ガスがエピタキシャル処理中に放
出されて半導体ウェーハに汚染が生ずるのを防止するた
め、サセプター本体をＣＶＤ法によるＳｉＣ膜でコーテ
ィグし、かつ所要個所に研磨を施して構成されている。2. Description of the Related Art Conventionally, this type of susceptor has been provided with a plurality of circular wafer accommodating recesses for accommodating a semiconductor wafer in a susceptor body made of carbon such as graphite, and the occluded gas of the susceptor body is subjected to an epitaxial process. The susceptor body is coated with a SiC film formed by a CVD method and polished at required locations to prevent the semiconductor wafer from being contaminated by being released into the semiconductor wafer.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
サセプターでは、単に１層のＣＶＤコートによって所望
の厚さのＳｉＣ膜を得ているため、部分的にＳｉＣ結晶
粒の異常成長が起こり、この上面を研磨するとチッピン
グ等により、ＳｉＣ膜に凹部やマイクロクラック等の欠
陥が生ずる。そして、このサセプターを半導体ウェーハ
のエピタキシャル処理や熱酸化処理等に用いた場合、上
記凹部あるいはマイクロクラック部分が半導体ウェーハ
表面と接触すると、ウェーハ面において部分的な熱膨張
差が生じ、半導体ウェーハにスリップが発生するという
問題があった。However, in the conventional susceptor, since a SiC film having a desired thickness is obtained simply by one-layer CVD coating, abnormal growth of SiC crystal grains occurs partially. When polishing is performed, defects such as concave portions and micro cracks are generated in the SiC film due to chipping or the like. When the susceptor is used for an epitaxial treatment or a thermal oxidation treatment of a semiconductor wafer, when the concave portion or the micro crack portion comes into contact with the semiconductor wafer surface, a partial difference in thermal expansion occurs on the wafer surface, and the semiconductor wafer slips. There was a problem that occurs.
【０００４】又、平坦度を高めるためにＳｉＣ膜の表面
研磨を繰り返して行うと、チッピングにより、サセプタ
ー本体が部分的に露出した状態が生ずることもある。そ
して、このサセプターを半導体ウェーハの表面酸化処理
に用いた場合、カーボンよりなるサセプター本体の酸化
消耗が起きたり、あるいはサセプター本体からの放出ガ
スによって半導体ウェーハの汚染が生ずるという問題が
あった。そこで、本発明は、半導体ウェーハに欠陥を生
じさせることなく、かつ長寿命のサセプターの提供を目
的とする。If the surface of the SiC film is repeatedly polished to increase the flatness, the susceptor body may be partially exposed due to chipping. When this susceptor is used for the surface oxidation treatment of a semiconductor wafer, there has been a problem that the susceptor body made of carbon is oxidized and consumed, or the gas discharged from the susceptor body causes contamination of the semiconductor wafer. Therefore, an object of the present invention is to provide a susceptor having a long life without causing a defect in a semiconductor wafer.
【０００５】[0005]
【課題を解決するための手段】前記課題を解決するた
め、本発明のサセプターは、カーボンを基材とするサセ
プター本体の少なくともウェーハ収容凹部の表面に、Ｃ
ＶＤ法によりコーティングされ、かつ表面を研磨された
所要厚さの研磨ＳｉＣ膜が２層以上積層されているもの
である。In order to solve the above-mentioned problems, a susceptor according to the present invention comprises a carbon-based susceptor body having at least a surface of a concave portion for accommodating a wafer.
Two or more polished SiC films of a required thickness, which are coated by the VD method and whose surface is polished, are laminated.
【０００６】[0006]
【作用】上記手段においては、各層のＳｉＣ膜の結晶の
成長や異方性を抑制され、ＳｉＣ膜全体の厚さが厚くな
っても凹部やマイクロクラック等の欠陥が少なくなる。
各層のＳｉＣ膜の厚さは、３０〜３００μｍが好まし
い。３０μｍ未満であると、平坦度を高めの研磨時に下
層表面が露出したりする一方、３００μｍを超えると、
結晶の成長や異方性を抑制できず、研磨後に凹部あるい
はマイクロクラック等の欠陥の発生率が高くなる。According to the above means, the growth and anisotropy of the crystal of the SiC film of each layer are suppressed, and even if the thickness of the entire SiC film is increased, defects such as concave portions and micro cracks are reduced.
The thickness of the SiC film of each layer is preferably 30 to 300 μm. When it is less than 30 μm, the lower layer surface is exposed at the time of polishing to increase the flatness, while when it exceeds 300 μm,
Crystal growth and anisotropy cannot be suppressed, and the incidence of defects such as recesses or microcracks after polishing increases.
【０００７】各層の表面粗さＲａは、０．０１〜７．０
μｍが好ましい。０．０１μｍ未満であると、加工が困
難となる一方、７．０μｍを超えると、スリップの発生
率が大きくなる。より好ましくは、Ｒａ＝０．０１〜
１．０μｍである。The surface roughness Ra of each layer is 0.01 to 7.0.
μm is preferred. If it is less than 0.01 μm, processing becomes difficult, while if it exceeds 7.0 μm, the rate of occurrence of slip increases. More preferably, Ra = 0.01 to
1.0 μm.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図１、図２は本発明の一実施例のサセプターの要部
の断面図、そのウェーハ収容凹部の底部の拡大断面図で
ある。このサセプターは、黒鉛又は等方性カーボンから
なるサセプター本体１の上面に、半導体ウェーハ２を収
容する複数の円形のウェーハ収容凹部３を、座ぐり加工
によって底部が凹球面状を呈するように設ける一方、全
表面にＣＶＤ法により厚さ３０〜３００μｍのＳｉＣ膜
４をコーティングし、かつウェーハ収容凹部３のＳｉＣ
膜４の表面を表面粗さＲａが０．０１〜７．０μｍとな
るように研磨して研磨ＳｉＣ膜５とし、更に、ＳｉＣ膜
４及び研磨ＳｉＣ膜５の表面に、同様にＣＶＤ法により
厚さ３０〜３００μｍのＳｉＣ膜６をコーティングし、
かつウェーハ収容凹部３のＳｉＣ膜６の表面を表面粗さ
Ｒａが０．０１〜７．０μｍとなるように研磨して研磨
ＳｉＣ膜７とした、いわばサセプター本体１のウェーハ
収容凹部３を除く表面にＳｉＣ膜４，６を２層積層し、
かつウェーハ収容凹部３の表面に研磨ＳｉＣ膜５，７を
２層積層した構造とされている。Next, the present invention will be described with reference to the drawings. 1 and 2 are a cross-sectional view of a main part of a susceptor according to an embodiment of the present invention, and an enlarged cross-sectional view of a bottom portion of a wafer accommodating recess. This susceptor is provided with a plurality of circular wafer housing recesses 3 for housing semiconductor wafers 2 on a top surface of a susceptor body 1 made of graphite or isotropic carbon so that the bottom has a concave spherical shape by spot facing. The entire surface is coated with a 30 to 300 μm thick SiC film 4 by CVD, and the SiC
The surface of the film 4 is polished so as to have a surface roughness Ra of 0.01 to 7.0 μm to form a polished SiC film 5, and the surface of the SiC film 4 and the polished SiC film 5 is similarly thickened by a CVD method. A SiC film 6 having a thickness of 30 to 300 μm,
In addition, the surface of the SiC film 6 in the wafer accommodating recess 3 is polished so as to have a surface roughness Ra of 0.01 to 7.0 μm to obtain a polished SiC film 7, that is, the surface of the susceptor body 1 excluding the wafer accommodating recess 3. And two layers of SiC films 4 and 6
In addition, it has a structure in which two layers of polished SiC films 5 and 7 are laminated on the surface of the wafer accommodating recess 3.
【０００９】ここで、ウェーハ収容凹部３の中間層とな
る研磨ＳｉＣ膜５の表面粗さＲａは、０．１〜５．０μ
ｍが好ましい。０．１μｍ未満であると、加工費がかか
ってコスト的に採算がとれなくなる一方、５．０μｍを
超えると、表面の凹凸がその上に積層されるＳｉＣ膜６
の結晶形態に影響を及ぼし、結晶の成長や異方性を抑制
できず、上層の研磨後に結晶粒界でのチッピング等によ
る凹部あるいはマイクロクラック等の欠陥の発生率が高
くなる。Here, the surface roughness Ra of the polished SiC film 5 as an intermediate layer of the wafer accommodating concave portion 3 is 0.1 to 5.0 μm.
m is preferred. If the thickness is less than 0.1 μm, processing costs will be incurred and the cost will become unprofitable, while if it exceeds 5.0 μm, unevenness on the surface will cause the SiC film 6
The crystal growth and anisotropy cannot be suppressed, and the occurrence rate of defects such as recesses or microcracks due to chipping at crystal grain boundaries after polishing the upper layer increases.
【００１０】上記構成のサセプターの製造に際しては、
先ず、黒鉛材を所要の寸法形状に加工して複数のサセプ
ター本体とし、これらを１２５０℃の温度下でＨＣｌガ
スを用いて洗浄処理した後、ＣＶＤ法により処理時間を
変えて種々の厚さのＳｉＣ膜を全面にコーティングし
た。ＣＶＤ条件は次の通りである。 原料ガス：ＳｉＣｌ4 ０．２４ ｌ／ｍｉｎ ＣＨ4 ０．２４ ｌ／ｍｉｎ Ｈ2 １０．０ ｌ／ｍｉｎ 温度：１５００℃In manufacturing the susceptor having the above structure,
First, a graphite material is processed into a required size and shape to form a plurality of susceptor bodies, which are subjected to a cleaning treatment using HCl gas at a temperature of 1250 ° C. An SiC film was coated on the entire surface. The CVD conditions are as follows. Source gas: SiCl 4 0.24 l / min CH 4 0.24 l / min H 2 10.0 l / min Temperature: 1500 ° C.
【００１１】次いで、各サセプター本体のウェーハ収容
凹部の表面のＳｉＣ膜に、ダイヤモンドペーパー及びダ
イヤモンドペーストによる研磨を行った。表１にこの時
の研磨ＳｉＣ膜の厚さと、その表面で観察された凹部あ
るいはマイクロクラック等の欠陥数との関係を示した。Next, the SiC film on the surface of the concave portion for accommodating the wafer of each susceptor body was polished with diamond paper and diamond paste. Table 1 shows the relationship between the thickness of the polished SiC film at this time and the number of defects such as recesses or microcracks observed on the surface.
【００１２】[0012]
【表１】 [Table 1]
【００１３】従って、試料Ｎｏ．２〜４の厚さのもの
が、欠陥数の点で優れていることがわかった。次に、厚
さ４５μｍのＳｉＣ膜を上述したＣＶＤ条件でコーティ
ングし、かつ上述した研磨方法でウェーハ収容凹部のＳ
ｉＣ膜を種々の表面粗さ研磨した後、サセプター本体の
全表面にＣＶＤ法により４５μｍの２層目のＳｉＣ膜を
コーティングした。Therefore, the sample No. It was found that those having a thickness of 2 to 4 were excellent in terms of the number of defects. Next, a 45 μm-thick SiC film is coated under the above-described CVD conditions, and the S
After polishing the iC film to various surface roughnesses, the entire surface of the susceptor body was coated with a second SiC film of 45 μm by CVD.
【００１４】ＣＶＤ条件は、次の通りである。 原料ガス：ＭＴＣＳ（トリメチルクロロシラン） ０．２４ ｌ／ｍｉｎ Ｈ2 ０．７０ ｌ／ｍｉｎ 温度：１３００℃ 次いで、各サセプター本体のウェーハ収容凹部の表面の
２層目のＳｉＣ膜を上述した研磨方法で研磨し、表面粗
さＲａが、１．０μｍの２層目の研磨ＳｉＣ膜とした
後、１２５０℃の温度下でＨＣｌガスを用いて洗浄処理
し、サセプターを得た。各サセプターの研磨ＳｉＣ膜の
表面のスリップ発生率を測定したところ、表２の結果を
得た。The CVD conditions are as follows. Source gas: MTCS (trimethylchlorosilane) 0.24 l / min H 2 0.70 l / min Temperature: 1300 ° C. Then, the second-layer SiC film on the surface of the wafer accommodating concave portion of each susceptor body is subjected to the above-mentioned polishing method. It was polished to form a second-layer polished SiC film having a surface roughness Ra of 1.0 μm, and then was washed at a temperature of 1250 ° C. with HCl gas to obtain a susceptor. When the rate of occurrence of slip on the surface of the polished SiC film of each susceptor was measured, the results shown in Table 2 were obtained.
【００１５】[0015]
【表２】 [Table 2]
【００１６】従って、界面となる１層目の研磨ＳｉＣ膜
の表面粗さＲａは、０．１〜５．０μｍが好ましく、よ
り好ましくは０．１〜１．０μｍであることがわかる。
一方、サセプター本体にコーティングするＳｉＣ膜を１
層、２層及び３層とすると共に、それぞれの厚さを９０
μｍ、４５μｍ及び３０μｍとし、かつウェーハ収容凹
部の表面の表面粗さＲａがいずれも１．０μｍとなるよ
うに研磨したサセプターをエピタキシャル装置内に納置
し、洗浄ガス（Ｈ2 ：１０ ｌ／ｍｉｎ＋ＨＣｌ：０．
５ ｌ／ｍｉｎ）を流しながら冷熱サイクル（室温→昇
温（約２０ｍｉｎ）→１２００℃（１０ｍｉｎ保持）→
降温（約６０ｍｉｎ）→室温）を加えたところ、マイク
ロクラック発生までの回数は、表３に示すようになっ
た。Accordingly, it is understood that the surface roughness Ra of the first-layer polished SiC film serving as the interface is preferably 0.1 to 5.0 μm, and more preferably 0.1 to 1.0 μm.
On the other hand, the SiC film coated on the susceptor body
Layers, two layers and three layers, each having a thickness of 90
A susceptor polished so as to have a surface roughness Ra of 1.0 μm, a susceptor having a surface roughness Ra of 1.0 μm, a cleaning gas (H 2 : 10 l / min + HCl) : 0.
Cooling / heating cycle (room temperature → heating (about 20 min) → 1200 ° C. (holding 10 min) while flowing 5 l / min) →
When the temperature was lowered (about 60 min) → room temperature, the number of times until the occurrence of microcracks was as shown in Table 3.
【００１７】[0017]
【表３】 [Table 3]
【００１８】従って、ＳｉＣ膜を２層以上積層すると共
に、各層の厚さを３０〜３００μｍとし、かつウェーハ
収容凹部の表面のＳｉＣ膜の表面粗さＲａが０．０１〜
７．０μｍとなるように研磨することによって、サセプ
ターの寿命を従来のものの２倍以上にできることがわか
る。なお、上述した実施例においては、１層目と２層目
のＳｉＣ膜をＣＶＤコーティングする際の原料ガス等を
異ならせているが、いずれか一方の原料ガスのみを用い
てＣＶＤコーティングするようにしてもよい。Therefore, two or more SiC films are stacked, the thickness of each layer is set to 30 to 300 μm, and the surface roughness Ra of the SiC film on the surface of the concave portion for accommodating the wafer is 0.01 to 300 μm.
It can be seen that the life of the susceptor can be more than doubled by polishing to 7.0 μm. In the above-described embodiment, the source gas and the like when the first layer and the second layer of the SiC film are subjected to the CVD coating are different, but the CVD coating is performed using only one of the source gases. You may.
【００１９】又、ウェーハ収容凹部の表面のＳｉＣ膜の
研磨は、全面に行う場合に限らず、実質的に半導体ウェ
ーハと接触する最外層の底面の外周部のみを、ウェーハ
収容凹部径の１０〜２０％程度の幅で研磨するようにし
てもよい。このようにすることにより、加工時間及び経
費の軽減を図ることができる。The polishing of the SiC film on the surface of the concave portion of the wafer accommodating portion is not limited to the case where the polishing is performed on the entire surface. Polishing may be performed with a width of about 20%. By doing so, processing time and cost can be reduced.
【００２０】[0020]
【発明の効果】以上説明したように、本発明のサセプタ
ーによれば、各層のＳｉＣ膜の結晶の成長や異方性を抑
制され、ＳｉＣ膜全体の厚さが厚くなっても凹部やマイ
クロクラック等の欠陥が少なくなるので、半導体ウェー
ハに欠陥を生じさせることが少なくなり、かつサセプタ
ーを長寿命とすることができる効果がある。As described above, according to the susceptor of the present invention, the growth and anisotropy of the crystal of the SiC film of each layer are suppressed, and even if the entire thickness of the SiC film becomes thick, the concave portions and the micro cracks are not formed. Since defects such as defects are reduced, defects are less likely to occur in the semiconductor wafer, and the susceptor has a long life.
【図１】本発明の一実施例のサセプター要部の断面図で
ある。FIG. 1 is a sectional view of a main part of a susceptor according to an embodiment of the present invention.
【図２】本発明の一実施例のサセプターのウェーハ収容
凹部の底部の断面図である。FIG. 2 is a cross-sectional view of a bottom portion of a wafer accommodating concave portion of the susceptor according to one embodiment of the present invention.
１ サセプター本体 ２ 半導体ウェーハ ３ ウェーハ収容凹部 ４ ＳｉＣ膜 ５ 研磨ＳｉＣ膜 ６ ＳｉＣ膜 ７ 研磨ＳｉＣ膜 REFERENCE SIGNS LIST 1 susceptor main body 2 semiconductor wafer 3 wafer receiving recess 4 SiC film 5 polished SiC film 6 SiC film 7 polished SiC film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 稲葉 毅 山形県西置賜郡小国町大字小国町378番 地 東芝セラミックス株式会社 小国製 造所内 (72)発明者 佐々木 泰実 山形県西置賜郡小国町大字小国町378番 地 東芝セラミックス株式会社 小国製 造所内 (56)参考文献 特開 昭58−125608（ＪＰ，Ａ) 特開 平１−145400（ＪＰ，Ａ) 特開 平３−257089（ＪＰ，Ａ) 特開 平２−68922（ＪＰ，Ａ) 特開 平５−47670（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/205 C23C 16/32 H01L 21/68 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Inaba 378, Oguni-machi, Oguni-machi, Oguni-machi, Nishiokitama-gun, Yamagata Prefecture Inside the Oguni Plant, Toshiba Ceramics Co., Ltd. 378, Toshiba Ceramics Co., Ltd. Oguni Works (56) References JP-A-58-125608 (JP, A) JP-A-1-145400 (JP, A) JP-A-3-257089 (JP, A) JP-A-2-68922 (JP, A) JP-A-5-47670 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/205 C23C 16/32 H01L 21/68
Claims (1)
少なくともウェーハ収容凹部の表面に、ＣＶＤ法により
コーティングされ、かつ表面を研磨された所要厚さの研
磨ＳｉＣ膜が２層以上積層されていることを特徴とする
サセプター。1. A susceptor main body made of carbon as a base material, at least a surface of a concave portion for accommodating a wafer, having at least two layers of a polished SiC film having a required thickness, which is coated by a CVD method and whose surface is polished, is laminated. A susceptor characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10849392A JP3094312B2 (en) | 1992-04-01 | 1992-04-01 | Susceptor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10849392A JP3094312B2 (en) | 1992-04-01 | 1992-04-01 | Susceptor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05283351A JPH05283351A (en) | 1993-10-29 |
| JP3094312B2 true JP3094312B2 (en) | 2000-10-03 |
Family
ID=14486177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10849392A Expired - Fee Related JP3094312B2 (en) | 1992-04-01 | 1992-04-01 | Susceptor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3094312B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3317781B2 (en) * | 1994-06-08 | 2002-08-26 | 東芝セラミックス株式会社 | Method of manufacturing susceptor for heat treatment of semiconductor wafer |
| JPH09219438A (en) * | 1996-02-09 | 1997-08-19 | Tera Tec:Kk | Jig for sample support use |
| JP3887052B2 (en) * | 1996-12-13 | 2007-02-28 | 東洋炭素株式会社 | Vapor growth susceptor |
| JP3565469B2 (en) * | 1997-02-10 | 2004-09-15 | 東芝セラミックス株式会社 | Susceptor for vapor phase growth |
| JP4619036B2 (en) * | 2004-05-10 | 2011-01-26 | イビデン株式会社 | Carbon composite material |
| JP4252944B2 (en) * | 2004-07-29 | 2009-04-08 | 新電元工業株式会社 | Susceptor and chemical vapor deposition method |
| JP2015146416A (en) * | 2014-01-06 | 2015-08-13 | 住友電気工業株式会社 | Silicon carbide substrate support member, member for silicon carbide growth device and silicon carbide epitaxial substrate manufacturing method |
| JP6841359B1 (en) * | 2020-03-09 | 2021-03-10 | 信越半導体株式会社 | Manufacturing method of susceptor for manufacturing silicon epitaxial wafer and manufacturing method of silicon epitaxial wafer |
-
1992
- 1992-04-01 JP JP10849392A patent/JP3094312B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05283351A (en) | 1993-10-29 |
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