JPS62126661A - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS62126661A
JPS62126661A JP60267712A JP26771285A JPS62126661A JP S62126661 A JPS62126661 A JP S62126661A JP 60267712 A JP60267712 A JP 60267712A JP 26771285 A JP26771285 A JP 26771285A JP S62126661 A JPS62126661 A JP S62126661A
Authority
JP
Japan
Prior art keywords
resin
semiconductor pellet
integrated circuit
circuit device
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60267712A
Other languages
English (en)
Inventor
Hiromi Sakata
坂田　博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60267712A priority Critical patent/JPS62126661A/ja
Publication of JPS62126661A publication Critical patent/JPS62126661A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野］ 本発明は複数の能動素子を搭載して成る混成集積回路装
置に関する。
〔従来の技術〕
従来、半導体ペレットを２ヶ以上搭載した混成集積回路
装置は第２図に示すように絶縁性基板１に配線導体２を
形成し半導体ペレッ）４ａ、４ｂを平面的に配置しＡｕ
線５でボンディングし樹脂６でコーティングする構成が
一般的である。
〔発明が解決しようとする問題点〕
近年、混成集積回路装置の小型化の要求は一層強くなっ
て来ており、従って部品の実装密度を高める事が必要と
なっている。
しかし、従来の平面的に半導体ベレットを配置する構造
では小型化に限界があった。
本発明の目的は、半導体ペレットの絶縁性基板上の配置
を改良し、高密度で小型化の達成できる混成集積回路装
置を提供することにある。
〔問題点を解決するだめの手段〕
本発明の混成集積回路装置は、検数の半導体ペレットを
搭載した混成集積回路装置において、配線導体を形成し
た絶縁性基板と、該基板上にマウントされた半導体ペレ
ットと、該半導体ペレットと配線導体をボンディングし
たＡｕｉ線と、前記半導体ペレットをコーティングした
樹脂と、該樹脂上にマウントされた他の半導体ペレット
と、該半導体ペレットと配線導体とをボンディングした
Ａｕｉ線と、全体をコーティングした樹脂とを含んで構
成される。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の一実施例の断面図である。
第１図において、絶縁基板１には配線導体２が形成され
ており、その絶縁基板１上にまず、接着樹脂３ａにより
半導体ペレット４をマウントする。
そして半導体ベレン）４ａの電極と配線導体２をＡｕ＃
１線５ａによりボンディングする。次いでコーティング
樹脂６ａによシ半導体ペレッ）４ａ及びｋｕ細［５ａを
コーティングする。
次に、別の半導体ペレッ）４ｂを先に設置した半導体ペ
レット４ａ上にコーティングしたコーチインク樹脂６ａ
の上に接着樹脂３ｂによりマウントする。次いでＡ−０
ＭＭ５ｂにより先に述べた方法で接続する。その後全体
をコーティング樹脂６ｂによりコーティングすると本実
施例の混成集積回路装置が完成する。
本実施例は、従来の混成集積回路とことなり初舷個の半
導体ペレットは平面的配置のみでなく、樹脂を介して二
段重ねに重ねられた構成をなしており高密度、小型化に
好適な構造を有している。
〔発明の効果〕
以上説明したように本発明によれば半導体ペレットを平
面的配置のみならず樹脂を介して２段重ねて実装する事
により高密度小形の混成集積回路装置を得る事が可能と
なった。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図は従来の混
成集積回路装置の一例の断面図である。 １・・・・・・絶縁基板、２・・・・・・配線導体、３
，３ａ。 ３ｂ・・・・・・接着樹脂、４，４ａ、４ｂ・川・・半
導体ペレット、５，５　ａ、５　ｂ−・−・−ｋｕ　ｍ
線、６，６ａ。 ６ｂ・・・・・・コーティング樹脂。 茅１回 東Ｚｌｌｆｌ

Claims (1)

    【特許請求の範囲】
  1. 複数の半導体ペレットを搭載した混成集積回路装置にお
    いて、配線導体を形成した絶縁性基板と、該基板上にマ
    ウントされた半導体ペレットと、該半導体ペレットと配
    線導体をボンディングしたＡｕ細線と、前記半導体ペレ
    ットをコーティングした樹脂と、該樹脂上にマウントさ
    れた他の半導体ペレットと、該半導体ペレットと配線導
    体とをボンディングしたＡｕ細線と、全体をコーティン
    グした樹脂とを含むことを特徴とする混成集積回路装置
    。
JP60267712A 1985-11-27 1985-11-27 混成集積回路装置 Pending JPS62126661A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60267712A JPS62126661A (ja) 1985-11-27 1985-11-27 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60267712A JPS62126661A (ja) 1985-11-27 1985-11-27 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS62126661A true JPS62126661A (ja) 1987-06-08

Family

ID=17448501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60267712A Pending JPS62126661A (ja) 1985-11-27 1985-11-27 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS62126661A (ja)

Cited By (32)

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US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
JPH0888316A (ja) * 1994-09-16 1996-04-02 Nec Corp ハイブリッドｉｃ及びその製造方法
EP0727819A3 (ja) * 1995-02-15 1996-08-28 Mitsubishi Electric Corp
US5801448A (en) * 1996-05-20 1998-09-01 Micron Technology, Inc. Conductive lines on the back side of wafers and dice for semiconductor interconnects
EP0736903A3 (en) * 1995-04-07 1999-01-27 Nec Corporation Three-dimensional multi-chip module having stacked semiconductor chips and process of fabrication thereof
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6107121A (en) * 1996-06-24 2000-08-22 International Business Machines Corporation Method of making interconnections between a multi-layer chip stack to a printed circuit board in a ceramic package
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
JP2006040983A (ja) * 2004-07-23 2006-02-09 Akita Denshi Systems:Kk 半導体装置の製造方法
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US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
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US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
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US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
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JP2006040983A (ja) * 2004-07-23 2006-02-09 Akita Denshi Systems:Kk 半導体装置の製造方法
WO2006106569A1 (ja) * 2005-03-31 2006-10-12 Spansion Llc 積層型半導体装置及びその製造方法
JPWO2006106569A1 (ja) * 2005-03-31 2008-09-11 スパンション エルエルシー 積層型半導体装置及びその製造方法
JP4896010B2 (ja) * 2005-03-31 2012-03-14 スパンション エルエルシー 積層型半導体装置及びその製造方法
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