JPS6186664A - Apparatus for measuring element - Google Patents
Apparatus for measuring elementInfo
- Publication number
- JPS6186664A JPS6186664A JP20879284A JP20879284A JPS6186664A JP S6186664 A JPS6186664 A JP S6186664A JP 20879284 A JP20879284 A JP 20879284A JP 20879284 A JP20879284 A JP 20879284A JP S6186664 A JPS6186664 A JP S6186664A
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- Prior art keywords
- voltage
- external power
- power source
- pulse
- power supply
- Prior art date
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はダイオード、トランジスタ等の素子の特性を測
定する装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for measuring the characteristics of elements such as diodes and transistors.
素子特性測定装置、特にカーブ・トレーサは、トランジ
スタやダイオード等の基本的な素子の特性を測定するの
に有効な装置である。従来のカーブ・トレーサは第４図
に示す如き構成となっている。即ち、コレクタ電圧供給
回路１０は、外部商用電源からの交流電圧を可変変圧器
により昇圧又は降圧して所望撮幅の正弦波電圧を発生し
、この正弦波電圧を変圧器１２の１次巻線に供給する。Device characteristic measuring devices, particularly curve tracers, are effective devices for measuring the characteristics of basic devices such as transistors and diodes. A conventional curve tracer has a configuration as shown in FIG. That is, the collector voltage supply circuit 10 uses a variable transformer to step up or step down an alternating current voltage from an external commercial power source to generate a sine wave voltage with a desired imaging width. supply to.
この変圧器１２０２次巻線は複数のタップを有し、選択
整流回路１４が測定レンジに応じてこれらタップの１つ
を選択し、選択されたタップからの正弦波電圧を整流す
る。選択整流回路１４からの整流された電圧は、リミッ
タ用抵抗器１６を介して被測定素子としてのトランジス
タ１８のコレクタに供給する。なお、抵抗器１６の値は
測定レンジに応じて切替える。変圧器１２の２次巻線の
下端は、電流検出用抵抗器２０を介して被測定トランジ
スタ１８のエミッタに接続すると共に接地する。The secondary winding of the transformer 120 has a plurality of taps, and the selective rectifier circuit 14 selects one of these taps depending on the measurement range and rectifies the sinusoidal voltage from the selected tap. The rectified voltage from the selective rectifier circuit 14 is supplied to the collector of a transistor 18 as an element to be measured via a limiter resistor 16. Note that the value of the resistor 16 is changed depending on the measurement range. The lower end of the secondary winding of the transformer 12 is connected to the emitter of the transistor to be measured 18 via a current detection resistor 20 and grounded.
壕だ、トランジスタ１８のベースには、ステップ状に変
化するバイアス信号をバイアス供給回路２２から供給す
る。なお、第４図では被測定トランジスタ１８がエミッ
タ接地形式でカーブ・トレーサに接続されているが、ベ
ース接地形式又はコレクタ接地形式でもよい。高入力イ
ンピーダンスの電圧検出回路２４は被測定トランジスタ
１８のコレクタ及びエミッタ間の電圧Ｖ。Ｅを検出し、
適当に分圧した後、増幅器２６を介して表示器である陰
極線管（ＣＲＴ）２８の水平偏向板に供給する。Finally, a stepwise changing bias signal is supplied to the base of the transistor 18 from a bias supply circuit 22. In FIG. 4, the transistor to be measured 18 is connected to the curve tracer in an emitter-grounded manner, but it may be connected in a base-grounded manner or a collector-grounded manner. The high input impedance voltage detection circuit 24 detects the voltage V between the collector and emitter of the transistor under test 18. detect E,
After appropriately dividing the voltage, it is supplied via an amplifier 26 to a horizontal deflection plate of a cathode ray tube (CRT) 28, which is a display.
高入力インピーダンスの電圧検出回路３０は抵抗器２０
０両端の電圧差、即ち被測定トランジスタ１８のコレク
タ電流■。を検出し、増幅器３２を介してＣＲＴ２８の
垂直偏向板に供給する。よって、ＣＲＴ２８にトランジ
スタ１８のＶ。Ｅ ＩＣ特性を表示することができる
。The voltage detection circuit 30 with high input impedance has a resistor 20
0, that is, the collector current of the transistor under test 18 (■). is detected and supplied to the vertical deflection plate of the CRT 28 via the amplifier 32. Therefore, the V of the transistor 18 is applied to the CRT 28. E IC characteristics can be displayed.
〔発明が解決しようとする問題点〕
ところで、第４図に示した従来の素子測定装置（カーブ
・トレーサ）には次のような種々の問題点がある。まず
、コレクタ電圧供給回路１０は外部商用電源を直接利用
しているが、外部商用電源の波形は完全な正弦波ではな
く、即ち、対称な繰返し波形ではなく、種々の歪を含ん
でいる。よって、カーブ・トレーサにおいて、被測定素
子に供給される繰返し電圧波形も完全な正弦波でないた
め、即ち、完全に対称でないため、ＣＲＴ２８に表示さ
れる特性曲線の行き（整流された正弦波電圧の上昇期間
）のトレースと戻り（整流された正弦波電圧の下降期間
）のトレースとが異なり、正確に被測定トランジスタの
特性が測定できない。この現象を便宜的に表示歪と呼ぶ
。また、商用電源電圧の振幅は正確ではなく、ある一定
の幅で変化するため、被測定トランジスタに供給される
繰返し波形電圧の振幅も商用電源に応じて変化し、正確
な特性測定が困難になる。更に、第４図のカーブ・トレ
ーサにデジタル・ストレージ回路を適用した場合、即ち
、電圧検出回路２４及び増幅器２６の間、並びに電圧検
出回路３０及び増幅器３２の間に、Ａ／Ｄ変換器、デジ
タル記憶回路及びＤ／Ａ変換器の組合せを接続した場合
、Ａ／Ｄ変換器のクロック周波数が商用電源周波数と独
立なので、Ａ／Ｄ変換器の出力に電源のリップルの影響
が現われ、測定精度が低下する。仮え、Ａ／Ｄ変換器の
クロック周波数を商用電源周波数に同期させるとしても
、新だに専用の位相制御回路が必要となり、カーブ・ト
レーサが高価となる。[Problems to be Solved by the Invention] By the way, the conventional device measuring device (curve tracer) shown in FIG. 4 has various problems as follows. First, although the collector voltage supply circuit 10 directly uses an external commercial power source, the waveform of the external commercial power source is not a perfect sine wave, that is, it is not a symmetrical repeating waveform, and contains various distortions. Therefore, in a curve tracer, since the repetitive voltage waveform supplied to the device under test is not a perfect sine wave, that is, it is not completely symmetrical, the curve of the characteristic curve displayed on the CRT 28 (rectified sine wave voltage The trace during the rising period) and the trace during the return (falling period of the rectified sine wave voltage) are different, making it impossible to accurately measure the characteristics of the transistor under test. This phenomenon is conveniently called display distortion. In addition, since the amplitude of the commercial power supply voltage is not accurate and changes within a certain range, the amplitude of the repetitive waveform voltage supplied to the transistor under test also changes depending on the commercial power supply, making accurate characteristic measurements difficult. . Furthermore, when a digital storage circuit is applied to the curve tracer of FIG. 4, that is, an A/D converter, a digital When a combination of a storage circuit and a D/A converter is connected, the clock frequency of the A/D converter is independent of the commercial power supply frequency, so the output of the A/D converter is affected by the ripple of the power supply, resulting in reduced measurement accuracy. descend. Even if the clock frequency of the A/D converter were to be synchronized with the commercial power supply frequency, a new dedicated phase control circuit would be required, making the curve tracer expensive.
本発明の素子測定装置は、外部電源周波数に同期１２、
かつこの外部電源周波数よりも高い周波数のパルスを発
生するパルス発生手段４８〜５０と、このパルス発生手
段からの出力パルスを分周する分周器５２と、この分周
器の出力パルスに応じて外部電源と同相の繰返し波形電
圧を発生する繰返し波形発生器５４と、この繰返し波形
発生器からの繰返し波形電圧を被測定素子に供給する電
圧供給手段１２〜１４と、被測定素子に供給される電圧
及び被測定素子に流れる電流を、パルス発生手段又は分
周器の出力パルスに応じてデジタル信号に変換するアナ
ログ・デジタル変換手段５８〜６４と、このアナログ・
デジタル変換手段のデジタル出力信号を記憶する記憶回
路６６とを具えている。The device measuring device of the present invention is synchronized with the external power supply frequency.
and pulse generating means 48 to 50 that generate pulses with a frequency higher than this external power supply frequency, a frequency divider 52 that frequency divides the output pulse from this pulse generating means, and a frequency divider 52 that divides the output pulse from this frequency divider. A repetitive waveform generator 54 that generates a repetitive waveform voltage that is in phase with an external power source; voltage supply means 12 to 14 that supplies the repetitive waveform voltage from the repetitive waveform generator to the device under test; Analog-to-digital conversion means 58 to 64 convert voltage and current flowing through the device under test into digital signals according to output pulses from the pulse generation means or frequency divider;
The storage circuit 66 stores the digital output signal of the digital conversion means.
本発明によれば、繰返し波形発生器によυ新たに繰返し
波形電圧、例えば正弦波電圧を発生しているので、この
電圧波形は外部電源波形のように歪を含んでおらず対称
であるため、上述の表示歪の問題を解決できる。また、
新たに発生した繰返し波形電圧は外部電源電圧と独立し
ているので、この外部電源電圧の変動にも影響されず、
正確な測定ができる。更に、パルス発生手段及び分周器
により、繰返し波形発生器からの繰返し波形電圧は外部
電源と同相になるので、この繰返し波形電圧を受ける各
回路は外部電源によるリップル、位相変動等の影響を受
けない。また、アナログ・デジタル変換手段は外部電源
に同期して被測定素子の電圧及び電流をサンプルするの
で、外部電源の変動による影響を受けない。更にまた、
パルス発生手段及び分周器の出力信号は繰返し波形発生
器及びアナログ・デジタル変換手段に共用できるので、
構成を簡略化できる。According to the present invention, since the repetitive waveform generator generates a new repetitive waveform voltage, for example, a sine wave voltage, this voltage waveform does not include distortion and is symmetrical unlike the external power supply waveform. , the above-mentioned display distortion problem can be solved. Also,
The newly generated repetitive waveform voltage is independent of the external power supply voltage, so it is not affected by fluctuations in this external power supply voltage.
Accurate measurements can be made. Furthermore, the pulse generation means and frequency divider cause the repetitive waveform voltage from the repetitive waveform generator to be in phase with the external power supply, so each circuit that receives this repetitive waveform voltage is not affected by ripples, phase fluctuations, etc. caused by the external power supply. do not have. Further, since the analog-to-digital conversion means samples the voltage and current of the device under test in synchronization with the external power supply, it is not affected by fluctuations in the external power supply. Furthermore,
The output signals of the pulse generation means and frequency divider can be shared by the repetitive waveform generator and analog-to-digital conversion means.
The configuration can be simplified.
以下、添付図を参照して本発明の好適な実施例を説明す
る。Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
第１及び第２図は本発明の好適な実施例のブロック図で
あり、第１図の信号が第２図に供給され、全体として１
つの素子測定装置を構成する。外部の商用電源からの交
流電圧は電源スィッチ３４を介して電源回路３６内の変
圧器４０の１次巻線に供給する。変圧器４０の複数の２
次巻線を電源回路３６内の直流電圧安定化回路（図示せ
ず）に接続して、各回路用の直流電圧を発生させる。変
圧器４０の最下端の２次巻線における接地に対する交流
電圧を抵抗器４２及び４４により分圧する。1 and 2 are block diagrams of a preferred embodiment of the present invention, in which the signals of FIG. 1 are fed into FIG.
A single element measuring device is constructed. AC voltage from an external commercial power source is supplied to the primary winding of a transformer 40 in a power supply circuit 36 via a power switch 34 . 2 of the transformers 40
The next winding is connected to a DC voltage stabilizing circuit (not shown) in power supply circuit 36 to generate DC voltage for each circuit. The alternating current voltage with respect to ground in the lowermost secondary winding of transformer 40 is divided by resistors 42 and 44 .
電圧比較器４６はこの分圧された交流電圧と接地電圧と
を比較し、電源電圧が接地電圧と交差する毎にそのレベ
ルが反転するパルス信号ｆＬを発生する。このパルス信
号ｆＬは外部電源電圧と周波数及び位相が等しいことに
注意されたい。The voltage comparator 46 compares this divided AC voltage with the ground voltage, and generates a pulse signal fL whose level is inverted every time the power supply voltage crosses the ground voltage. It should be noted that this pulse signal fL has the same frequency and phase as the external power supply voltage.
可変周波数信号発生器（ＶＣＯ）５０の発振周波数はパ
ルス信号ｆＬの２ｎ倍（ｎ：正の整数）であシ、例えば
４０９６倍であり、その出力信号（４０９６ｆＬ）を分
周器５２であるカウンタのクロック端子に供給する。分
周器５２はＶ６Ｏ１３の出力信号を分周し、周波数がパ
ルス信号ｆ、の２０４８倍の信号２０４８ｆ、１０２４
倍の信号１０２４ｆ 、 １６倍の信号１６ｆ、８倍
の信号材、４倍の信号「、２倍の信号Ｕ及び等しい信号
ｆを発生する。なお、２０４８ｆ。The oscillation frequency of the variable frequency signal generator (VCO) 50 is 2n times (n: a positive integer) the pulse signal fL, for example 4096 times, and the output signal (4096fL) is applied to the counter which is the frequency divider 52. Supplied to the clock terminal of The frequency divider 52 divides the output signal of the V6O13 to generate a signal 2048f, 1024, whose frequency is 2048 times that of the pulse signal f.
A double signal 1024f, a 16 times signal 16f, an 8 times signal material, a 4 times signal "," a double signal U, and an equal signal f are generated. Note that 2048f.
１０２４ｆ、 Ｎ汀、訂、ｎ及び訂の横線は人力信号に
対し、位相反転されたものであることを示す。1024f, N, correction, horizontal lines of n and correction indicate that the phase of the human input signal has been inverted.
位相比較器４８はパルス信号ｆＬと分周器５２からの出
力パルス信号ｆとの位相を比較し、パルス信号ｆＬとｆ
との位相が等しくなるように、Ｖ６Ｏ１３の発振周波数
を制御する。よって、位相比較器４８、Ｖ６Ｏ１３及び
分周器５２は位相ロック−ループを形成し、分周器５２
の各出力パルスは外部電源に同期する。壕だ、位相比較
器４８及びＶ６Ｏ１３はパルス発生手段となる。The phase comparator 48 compares the phases of the pulse signal fL and the output pulse signal f from the frequency divider 52, and compares the phases of the pulse signal fL and the output pulse signal f from the frequency divider 52.
The oscillation frequency of V6O13 is controlled so that the phase is equal to that of V6O13. Therefore, the phase comparator 48, V6O13 and the frequency divider 52 form a phase-locked loop, and the frequency divider 52
Each output pulse of is synchronized to an external power supply. In fact, the phase comparator 48 and V6O13 serve as pulse generating means.
分周器５２の出力パルス１６ｆ、８ｆ、４ｆ、２ｆ及び
ｆを繰返し波形発生器５４に供給して、外部電源周波数
と同相で所定振幅の繰返し波形電圧、例えば正弦波電圧
（以下、正弦波電圧として説明する）を発生する。この
繰返し波形発生器５４については、第３図を参照して詳
細に後述する。繰返し波形発生器５４からの正弦波電圧
は、可変増幅器５６又は他の適当なアナログ掛算器を介
して変圧器１２の１次巻線に供給する。変圧器１２の２
次側は、第４図の従来例と同様であり、選択整流回路１
４が測定レンジに応じて２次巻線のタップの１つを選択
し、選択されたタップからの正弦波電圧を整流する。選
択整流回路１４からの整流された電圧は、リミッタ用抵
抗器１６を介して被測定半導体素子であるトランジスタ
１８のコレクタに供給する。これら変圧器１２及び選択
整流回路１４等は電圧供給手段となる。変圧器１２の２
次巻線の下端は、電流検出用抵抗器２ｏを介して被測定
素子であるトランジスタ１８のエミッタに接続すると共
に接地する。また、トランジスタ１８のベースには、分
周器５２の出力パルスｆに同期してステップ状に変化す
るバイアス信号をバイアス供給回路２２から供給する。The output pulses 16f, 8f, 4f, 2f, and f of the frequency divider 52 are supplied to a repetitive waveform generator 54 to produce a repetitive waveform voltage having a predetermined amplitude and in phase with the external power supply frequency, such as a sine wave voltage (hereinafter referred to as a sine wave voltage). ) occurs. This repetitive waveform generator 54 will be described in detail later with reference to FIG. The sinusoidal voltage from the repetitive waveform generator 54 is applied to the primary winding of the transformer 12 via a variable amplifier 56 or other suitable analog multiplier. Transformer 12-2
The next side is the same as the conventional example shown in FIG. 4, and the selective rectifier circuit 1
4 selects one of the taps of the secondary winding according to the measurement range and rectifies the sinusoidal voltage from the selected tap. The rectified voltage from the selective rectifier circuit 14 is supplied to the collector of a transistor 18, which is a semiconductor element to be measured, via a limiter resistor 16. These transformer 12, selective rectifier circuit 14, etc. serve as voltage supply means. Transformer 12-2
The lower end of the next winding is connected to the emitter of the transistor 18, which is the element to be measured, via the current detection resistor 2o, and is also grounded. Further, a bias signal that changes stepwise in synchronization with the output pulse f of the frequency divider 52 is supplied to the base of the transistor 18 from the bias supply circuit 22 .
々お、図では被測定トランジスタ１８がエミッタ接地形
式でカーブ・トレーサに接続されているが、ベース接地
形式又はコレクタ接地形式でもよい。高入力インピーダ
ンスの電圧検出回路２４は被測定トランジスタ１８のコ
レクタ及びエミッタ間の電圧ｖｃＥを検出し、適当に分
圧する。また、高入力インピーダンスの電圧検出回路３
０は抵抗器２０の両端の電圧差、即ち被測定トランジス
タ１８のコレクタ電流ＩＣを検出する。In the figure, the transistor to be measured 18 is connected to the curve tracer in an emitter-grounded manner, but it may be in a base-grounded type or a collector-grounded type. The high input impedance voltage detection circuit 24 detects the voltage vcE between the collector and emitter of the transistor under test 18 and divides it appropriately. In addition, the voltage detection circuit 3 with high input impedance
0 detects the voltage difference across the resistor 20, that is, the collector current IC of the transistor under test 18.
本発明では、電圧検出器２４及び３ｏの検出した電圧（
検出器３０の場合は、電圧に変換された電流）をデジタ
ル信号に変換するため、アナログ・デジタル（Ａ／Ｄ
）変換手段を設けている。このＡ／１）変換手段はサン
プル・ホールド（Ｓ／Ｈ）回路、Ａ／Ｄ変換器等で構成
されている。Ｓ／Ｈ回路５８及び６０は分周器５２の出
力パルス１０２４ｆに応じて電圧検出器２４及び３０の
出力電圧をサンプルし、ホールドする。正弦波発生器５
４の１周期はｆ分の１なので、この１周期内に１０２４
の点がサンプルされることになる。電子スイッチ６２は
分周器５２の出力パルス１０２４ｆの半周期毎ＫＳ／Ｈ
回路５８及び６０を交互に選択して、その出力信号をＡ
／Ｄ変換器６４に供給する。このＡ／Ｄ変換器６４は、
スイッチ６２がＳ／Ｈ回路５８及び６０を交互に選択す
るだめ、クロック信号として分周器５２の出力パルス２
０４８ｆ （１０２４ｆの２倍の周波数）を受け、Ｓ／
Ｈ回路５８及び６０からのアナログ電圧を交互にデジタ
ル信号に変換する。なお、パルス１０２４ｆ及び２０４
８ｆは共に外部電源に同期している点に注意されたい。In the present invention, the voltage detected by the voltage detectors 24 and 3o (
In the case of the detector 30, analog/digital (A/D) is used to convert the current converted into voltage into a digital signal.
) A conversion means is provided. This A/1) conversion means is composed of a sample and hold (S/H) circuit, an A/D converter, and the like. The S/H circuits 58 and 60 sample and hold the output voltages of the voltage detectors 24 and 30 according to the output pulse 1024f of the frequency divider 52. Sine wave generator 5
One period of 4 is 1/f, so within this one period there are 1024
points will be sampled. The electronic switch 62 outputs KS/H every half period of the output pulse 1024f of the frequency divider 52.
Circuits 58 and 60 are alternately selected to output their output signals to A.
/D converter 64. This A/D converter 64 is
Since the switch 62 alternately selects the S/H circuits 58 and 60, the output pulse 2 of the frequency divider 52 is used as a clock signal.
048f (twice the frequency of 1024f), S/
Analog voltages from H circuits 58 and 60 are alternately converted to digital signals. In addition, pulses 1024f and 204
Note that both 8f are synchronized to an external power supply.
Ａ／Ｄ変換器６４のデジタル出力信号は第２図の制御回
路６８のアドレス信号に応じてデジタル記憶回路６６に
記憶される。制御回路６８は記憶回路６６の書込みモー
ド及び読出しモードを制御すると共に、書込みモードで
は分周器５２の出力パルス２０４８ｆを計数して書込み
アドレス信号を発生し、また読出しモードでは読出しク
ロック信号発生器７０のクロック信号を計数して読出し
アドレス信号を発生する。よって、書込みモードにおい
て、例えばＳ／Ｈ回路５８の出力信号（ＶＣＥ ）は記
憶回路６６の奇数アドレスに記憶され、Ｓ／Ｈ回路工Ｃ
６０の出力信号（井）は記憶回路６６の偶数アドレスに
記憶される。このように、被測定半導体素子１８に供給
される電圧は、外部電源と同相であるが、その振幅や波
形が外部電源に影響されず、またＳ／Ｈ回路５８及び６
０、電子スイッチ６２、Ａ／Ｄ変換器６４が外部電源に
同期して動作するので、外部電源の電圧や位相変動、波
形歪に関係なく、被測定半導体素子の特性を表わすデジ
タル値を記憶回路に記憶できる。The digital output signal of the A/D converter 64 is stored in the digital storage circuit 66 in response to the address signal of the control circuit 68 shown in FIG. The control circuit 68 controls the write mode and the read mode of the memory circuit 66, and in the write mode, counts the output pulses 2048f of the frequency divider 52 to generate a write address signal, and in the read mode, it counts the output pulses 2048f of the frequency divider 52 and generates a write address signal. A read address signal is generated by counting the clock signals. Therefore, in the write mode, for example, the output signal (VCE) of the S/H circuit 58 is stored in the odd address of the storage circuit 66, and the output signal (I) of the S/H circuit C 60 is stored in the even address of the storage circuit 66. be remembered. In this way, the voltage supplied to the semiconductor device under test 18 is in phase with the external power supply, but its amplitude and waveform are not affected by the external power supply, and the S/H circuits 58 and 6
0. Since the electronic switch 62 and A/D converter 64 operate in synchronization with the external power supply, the storage circuit stores digital values representing the characteristics of the semiconductor device under test, regardless of the voltage, phase fluctuation, and waveform distortion of the external power supply. can be memorized.
読出しモードにおいて、ランチ回路７２はアドレス信号
のＬＳＢ（最下位ビット）によシ記憶回路６６の偶数ア
ドレスの記憶内容を順次ラッチし、ラッチ回路７４はイ
ンバータ７６で位相反転されたアドレス信号のＬＳＢに
よシ記憶回路６６の奇数アドレスの記憶内容を順次ラッ
チする。ラッチ回路７８はラッチ回路７４のラッチ動作
と同時にラッチ回路７２の内容をラッチするので、デジ
タル・アナログ（Ｄ／Ａ ）変換器８０及び８２には、
夫工Ｇ
夫ラッチ回路７８の＃のデジタル値及びラッチ回路７４
０■。、のデジタル値が同時に供給され、アナログ信号
に変換される。これらアナログ信号は増幅器２６及び３
２を介してＣＲＴ２８の垂直偏向板及び水平偏向板に供
給されて、ＩＣＶＣＥ特性を表示する。なお、記憶回路
６６の読出しデジタル信号をコンビーータ等に供給して
、種々の処理を行なってもよい。In the read mode, the launch circuit 72 sequentially latches the contents of even addresses in the storage circuit 66 using the LSB (least significant bit) of the address signal, and the latch circuit 74 latches the LSB (least significant bit) of the address signal whose phase has been inverted by the inverter 76. The contents stored at odd addresses in the storage circuit 66 are sequentially latched. Since the latch circuit 78 latches the contents of the latch circuit 72 simultaneously with the latching operation of the latch circuit 74, the digital-to-analog (D/A) converters 80 and 82
#digital value of # of latch circuit 78 and latch circuit 74
0 ■. , are simultaneously supplied and converted into analog signals. These analog signals are transmitted to amplifiers 26 and 3.
2 to the vertical deflection plate and horizontal deflection plate of the CRT 28 to display ICVCE characteristics. Note that the read digital signal of the storage circuit 66 may be supplied to a converter or the like to perform various processing.
次に第３図を参照して繰返し波形発生器５４の一例を説
明する。なお、この例では正弦波電圧を発生する。分周
器５２の出力パルス石汀、 ８ｆ、 ４ｆ。Next, an example of the repetitive waveform generator 54 will be explained with reference to FIG. Note that in this example, a sine wave voltage is generated. Output pulses of the frequency divider 52, 8f, 4f.
２ｆ及びｆを符号化回路に供給する。この符号化回路は
４個の排他的オア・ゲー）（ＸＯＲ）８４〜９０を含ん
でおり、ＸＯＲ８４はパルス１６ｆ 及びΣ１”を受け
、Ｘ０Ｒ８６はパルス訂及び２ｆを受け、Ｘ０Ｒ８８は
パルス丁］１及び■を受け、Ｘ０Ｒ９０はパルス２ｆ及
びｆを受ける。よって、Ｘ０Ｒ９０（７）出力パルスＳ
はパルスｆ即ちｆＬよりも位相が９０度遅れ、Ｘ０Ｒ８
４〜８８の出力パルス信号Ａ −ＣはパルスＳの９０度
（４分の１周期）毎にｒｏ ００Ｊ〜ｒｌ ｌ ＩＪに
まだｒｌｌｌＪ〜ｒ０００Ｊに変化する３ビツトのデジ
タル信号となる。2f and f to the encoding circuit. This encoding circuit includes four exclusive OR gates (XOR) 84-90, where XOR84 receives pulses 16f and Σ1'', X0R86 receives pulse correction and 2f, and X0R88 receives pulses 16f and Σ1''. and ■, X0R90 receives pulses 2f and f. Therefore, X0R90 (7) output pulse S
is delayed in phase by 90 degrees from the pulse f, that is, fL, and X0R8
The output pulse signals A to C of 4 to 88 are 3-bit digital signals that change from ro00J to rllIJ to rllllJ to r000J every 90 degrees (one quarter period) of the pulse S.
第１選択手段であるアナログ・マルチプレクサ９２はＸ
０Ｒ８４〜８８からのデジタル信号Ａ〜Ｃにより、入力
端子■を出力端子Ｏ〜７の１つに選択的に接続する。即
ち、選択端子Ａ−Ｃの信号がｒｏ ＯＯＪのとき出力端
子０を選択し、ｒｏ ０１Ｊのとき出力端子１を選択し
、ｒｏ １０Ｊのとき出力端子２を選択し、以下同様に
ｒｏｌｌＪ 、 ｒｌｏｏＪ 。The analog multiplexer 92, which is the first selection means,
Digital signals A-C from 0R84-88 selectively connect input terminal (2) to one of output terminals O-7. That is, when the signal at the selection terminals A-C is ro OOJ, output terminal 0 is selected, when ro 01J, output terminal 1 is selected, when ro 10J, output terminal 2 is selected, and so on.rollJ, rlooJ.
ｒｌｏｌｊ 、 ｒｌｌＯＪ及びｒｌ １１Ｊのとき
夫々出力端子３．４．５．６及び７を選択する。マルチ
プレクサ９２の出力端子Ｏ〜７を夫々抵抗器９４〜１０
８の一端に接続し、これら抵抗器の他端を積分器の入力
端に接続する。この積分器は、非反転入力端が接地され
た演算増幅器１１０、並びにこの演算増幅器の反転入力
端及び出力端間に接続されたコンデンサ１１２により構
成する。よって、選択された抵抗器９４〜１０８の１つ
が入力抵抗器であるミラー積分器となる。なお、これら
抵抗器９４〜１０８の値は例えば、夫々１５．ＯＫＯ，
１６，９ＫΩ。When rlolj, rllOJ and rl11J, select output terminals 3.4.5.6 and 7, respectively. The output terminals O to 7 of the multiplexer 92 are connected to resistors 94 to 10, respectively.
8, and the other ends of these resistors are connected to the input of the integrator. This integrator consists of an operational amplifier 110 whose non-inverting input terminal is grounded, and a capacitor 112 connected between the inverting input terminal and the output terminal of this operational amplifier. Therefore, one of the selected resistors 94-108 becomes a Miller integrator as the input resistor. Note that the values of these resistors 94 to 108 are, for example, 15. OK,
16.9KΩ.
１９、ＩＫΩ、２３．７にΩ、３１．６にΩ、５１．１
にΩ及び１５４にΩであり、コンデンサ１１２の値は例
えば０．１μＦである。19, IKΩ, Ω at 23.7, Ω at 31.6, 51.1
Ω and 154Ω, and the value of the capacitor 112 is, for example, 0.1 μF.
積分器の出力信号Ｑをピーク値検出器を介して電圧比較
器１１４に供給する。このピーク検出器はダイオード１
１６、コンデンサ１１８、抵抗器１２０及び１２２によ
り構成する。電圧比較器１１４は、積分器の出力信号Ｑ
のピーク値と基準電圧ＶＲＥＦとを比較し、それらの差
である出力電圧は抵抗器１２４及び１２６により、分圧
されて、反転増幅器１２８及び非反転増幅器１３０に供
給される。なお、反転増幅器１２８の入力抵抗器１３２
及び帰還抵抗器１３４の値は等しい。増幅器１２８及び
１３０の出力電圧は第２選択手段である電子スイッチ１
３６を介してマルチプレクサ９２の入力端子■に供給す
る。また、電子スインｆ−１３６ｔ−パルス信号Ｓによ
り制御する。The output signal Q of the integrator is provided to a voltage comparator 114 via a peak value detector. This peak detector is diode 1
16, a capacitor 118, and resistors 120 and 122. Voltage comparator 114 outputs the integrator output signal Q
The peak value of is compared with the reference voltage VREF, and the output voltage that is the difference between them is divided by resistors 124 and 126 and supplied to an inverting amplifier 128 and a non-inverting amplifier 130. Note that the input resistor 132 of the inverting amplifier 128
and the values of feedback resistor 134 are equal. The output voltages of the amplifiers 128 and 130 are controlled by the electronic switch 1 which is the second selection means.
36 to the input terminal (3) of the multiplexer 92. Further, it is controlled by an electronic swing f-136t-pulse signal S.
よって、最初４分の１周期は、スイッチ１３６により非
反転増幅器１３０の出力信号がマルチプレクサ９２０入
力端子■に供給される。また、パルス信号Ａ−Ｃにより
、この４分の１周期を８等分して抵抗器９４〜１０８を
順次選択するので、積分器の出力信号Ｑは正弦波の４分
の１周期となる。次の４分の１周期は、反転増幅器１２
８の出力電圧がマルチプレクサ９２の入力端子Ｉに供給
され、またこの期間を８等分して抵抗器１０８〜９４を
順次選択する。以下、同様な動作により積分器の出力信
号Ｑは電源周波数と同相な繰返し正弦波電圧になる。な
お、ピーク検出器１１６〜１２２と電圧比較器１１４と
により、積分器の入力電圧を制御してこの正弦波電圧Ｑ
の振幅を一定に保持しているので、外部商用電源の周波
数及び振幅の変動に正弦波電圧Ｑの振幅は影響されない
。Therefore, for the first quarter cycle, the switch 136 supplies the output signal of the non-inverting amplifier 130 to the multiplexer 920 input terminal (2). Further, since this quarter period is divided into eight equal parts and the resistors 94 to 108 are sequentially selected by the pulse signal A-C, the output signal Q of the integrator becomes a quarter period of the sine wave. The next quarter period is the inverting amplifier 12
8 output voltages are supplied to input terminal I of multiplexer 92, and this period is divided into eight equal parts to sequentially select resistors 108-94. Thereafter, by similar operation, the output signal Q of the integrator becomes a repetitive sine wave voltage in phase with the power supply frequency. Note that the input voltage of the integrator is controlled by the peak detectors 116 to 122 and the voltage comparator 114 to obtain this sine wave voltage Q.
Since the amplitude of the sine wave voltage Q is held constant, the amplitude of the sine wave voltage Q is not affected by fluctuations in the frequency and amplitude of the external commercial power supply.
本発明の好適な実施例について説明したが、本発明の要
旨を逸脱することなく種々の変形及び変更が可能である
。例えば、 Ｓ／Ｈ回路５８及び６０の後段に夫々専用
のＡ／Ｄ変換器及び記憶回路を接続してもよい。また、
Ａ／Ｄ変換器の動作が高速ならば、Ｓ／Ｈ回路は不要で
ある。更に、第３図において、抵抗器９４〜１０８の数
及び値を変更することにより、３角波等の繰返し波形電
圧を発生することもできる。また、アナログ・デジタル
変換手段に供給するパルスは、バイアス供給回路２２か
らのステソゲ状バイアスのステップ数に応じて、２０４
８ｆ及び１０２４ｆ以外の種々の周波数のパルスが利用
できる。この場合、スイッチによシ分周器の複数の出力
パルスを選択すればよい。Although preferred embodiments of the invention have been described, various modifications and changes can be made without departing from the spirit of the invention. For example, dedicated A/D converters and memory circuits may be connected to the subsequent stages of the S/H circuits 58 and 60, respectively. Also,
If the A/D converter operates at high speed, the S/H circuit is not necessary. Furthermore, in FIG. 3, by changing the number and values of resistors 94 to 108, it is also possible to generate a repetitive waveform voltage such as a triangular wave. Further, the number of pulses supplied to the analog-to-digital conversion means is 204, depending on the number of steps of the stethoscope bias from the bias supply circuit 22.
Pulses of various frequencies other than 8f and 1024f are available. In this case, a switch may be used to select a plurality of output pulses from the frequency divider.
〔発明の効果〕
上述の如く本発明によれば、新たに正弦波電圧等の繰返
し波形電圧を発生しているので、この電圧波形は外部電
源波形のように歪を含んでおらず対称であるため、表示
歪の問題を解決できる。まだ、新だに発生した繰返し波
形電圧は外部電源電圧と独立しているので、この外部電
源電圧の変動にも影響されず、正確な測定ができる。更
に、繰返し波形電圧は外部電源と同相なので、この繰返
し波形電圧を受ける各回路は外部電源によるリップル、
位相変動等の影響を受けない。塘た、アナログ・デジタ
ル変換手段は外部電源に同期して被測定半導体素子の電
圧及び電流をサンプルするので、外部電源の変動による
影響を受けない。更にまた、パルス発生手段及び分周器
の出力信号は正弦波発生器及びアナログ・デジタル変換
手段に共用できるので、構成を簡略化できる。[Effects of the Invention] As described above, according to the present invention, since a repetitive waveform voltage such as a sine wave voltage is newly generated, this voltage waveform does not include distortion and is symmetrical unlike the external power supply waveform. Therefore, the problem of display distortion can be solved. However, since the newly generated repetitive waveform voltage is independent of the external power supply voltage, it is not affected by fluctuations in the external power supply voltage and can be accurately measured. Furthermore, since the repetitive waveform voltage is in phase with the external power supply, each circuit that receives this repetitive waveform voltage is subject to ripples and ripples caused by the external power supply.
Not affected by phase fluctuations, etc. Furthermore, since the analog-to-digital conversion means samples the voltage and current of the semiconductor device under test in synchronization with the external power supply, it is not affected by fluctuations in the external power supply. Furthermore, since the output signals of the pulse generating means and the frequency divider can be shared by the sine wave generator and the analog-to-digital converting means, the configuration can be simplified.
第１及び第２図は本発明の好適な一実施例のブロック図
、第３図は第１図内の繰返し波形発生器の一例の回路図
、第４図は従来の素子測定装置のブロック図である。
図において、１２〜１４は電圧供給手段、４８〜５０は
パルス発生手段、５２は分周器、５４は繰返し波形発生
器、５８〜６４はアナログ・デジタル変換手段、６６は
記憶回路である。1 and 2 are block diagrams of a preferred embodiment of the present invention, FIG. 3 is a circuit diagram of an example of the repetitive waveform generator shown in FIG. 1, and FIG. 4 is a block diagram of a conventional device measuring device. It is. In the figure, 12 to 14 are voltage supply means, 48 to 50 are pulse generation means, 52 is a frequency divider, 54 is a repetitive waveform generator, 58 to 64 are analog/digital conversion means, and 66 is a storage circuit.
Claims (1)
高い周波数のパルスを発生するパルス発生手段と、該パ
ルス発生手段からの出力パルスを分周する分周器と、該
分周器の出力パルスに応じて上記外部電源と同相の繰返
し波形電圧を発生する繰返し波形発生器と、該繰返し波
形発生器からの繰返し波形電圧を被測定素子に供給する
電圧供給手段と、上記被測定素子に供給される電圧及び
上記被測定素子に流れる電流を、上記パルス発生手段又
は上記分周器の出力パルスに応じてデジタル信号に変換
するアナログ・デジタル変換手段と、該アナログ・デジ
タル変換手段のデジタル出力信号を記憶する記憶回路と
を具えた素子測定装置。A pulse generating means for generating pulses in synchronization with an external power supply frequency and having a higher frequency than the external power supply frequency, a frequency divider for dividing the output pulse from the pulse generation means, and an output pulse of the frequency divider. a repetitive waveform generator that generates a repetitive waveform voltage that is in phase with the external power supply according to the voltage; a voltage supply means that supplies the repetitive waveform voltage from the repetitive waveform generator to the device under test; analog-to-digital conversion means for converting the voltage flowing through the device under test and the current flowing through the device under test into digital signals in accordance with the output pulses of the pulse generation means or the frequency divider; An element measuring device comprising a memory circuit for storing information.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20879284A JPS6186664A (en) | 1984-10-04 | 1984-10-04 | Apparatus for measuring element |
| NL8502385A NL8502385A (en) | 1984-10-04 | 1985-08-30 | DEVICE FOR MEASURING THE CHARACTERISTICS OF ELECTRONIC DEVICES. |
| GB08522462A GB2165363B (en) | 1984-10-04 | 1985-09-11 | Waveform generator and apparatus for measuring characteristics of electronic devices |
| DE19853533636 DE3533636C2 (en) | 1984-10-04 | 1985-09-20 | Device for measuring the characteristic data of electronic components |
| US06/780,957 US4727318A (en) | 1984-10-04 | 1985-09-27 | Apparatus for measuring characteristics of electronic devices |
| CA000491897A CA1242813A (en) | 1984-10-04 | 1985-09-30 | Apparatus for measuring characteristics of electronic devices |
| FR8514776A FR2571501B1 (en) | 1984-10-04 | 1985-10-04 | APPARATUS FOR MEASURING THE CHARACTERISTICS OF ELECTRONIC DEVICES |
| US07/074,910 US4782290A (en) | 1984-10-04 | 1987-07-17 | Apparatus for measuring characteristics or electronic devices |
| CA000547089A CA1248600A (en) | 1984-10-04 | 1987-09-16 | Sine-wave generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20879284A JPS6186664A (en) | 1984-10-04 | 1984-10-04 | Apparatus for measuring element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6186664A true JPS6186664A (en) | 1986-05-02 |
| JPS649595B2 JPS649595B2 (en) | 1989-02-17 |
Family
ID=16562187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20879284A Granted JPS6186664A (en) | 1984-10-04 | 1984-10-04 | Apparatus for measuring element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6186664A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255670A (en) * | 1987-04-13 | 1988-10-21 | Sony Tektronix Corp | Element measuring apparatus |
| US7466253B2 (en) | 2006-08-03 | 2008-12-16 | Kabushiki Kaisha Toshiba | Integrated circuit, self-test method for the integrated circuit, and optical disc apparatus including the integrated circuit |
-
1984
- 1984-10-04 JP JP20879284A patent/JPS6186664A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255670A (en) * | 1987-04-13 | 1988-10-21 | Sony Tektronix Corp | Element measuring apparatus |
| US7466253B2 (en) | 2006-08-03 | 2008-12-16 | Kabushiki Kaisha Toshiba | Integrated circuit, self-test method for the integrated circuit, and optical disc apparatus including the integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS649595B2 (en) | 1989-02-17 |
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