JPS6184110A - Voltage comparator - Google Patents
Voltage comparatorInfo
- Publication number
- JPS6184110A JPS6184110A JP20591484A JP20591484A JPS6184110A JP S6184110 A JPS6184110 A JP S6184110A JP 20591484 A JP20591484 A JP 20591484A JP 20591484 A JP20591484 A JP 20591484A JP S6184110 A JPS6184110 A JP S6184110A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- clock
- activated
- differential voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Measurement Of Current Or Voltage (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は被測定電圧を基準電圧と比較し結果を論理レベ
ルで出力するチオツバ型式の電圧比較器＠ＣＭＯＳデバ
イスで構成したものの改良に関するものである。[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to an improvement of a Chiotsuba-type voltage comparator @CMOS device that compares a voltage to be measured with a reference voltage and outputs the result at a logic level. be.
（従来の技術）
チョッパ型式の電圧比較器（以下コンパレータと称す）
は被測定電圧の標本化（サンプル）のステートと基準電
圧との比較（コンベア）のステート金交互に繰シ返えす
ことにエリ時系列的な電圧比較動作を行なうものである
。(Prior art) Chopper type voltage comparator (hereinafter referred to as comparator)
The voltage comparison operation is performed in a time-series manner by alternately repeating the state of sampling the voltage to be measured (sample) and the state of comparison (conveyor) with the reference voltage.
第１図は従来のコンパレータで、データ選択回路３は、
クロックφ寡がロウレベルであるサンプルステートでは
被測定電圧入力端子１１の電圧（以下ｖＩｎと称す）ｔ
−選択し、クロックφ１がノーイレペルで基準電圧入力
端子２の電圧Ｖｒｅｆｔ選択し差電圧増幅器４へ与える
。差電圧増幅器４゜５は電圧ｖｉｎとＶｒｅｆ のＭ
ｋ増幅するもので同一のものであり、コンパレータの分
解能に対応してカスケード接続するものであり、５く無
い場合もあフ複数の場合もある。当該コンパレータでは
差電圧増幅器４．５へサンプルステートに於て差電圧増
幅用インバータを最も電圧利得の高い動作点に保持する
ため、インバータをセルフバイアスさせる方法で得た動
作点設定電圧をその供給回路６から供給する。差電圧増
幅回路５の出力は波形整形用インバータ７を通力、クロ
ックφ、がハイレベルからロウレベルへ反転すると比較
器出力ラッチ用フリ、プフロ、プ８にう、チされ、その
論理レベルを出力端子９へ出力する。FIG. 1 shows a conventional comparator, and the data selection circuit 3 is
In the sample state where the clock φ is at low level, the voltage at the voltage input terminal 11 to be measured (hereinafter referred to as vIn) t
- is selected, and the voltage Vreft of the reference voltage input terminal 2 is selected and applied to the differential voltage amplifier 4 when the clock φ1 is no-repel. The differential voltage amplifier 4.5 has voltages vin and Vref M
They are the same for k amplification, and are connected in cascade according to the resolution of the comparator, and there may be more than five or more than five. In this comparator, in order to maintain the differential voltage amplification inverter at the operating point with the highest voltage gain in the sample state, the operating point setting voltage obtained by self-biasing the inverter is applied to the differential voltage amplifier 4.5 in its supply circuit. Supply from 6. The output of the differential voltage amplifier circuit 5 is passed through the waveform shaping inverter 7, and when the clock φ is inverted from high level to low level, it is passed to the comparator output latch circuit 8, and the logic level is output to the output terminal. Output to 9.
（発明が解決しようとする問題点）
上述した従来のコンパレータは、サンプルステートの期
間中インバータおよび波形整形用インバータ７には貫通
を流が流れることとなカ、当該コンパレータｔ−ＬＳＩ
の一部として使用する場合、ＬＳＩの低消費電流化の点
で好ましくないと込う欠点がある。本発明はかかる欠点
を改善し汎用性の高い電圧比較器を提供するものである
。(Problems to be Solved by the Invention) In the conventional comparator described above, a current flows through the inverter and the waveform shaping inverter 7 during the sample state, and the comparator T-LSI
When used as a part of the LSI, there is a drawback that it is not preferable in terms of reducing the current consumption of the LSI. The present invention aims to improve these drawbacks and provide a highly versatile voltage comparator.
（問題点ｔ−解決するための手段）
本発明の電圧比較器は、クロックのサイクルタイムで被
測定電圧又は基準電圧を交互に選択するデータ選択回路
と、該データ選択回路の出力全入力とし被測定電圧と基
準電圧の差電圧を前記クロ、クサイクルタイムで標本化
しデータラ、チ用クロックで能動化されて増幅する差電
圧増幅回路と、該差電圧増幅回路の出力を入力し前記デ
ータラ。(Problem t - Means for Solving) The voltage comparator of the present invention includes a data selection circuit that alternately selects a voltage to be measured or a reference voltage at the cycle time of a clock, and a data selection circuit that alternately selects a voltage to be measured or a reference voltage. a differential voltage amplification circuit that samples the difference voltage between the measurement voltage and the reference voltage at the clock cycle times and is activated and amplified by the data clock and clock;
チ用クロックで能動化される波形整形回路と、該波形整
形回路の出力を前記データラ、チ用クロ。A waveform shaping circuit is activated by the first clock, and the output of the waveform shaping circuit is used as the data controller and the first clock.
りでう、チするデータ７す、グアａツブと、前記差電圧
増幅回路の動作点を設定する動作点設定電圧供給回路と
を含んで溝底される。The circuit includes a data input circuit 7, a guide, and an operating point setting voltage supply circuit for setting the operating point of the differential voltage amplification circuit.
（実施例） 以下、図面を参照して本発明の詳細な説明する。(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.
第２図は本発明の一実施例の回路図、第３図は第２図の
回路の動作および第１図に示す回路の貫通電流の変化を
示すタイミングチャートである。FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a timing chart showing the operation of the circuit shown in FIG. 2 and changes in the through current of the circuit shown in FIG. 1.
りａ、りφ里がロウレベルすなわちサンプルステートで
はデータ選択回路１３［被測足蹴圧入力端子１１の電圧
ｖｉｎ ”：選択し差電圧増幅回路１４へ与える。−
ｔ ７を差電圧増幅回路１４には動作点設定電圧供給回
路１６から増幅用クロックドインバータ２１ｆ、最も利
得の高い状態に設定する電圧（コンパレータの電源電圧
のｌ／２．以下ＶＴＨと称す）も与える。差電圧（ｖｉ
ｎ−ｖＴや）は差電圧保持用コンデンサ２０に蓄えられ
る。この時点ではクロックφ２がロウレベルであるため
クロ、クドインバータ２１は非能動状態にある。ま７？
：第２の差電圧増幅回路１５の増幅用クロックドインバ
ータ２２ｒｓ、、クロ、クドインバータ２１と同一状態
にある。さらに、波形整形用クロ、クドインパータ１７
もクロックφ３がロウレベルであるため非能動状態とな
っている。従ってこのステートで電流を消費しているの
は動作点設定電圧供給回路１６のインバータ２３のみで
ある。When RIa and RIφri are at low level, that is, in the sample state, the data selection circuit 13 [voltage vin'' of the foot kick pressure input terminal 11 to be measured] is selected and applied to the differential voltage amplification circuit 14.
t 7 to the differential voltage amplification circuit 14 from the operating point setting voltage supply circuit 16 to the clocked inverter 21f for amplification, and also the voltage (1/2 of the power supply voltage of the comparator, hereinafter referred to as VTH) that sets the highest gain state. give. Differential voltage (vi
n-vT) is stored in the differential voltage holding capacitor 20. At this point, the clock φ2 is at a low level, so the black and double inverters 21 are in an inactive state. 7?
: It is in the same state as the amplification clocked inverter 22rs, , clocked inverter 21 of the second differential voltage amplification circuit 15. In addition, a waveform shaping black, Kudo inperter 17
Since the clock φ3 is at a low level, it is also in an inactive state. Therefore, only the inverter 23 of the operating point setting voltage supply circuit 16 consumes current in this state.
次にクロックφ１がハイレベルに変化レコンペアステー
トとなると、データ選択回路１３はＶ・ ｎ
の選択状態から基準電圧（以下Ｖｒｅｆと称す）の選択
状態に移行する。第一、第二の差電圧増幅回路１４．１
５は動作点設定電圧供給回路１６からのＶＴＨの取り込
みを禁止し、供給回路１６のインバータ２３はセルフバ
イアス状態全解除して入力を電源電圧２４の高電位側に
固定する。Next, when the clock φ1 changes to a high level and enters the recompare state, the data selection circuit 13 shifts from the V·n selection state to the reference voltage (hereinafter referred to as Vref) selection state. First and second differential voltage amplification circuits 14.1
5 prohibits the acquisition of VTH from the operating point setting voltage supply circuit 16, and the inverter 23 of the supply circuit 16 completely releases the self-bias state and fixes the input to the high potential side of the power supply voltage 24.
ここで差醒圧保持用コンデンサ２０のデータ選択回路側
電位ば■ｒｅｆとなるからクロ、ノドインバータ２１０
入力端電位（以下Ｖ。１と称す）は下式となる。Here, the potential on the data selection circuit side of the differential pressure holding capacitor 20 becomes
The input terminal potential (hereinafter referred to as V.1) is expressed by the following formula.
Ｖｏ１＝■ｖｅｆ−（”ｉｎ−ＶＴＨ）＝（”ｒｅｆ−
Ｖｉｎ）＋ｖＴｌ（
従って、ｖｏｌは ｖＴＨから（” ｒ ｅ ｆ−ｖｉ
ｎ ） 疋はシフトした値となっている。さらに、タ
ロツクφ：がハイレベルとなると、クロックドインバー
タ２１゜２２．１７は各々能動状態となりデータフリッ
プフロップはデータを取り込み状態となる。クロックド
インバータ２１は利得ｔ” Ａ ｔ としてすの出力電
圧ｎ ＶＴＨ−ＡＩ・（■ｒ ｅ ｆ−ｖ４ ｎ）
とンより、クロックドインバータ２２の入力電圧（以
下Ｖ。２と称す〕となる。クロックドインバータ２２は
利得ｆＩニーＡ−２としてその出力■圧は■ＴＨ＋Ａｌ
−Ａ２・（Ｖｒｅｆ−Ｖ、ｎ）となりクロックドインバ
ータ１７の入力電圧（以下Ｖ。３と称）”ンとなる。
ここで差電圧（ｖｒｅｆ−ｖｌｎ）がＡ Ｉ ＠Ａ ２
によＶ十分増幅されていてＶ。３が電源′！り圧でクリ
ップしていれば、波形整形用インバータ１７は論理レベ
ルの反転用として機能し、増幅が不十分の場合はさらに
増幅器としても機能する。クロックφ意がハイレベルか
らロウレベルへ反転するとデータフリップフロップ１８
くインバータ１７の出力をラッチし、その論理レベルを
出力端子１９へ出力する。Vo1=■vef-("in-VTH)=("ref-
Vin) + vTl (Therefore, vol is from vTH to (”re f-vi
n) The value is shifted. Further, when the tarlock φ: becomes high level, the clocked inverters 21, 22, and 17 are each activated, and the data flip-flop becomes ready to take in data. The clocked inverter 21 has a gain t" A t and an output voltage n VTH-AI (■r e f-v4 n)
As a result, the input voltage (hereinafter referred to as V.2) of the clocked inverter 22 becomes the input voltage (hereinafter referred to as V.2).The clocked inverter 22 has a gain fI knee A-2, and its output
-A2·(Vref-V, n), which becomes the input voltage of the clocked inverter 17 (hereinafter referred to as V.3).
Here, the differential voltage (vref-vln) is A I @A 2
V is sufficiently amplified. 3 is the power supply'! If the voltage is clipped by the voltage, the waveform shaping inverter 17 functions as a logic level inverter, and if the amplification is insufficient, it also functions as an amplifier. When the clock signal φ is reversed from high level to low level, the data flip-flop 18
The output of the inverter 17 is latched and its logic level is output to the output terminal 19.
以上よりこのステートで電流を消費するのはクロックφ
２がハイレベルの期間のみである（第３図に２いて、従
来例お工び本発明の貫通電流を示す波形は、高レベルの
時点で貫通電流があること金示す。）。従って従来例で
にサンプルステート全期間および、Ｖｔｎとｖｒｅｆが
ほぼ一致している条件に於てはさらにコンベアステート
の全期間それぞれ差電圧増幅用インバータは電流を消費
する。From the above, it is the clock φ that consumes current in this state.
(The waveform 2 in FIG. 3, which shows the through current of the conventional example and the present invention, shows that there is a through current when the current is at a high level.) Therefore, in the conventional example, the inverter for differential voltage amplification consumes current during the entire period of the sample state and under the condition that Vtn and vref almost match, and further during the entire period of the conveyor state.
しかし本発明ではコンベアステート内のクロックφ、が
ハイレベルの期間のみ電流を消費するだけである。However, in the present invention, current is consumed only while the clock φ in the conveyor state is at a high level.
なお本実施例は種々の変更が可能であるが本発明の主た
る点は従来インバータで構成した差動増幅回路をクロ、
クドインバータ化し、これＧｆコンベアーステートの一
部期間のみ能動状態とすることにある。Although this embodiment can be modified in various ways, the main point of the present invention is to replace the conventional differential amplifier circuit composed of inverters with
The purpose is to convert it into a double inverter and make it active only during a part of the Gf conveyor state.
（発明の効果）
以上説明したように本発明の電圧比較器は、チヨ、バ型
式のコンパレータの低消費電流化がはかれ、０ＭＯ８Ｌ
ＳＩ の特徴である低消費電流のメリ、ト金損なうこ
となく電圧比較機能を用いるＣとができ、その効果は大
きい。(Effects of the Invention) As explained above, the voltage comparator of the present invention achieves low current consumption of Chiyo-Ba type comparators, and
It is possible to use the voltage comparison function without sacrificing the advantage of low current consumption, which is a feature of SI, and the effect is great.
第１図は従来の電圧比較器の回路図、第２図及び第３図
は本発明の一実施例の回路図及びその動作ｔ−説明する
タイミングチャードである。
１．１１・・・・・・被測定電圧入力端子、２．１２・
・・・・・基準電圧入力端子、３．１３・・・・−デー
タ選択回路、４，１４，５．１５・・・・差電圧増幅回
路、７゜１７・・・・・・波形整形用インバータ、８．
１８・・・・・比較器出力ラッチ用フリップフロップ、
６．１６・・・・・動作点設定電圧供給回路。
゛・ニ゛９、；−、ｇ。
＼、−一
等７図
需２ 図FIG. 1 is a circuit diagram of a conventional voltage comparator, and FIGS. 2 and 3 are circuit diagrams of an embodiment of the present invention and timing charts for explaining its operation. 1.11... Voltage input terminal to be measured, 2.12.
...Reference voltage input terminal, 3.13...-data selection circuit, 4,14,5.15...Difference voltage amplification circuit, 7゜17...For waveform shaping Inverter, 8.
18...Flip-flop for comparator output latch,
6.16...Operating point setting voltage supply circuit.゛・ni゛9,;-,g. ＼、-1st class 7 figure demand 2 figure
Claims (1)
交互に選択するデータ選択回路と、該データ選択回路の
出力を入力とし被測定電圧と基準電圧の差電圧を前記ク
ロックのサイクルタイムで標本化しデータラッチ用クロ
ックで能動化されて増幅する差電圧増幅回路と、該差電
圧増幅回路の出力を入力し前記データラッチ用クロック
で能動化される波形整形回路と、該波形整形回路の出力
を前記データラッチ用クロックでラッチするデータフリ
ップフロップと、前記差電圧増幅回路の動作点を設定す
る動作点設定電圧供給回路とを含むことを特徴とする電
圧比較器。A data selection circuit that alternately selects the voltage to be measured or a reference voltage at the cycle time of the clock, and a data latch that takes the output of the data selection circuit as input and samples the voltage difference between the voltage to be measured and the reference voltage at the cycle time of the clock. a differential voltage amplification circuit that is activated and amplified by the data latch clock; a waveform shaping circuit that receives the output of the differential voltage amplification circuit and is activated by the data latch clock; and a waveform shaping circuit that inputs the output of the differential voltage amplification circuit and is activated by the data latch clock; 1. A voltage comparator comprising: a data flip-flop that latches using a clock; and an operating point setting voltage supply circuit that sets an operating point of the differential voltage amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20591484A JPS6184110A (en) | 1984-10-01 | 1984-10-01 | Voltage comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20591484A JPS6184110A (en) | 1984-10-01 | 1984-10-01 | Voltage comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6184110A true JPS6184110A (en) | 1986-04-28 |
Family
ID=16514834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20591484A Pending JPS6184110A (en) | 1984-10-01 | 1984-10-01 | Voltage comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184110A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133410A (en) * | 1987-11-19 | 1989-05-25 | Fujitsu Ltd | Comparator |
| JPH01138808A (en) * | 1987-11-26 | 1989-05-31 | Toshiba Corp | Voltage comparator circuit |
| JPH03232313A (en) * | 1990-02-07 | 1991-10-16 | Yamaha Corp | Chopper type comparing circuit |
| US5262685A (en) * | 1991-10-16 | 1993-11-16 | Unitrode Corporation | High-speed, low power auto-zeroed sampling circuit |
| JP2010068048A (en) * | 2008-09-08 | 2010-03-25 | Sony Corp | Ad converter |
| US8120388B2 (en) | 2003-04-09 | 2012-02-21 | Sony Corporation | Comparator, sample-and-hold circuit, differential amplifier, two-stage amplifier, and analog-to-digital converter |
| JP2013048459A (en) * | 2006-01-16 | 2013-03-07 | Sk Hynix Inc | Apparatus for controlling on-die termination |
-
1984
- 1984-10-01 JP JP20591484A patent/JPS6184110A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133410A (en) * | 1987-11-19 | 1989-05-25 | Fujitsu Ltd | Comparator |
| JPH01138808A (en) * | 1987-11-26 | 1989-05-31 | Toshiba Corp | Voltage comparator circuit |
| JPH03232313A (en) * | 1990-02-07 | 1991-10-16 | Yamaha Corp | Chopper type comparing circuit |
| US5262685A (en) * | 1991-10-16 | 1993-11-16 | Unitrode Corporation | High-speed, low power auto-zeroed sampling circuit |
| US8120388B2 (en) | 2003-04-09 | 2012-02-21 | Sony Corporation | Comparator, sample-and-hold circuit, differential amplifier, two-stage amplifier, and analog-to-digital converter |
| JP2013048459A (en) * | 2006-01-16 | 2013-03-07 | Sk Hynix Inc | Apparatus for controlling on-die termination |
| JP2010068048A (en) * | 2008-09-08 | 2010-03-25 | Sony Corp | Ad converter |
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