JPS615345A - Serial multiplication method - Google Patents
Serial multiplication methodInfo
- Publication number
- JPS615345A JPS615345A JP12128184A JP12128184A JPS615345A JP S615345 A JPS615345 A JP S615345A JP 12128184 A JP12128184 A JP 12128184A JP 12128184 A JP12128184 A JP 12128184A JP S615345 A JPS615345 A JP S615345A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- circuit
- multiplier
- output
- multiplicand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/525—Multiplying only in serial-serial fashion, i.e. both operands being entered serially
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、乗算方法に係り、特にディジタル信号の乗算
を直列の１ビット加算により実現する直列乗算方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplication method, and particularly to a serial multiplication method in which multiplication of digital signals is realized by serial 1-bit addition.
近年ディジタル信号処理（Ｄ Ｓ Ｐ ： Ｄｉｇｉｔ
ａｌ Ｓｉｇｎａｌ Ｐｒｏｃｅｓｓｉｎｇ ）が盛ん
に行なわれており、また、このＤＳＰに於てディジタル
信号の乗算は、欠く事のできない重要な演算処理の１つ
である。In recent years, digital signal processing (DSP: Digit)
In addition, multiplication of digital signals is one of the indispensable and important arithmetic processes in this DSP.
例えば、音声信号処理におけるディジタルフィルタの計
算等に斯かる乗算処理が必要となる。For example, such multiplication processing is necessary for calculating digital filters in audio signal processing.
本発明は、この様なりＳＰに於ける乗算回路を極めて小
規模な回路で実現できる乗算方法を提案するものである
。The present invention proposes a multiplication method that allows the multiplication circuit in the SP to be realized with an extremely small-scale circuit.
第２図を参照して従来の乗算回路の動作を説明する。 The operation of the conventional multiplication circuit will be explained with reference to FIG.
ここでは、レジスタ７に蓄えられた被乗数Ａの並列デー
タを加算回路１０で順次加算することにより乗算処理を
行う。即ち、まずパラレル／シリアル変換回路８で変換
された乗数Ｂの各ビットの値に従って、被乗数Ａの値を
セレクタ９で選別し、次いで乗数Ｂの各桁のビットに対
応するこのセレクタ９の出力を加算回路１０で順次足し
込んで行く。Here, the multiplication process is performed by sequentially adding the parallel data of the multiplicand A stored in the register 7 in the adding circuit 10. That is, first, the value of the multiplicand A is selected by the selector 9 according to the value of each bit of the multiplier B converted by the parallel/serial conversion circuit 8, and then the output of this selector 9 corresponding to the bit of each digit of the multiplier B is selected. The addition circuit 10 sequentially adds the values.
尚、ここに病て、セレクタ９の出力を乗数Ｂの各桁のビ
ットに対応させるために、被乗数Ａは上記レジスタ７か
ら１ビットづつシフトされて順次加算回路１０に入力さ
れている。Incidentally, in order to make the output of the selector 9 correspond to the bits of each digit of the multiplier B, the multiplicand A is shifted one bit at a time from the register 7 and is sequentially input to the adder circuit 10.
上記従来の乗算回路では、加算回路１０が乗算出力Ｃの
ビット数と同じビット数の加算回路となっているため、
加算回路１０の回路構成が極めて大規模なものになって
いる。In the conventional multiplication circuit described above, since the addition circuit 10 is an addition circuit with the same number of bits as the number of bits of the multiplication output C,
The circuit configuration of the adder circuit 10 is extremely large-scale.
本発明ではこの大規模な加算回路を不要とした、新規な
乗算方法を提案するものである。The present invention proposes a new multiplication method that does not require this large-scale addition circuit.
本発明では、被乗数のシリアルデータを、乗数の各桁ビ
ットに対応して順次１ビットづつ積み上げ加算すること
により、上記従来技術の問題点を解決する。In the present invention, the problems of the prior art described above are solved by sequentially accumulating and adding the serial data of the multiplicand one bit at a time corresponding to each digit bit of the multiplier.
即ち、本発明では被乗数のビット数にほぼ等しい数の直
列接続された１ビット加算回路により、乗算処理を行な
えるよ・うにした。従って、上記の大規模な乗算回路を
不要とできる。That is, in the present invention, multiplication processing can be performed using 1-bit adder circuits connected in series, the number of which is approximately equal to the number of bits of the multiplicand. Therefore, the above-mentioned large-scale multiplication circuit can be eliminated.
第１図を参照して本発明の詳細な説明する。 The present invention will be described in detail with reference to FIG.
図中、１はパラレル／シリアル変換回路、２はレジスタ
、３〜５は１ビット加算回路、Ｇ１−Ｇ５はゲート回路
である。In the figure, 1 is a parallel/serial conversion circuit, 2 is a register, 3 to 5 are 1-bit adder circuits, and G1 to G5 are gate circuits.
まず、被乗数Ａをパラレル／シリアル変換回路１に入力
し、続いて、それをシリアルに読出す。First, the multiplicand A is input to the parallel/serial conversion circuit 1, and then it is read out serially.
一方、乗数Ｂはレジスタ７に並列のデータのまま一旦蓄
えられる。On the other hand, the multiplier B is temporarily stored in the register 7 as parallel data.
レジスタ２からの乗数Ｂの最下位ビットと、上記パラレ
ル／シリアル変換回路１の出力（ａ）はゲート回路Ｇ１
に入力され、乗数Ｂの最下位ビットが１である場合には
、被乗数の値がそのまま出力されて１ビット加算回路３
に入力されるが、乗数Ｂの最下位ピントが０の場合には
、ゲート回路Ｇ１の出力は、常に０となる。The least significant bit of the multiplier B from the register 2 and the output (a) of the parallel/serial conversion circuit 1 are connected to the gate circuit G1.
, and if the least significant bit of multiplier B is 1, the value of the multiplicand is output as is and the 1-bit addition circuit 3
However, when the lowest focus of the multiplier B is 0, the output of the gate circuit G1 is always 0.
一方、ゲート回路Ｇ２には上記パラレル／シリアル変換
回路１の出力＋ａ）のタイミングから１ビット遅れた被
乗数のシリアルデータ（ｂｌと乗数Ｂの最下位から２ビ
ット目のデータが入力され、前記と同様にその出力を１
ビット加算回路３に入力する。On the other hand, the serial data of the multiplicand (bl and the second bit from the lowest bit of the multiplier B) which is delayed by 1 bit from the timing of the output +a) of the parallel/serial conversion circuit 1 is input to the gate circuit G2, and the same as above. The output is 1
Input to bit adder circuit 3.
ここに於て、１ビット遅れたパラレル／シリアル変換回
路１の出力（ｂ）を採用する理由は、ゲート回路Ｇ２の
出力がゲート回路Ｇ１の出力に比べて１ビットシフトし
ていなければならない為であり、従来回路の加算に於て
乗数の出力を１ビットづつシフトして加算していた事に
対応する。Here, the reason why the output (b) of the parallel/serial conversion circuit 1 delayed by 1 bit is adopted is that the output of the gate circuit G2 must be shifted by 1 bit compared to the output of the gate circuit G1. This corresponds to the fact that in addition in conventional circuits, the output of the multiplier is shifted one bit at a time and added.
上記の処理により、１ビット加算回路３からは、乗数Ｂ
の下位２ビットにより加算すべきか、０にすべきかを判
定された被乗数Ａと当該被乗数Ａを１ビット遅延させた
ものの加算結果がシリアルに出力されることとなる。Through the above processing, the 1-bit addition circuit 3 outputs the multiplier B
The result of adding the multiplicand A, for which it is determined whether to add or set it to 0 based on the lower two bits of the multiplicand A and the multiplicand A delayed by 1 bit, is serially output.
次いで、この１ビット加算回路３の出力は、１ビット加
算回路４に於て、ゲート回路Ｇ３の出力左加算される。Next, the output of this 1-bit addition circuit 3 is added to the left of the output of gate circuit G3 in 1-bit addition circuit 4.
尚、ゲート回路Ｇ３には、前記ゲート回路Ｇｌ、Ｇ２と
同様に、２ビット遅延させたパラレル／シリアル変換回
路１の出力（Ｃ）と乗数Ｂの最下位から３ビット目のデ
ータとが入力されている。Note that, like the gate circuits Gl and G2, the output (C) of the parallel/serial conversion circuit 1 delayed by 2 bits and the third bit data from the lowest bit of the multiplier B are input to the gate circuit G3. ing.
同様に、１ビット加算回路５には、１ビット加算回路４
の出力と、ゲート回路Ｇ４を介した乗数Ｂの最下位から
４ビット目のデータに対応したパラレル／シリアル変換
回路１の出力ｆｄｌが入力され、その出力端６からは、
例えば４ビットの乗数による直列乗算結果Ｃが出力され
る。Similarly, the 1-bit adder circuit 5 includes the 1-bit adder circuit 4
and the output fdl of the parallel/serial conversion circuit 1 corresponding to the fourth bit from the lowest bit of the multiplier B via the gate circuit G4 are input, and from the output terminal 6,
For example, a serial multiplication result C using a 4-bit multiplier is output.
具体的に被乗数Ａ＝１１０１、乗数Ｂ＝１０１０の場合
について、各１ビット加算回路１〜４の入出力データを
図中の参照記号イ〜トに対応させて以下に示す。Specifically, for the case where the multiplicand A=1101 and the multiplier B=1010, the input/output data of each of the 1-bit adder circuits 1 to 4 is shown below, corresponding to reference symbols I to 4 in the figure.
被乗数（シリアルデータ）：ｔｏｉ１
イ： （対応乗数ビット０） ００００口： （対
応乗数ビット１） １０１１ハ：
０１０１に
： （対応乗数ビットＯ） ００００ホ：
０１０１１
へ： （対応乗数ビット１） ｌ Ｏ１１ト
： ｏｔｏ
ｏｏｏｏｉ上記具体例からも明らかであるように、本発
明によれば、１１０１＊１０１０＝１０００００１０と
云う４ビット乗数の乗算処理を直列に接続された３ＩＩ
Ｍの１ビット加算回路により行うことができる。Multiplicand (serial data): toi1 A: (Corresponding multiplier bit 0) 0000 unit: (Corresponding multiplier bit 1) 1011 C:
to 0101: (corresponding multiplier bit O) 0000 ho:
To 01011: (corresponding multiplier bit 1) l O11 to: oto
ooooiAs is clear from the above specific example, according to the present invention, the multiplication process of the 4-bit multiplier 1101*1010=10000010 is performed using 3II connected in series.
This can be performed using M 1-bit adder circuits.
尚、上記実施例にでは４ビットの乗数による演算につい
て説明をしたが、本発明の適用はこれに限られるもので
はない。即ち、適宜乗数のビット数に応じて直列接続さ
れる１ビット加算回路等の数を変更し、演算を行うこと
が出来るものである。Incidentally, in the above embodiment, an operation using a 4-bit multiplier was explained, but the application of the present invention is not limited to this. That is, it is possible to perform calculations by appropriately changing the number of 1-bit adder circuits connected in series according to the number of bits of the multiplier.
また、予め多数の１ビット加算回路を直列に接続し、所
定段の加算回路出力を取り出すことによっても同様に所
定の乗算処理を行わせることができる。Further, a predetermined multiplication process can be similarly performed by connecting a large number of 1-bit adder circuits in series in advance and taking out the output of the adder circuits at a predetermined stage.
以上本発明によれば、従来必要であった大規模の加算回
路を不要とし、小規模の１ビット加算回路を直列に接続
して乗算を行うことができるため、その回路規模を極め
て小さくすることができる。As described above, according to the present invention, the large-scale adder circuit that was conventionally required is not required, and multiplication can be performed by connecting small-scale 1-bit adder circuits in series, so that the circuit scale can be made extremely small. Can be done.
尚、本発明に於ては、被乗数のビット数及び乗数のビッ
ト数の和に対応した数の信号処理サイクルが必要となる
ため、従来の演算方式に比べて若干演算処理時間が多く
なることがある。しかしながら、特に高速演算処理を要
求されず、回路規模の縮小の要請の強い領域、例えば音
声信号処理の応用に於けるチップのＬＳＩを製造する場
合等に本発明の適用が特に有効である。Note that in the present invention, the number of signal processing cycles corresponding to the sum of the number of bits of the multiplicand and the number of bits of the multiplier is required, so the calculation processing time may be slightly longer than that of conventional calculation methods. be. However, the application of the present invention is particularly effective in areas where high-speed arithmetic processing is not required and there is a strong demand for circuit scale reduction, such as when manufacturing LSI chips for audio signal processing applications.
第１図は本発明による直列乗算を行うための一実施例を
、第２図は従来の乗算回路を、それぞれ示す。
図中、１．８はパラレル／シリアル変換回路を、２．７
はレジスタを、３〜５は１ビット加算回路を、６１〜Ｇ
４はゲート回路を、９はセレクタを、１０は加算回路を
表す。FIG. 1 shows an embodiment for performing serial multiplication according to the present invention, and FIG. 2 shows a conventional multiplication circuit. In the figure, 1.8 is the parallel/serial conversion circuit, 2.7
is a register, 3 to 5 is a 1-bit addition circuit, 61 to G
4 represents a gate circuit, 9 represents a selector, and 10 represents an adder circuit.
Claims (1)
て順次１ビットづつ積み上げ加算することを特徴とする
直列乗算方法。A serial multiplication method characterized in that serial data of a multiplicand is sequentially accumulated and added one bit at a time corresponding to each digit bit of the multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12128184A JPS615345A (en) | 1984-06-13 | 1984-06-13 | Serial multiplication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12128184A JPS615345A (en) | 1984-06-13 | 1984-06-13 | Serial multiplication method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615345A true JPS615345A (en) | 1986-01-11 |
Family
ID=14807368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12128184A Pending JPS615345A (en) | 1984-06-13 | 1984-06-13 | Serial multiplication method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615345A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61236340A (en) * | 1985-04-10 | 1986-10-21 | Matsushita Electric Ind Co Ltd | Motor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5327337A (en) * | 1976-08-26 | 1978-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Pipeline multiplier |
| JPS5373042A (en) * | 1976-12-13 | 1978-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Pipeline multiplier |
| JPS5447539A (en) * | 1977-09-22 | 1979-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Digital binary multiplier circuit |
-
1984
- 1984-06-13 JP JP12128184A patent/JPS615345A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5327337A (en) * | 1976-08-26 | 1978-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Pipeline multiplier |
| JPS5373042A (en) * | 1976-12-13 | 1978-06-29 | Nippon Telegr & Teleph Corp <Ntt> | Pipeline multiplier |
| JPS5447539A (en) * | 1977-09-22 | 1979-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Digital binary multiplier circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61236340A (en) * | 1985-04-10 | 1986-10-21 | Matsushita Electric Ind Co Ltd | Motor |
| JPH0510022B2 (en) * | 1985-04-10 | 1993-02-08 | Matsushita Electric Ind Co Ltd |
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