JPS6137198U - Unmounted area recognition device for variable capacity memory - Google Patents

Unmounted area recognition device for variable capacity memory

Info

Publication number
JPS6137198U
JPS6137198U JP12174584U JP12174584U JPS6137198U JP S6137198 U JPS6137198 U JP S6137198U JP 12174584 U JP12174584 U JP 12174584U JP 12174584 U JP12174584 U JP 12174584U JP S6137198 U JPS6137198 U JP S6137198U
Authority
JP
Japan
Prior art keywords
memory
variable capacity
sent
recognition device
capacity memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12174584U
Other languages
Japanese (ja)
Inventor
栄一 瀬戸
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP12174584U priority Critical patent/JPS6137198U/en
Publication of JPS6137198U publication Critical patent/JPS6137198U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロック図、第２図
はメモリ選択制御部にＲＯＭ （ＰＬＡ）を用いて構成
した構成説明図、第３図はアドレス上位ビットと選択さ
れる対応バンクとの説明図、第４図はメモリ選択制御部
のフローチャートである。 ＣＰＵ・・・中央処理装置、ＭＳＣ・・・メモリ選択制
御部、ＣＳＷ・・・メモリコンフィギュレーションスイ
ッチ情報部、ＭＢＫ・・・メモリバンク、ＵＢＣ・・・
異常．処理部。Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is an explanatory diagram of a configuration using a ROM (PLA) in the memory selection control section, and Fig. 3 shows the upper bits of the address and the corresponding bank selected. FIG. 4 is a flowchart of the memory selection control section. CPU...central processing unit, MSC...memory selection control section, CSW...memory configuration switch information section, MBK...memory bank, UBC...
Abnormal. processing section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリコンフイギュレーションスイッチ情報ト中央処理
装置から出力されるアドレス情報が入力されるメモリ選
択制御部を有し、このメモリ選択制御部は前記両情報か
らメモリ実装容量を認識して不実装領域があるかどうか
をｉ断し、その領域がないと判断したときにはメモリバ
ンクセレクト信号を送出し、その領域があると判断した
ときには前記バンクセレクト信号を送出しないで中央処
理装置に非選択信号（トラップ信号）を供給したことを
特徴とする可変容量メモリにおける不実装領域認識装置
。The memory configuration switch information has a memory selection control section into which address information output from the central processing unit is input, and this memory selection control section recognizes the memory mounting capacity from both of the above information and determines whether the unmounted area is If it is determined that the area does not exist, a memory bank select signal is sent, and if it is determined that the area exists, the bank select signal is not sent and a non-selection signal (trap signal) is sent to the central processing unit. ) in a variable capacity memory.
JP12174584U 1984-08-08 1984-08-08 Unmounted area recognition device for variable capacity memory Pending JPS6137198U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12174584U JPS6137198U (en) 1984-08-08 1984-08-08 Unmounted area recognition device for variable capacity memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12174584U JPS6137198U (en) 1984-08-08 1984-08-08 Unmounted area recognition device for variable capacity memory

Publications (1)

Publication Number Publication Date
JPS6137198U true JPS6137198U (en) 1986-03-07

Family

ID=30680523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12174584U Pending JPS6137198U (en) 1984-08-08 1984-08-08 Unmounted area recognition device for variable capacity memory

Country Status (1)

Country Link
JP (1) JPS6137198U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372533A (en) * 1976-12-10 1978-06-28 Sharp Corp Block selecting device for memory card
JPS5496935A (en) * 1978-01-17 1979-07-31 Nec Corp Memory module
JPS55153188A (en) * 1979-05-17 1980-11-28 Mitsubishi Electric Corp Memory unit
JPS5922150A (en) * 1982-07-28 1984-02-04 Fanuc Ltd Memory control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372533A (en) * 1976-12-10 1978-06-28 Sharp Corp Block selecting device for memory card
JPS5496935A (en) * 1978-01-17 1979-07-31 Nec Corp Memory module
JPS55153188A (en) * 1979-05-17 1980-11-28 Mitsubishi Electric Corp Memory unit
JPS5922150A (en) * 1982-07-28 1984-02-04 Fanuc Ltd Memory control system

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