JPS6132560A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6132560A JPS6132560A JP15434884A JP15434884A JPS6132560A JP S6132560 A JPS6132560 A JP S6132560A JP 15434884 A JP15434884 A JP 15434884A JP 15434884 A JP15434884 A JP 15434884A JP S6132560 A JPS6132560 A JP S6132560A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- film lead
- film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は積層にした半導体素子間の電極リードを簡便に
接続する方法に関するものでろる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for easily connecting electrode leads between stacked semiconductor elements.
従来例の構成とその問題点
近年、半導体素子を多数個用いるＩＣカードやデジタル
回路等の開発が促進されてきている。これらは、いずれ
も多数個のＩＣ，ＬＳＩを一定の面積を有する基板に高
密度に搭載しなければならない。複数個のＩＣ，ＬＳＩ
を搭載する場合には一般に、入力端子もしくは出力端子
が共通である場合が多く、しかも、これらの端子の接続
距離は応答速度や使用周波数等の問題から、できる限シ
短かくする必要がある。2. Description of the Related Art Structures of Conventional Examples and Their Problems In recent years, the development of IC cards, digital circuits, etc. that use a large number of semiconductor elements has been promoted. All of these require a large number of ICs and LSIs to be mounted at high density on a substrate having a certain area. Multiple ICs, LSIs
In general, when a device is equipped with a device, the input terminal or output terminal is common, and the connection distance between these terminals must be kept as short as possible due to issues such as response speed and operating frequency.
従来の接続方法においては、ＤＩＬやフラットパレケー
ジ型のＩＣ，ＬＳＩを用パ、これらのリード端子を半田
づけし、プリント配線基板上に平面的に搭載していた。In conventional connection methods, DIL and flat package type ICs and LSIs are used, their lead terminals are soldered, and the ICs and LSIs are mounted flatly on a printed wiring board.
この様な搭載方法においては次の様な問題が４あった。In this mounting method, there were four problems as follows.
ＩＣ，ＬＳＩを一度バンケージングしたものをプリント
配線基板上に半田づけするから、どうしても、半田づけ
やワイヤボンディング接続等の接続箇所が増えたり、半
導体素子の電極から、次の結線すべき半導体素子の電極
までの距離が著しるしく長くなるばかシか、実装する面
積が増大する結果になっていた。これら接続箇所の増大
は信頼性を低下さすばかシでなく製造コストを高くした
リ、全体の回路としての電気的な応答速度の低下や、高
周波使用領域での波形の歪やリークが発生し、著しるし
く実用的価値を低下さすものであった０
発明の目的
本発明はこのような従来の問題に鑑み、配線距離が著し
るしく短かく、接続箇所の少ない、信頼性が高く、安価
な接続方法を提供することを目的とする。Because ICs and LSIs are soldered onto a printed wiring board once they have been buncaged, the number of connections such as soldering and wire bonding increases, and connections between the electrodes of a semiconductor element and the next semiconductor element to be connected are inevitably increased. Either the distance to the electrode becomes significantly longer, or the mounting area increases. The increase in the number of connection points not only reduces reliability but also increases manufacturing costs, reduces the electrical response speed of the entire circuit, and causes waveform distortion and leakage in the high frequency range. Purpose of the Invention In view of these conventional problems, the present invention has been developed to provide a highly reliable and inexpensive method with significantly short wiring distance and fewer connection points. The purpose is to provide a connection method.
発明の構成
本発明は半導体素子の電極に孔もしくは切欠きを有する
フィルムリードを接続し、この半導体素子を積層せしめ
、前記フィルムリードの任意の孔もしくは切欠き同志を
、半導体素子の厚み方向に最短距離で接続せんとする構
成である０実施例の説明
第１の実施例を第１図で説明する０
半導体素子１，１′の電極２，２′に接合されたフィル
ムリード群３．３’、４．４’、５には半導体素子の端
部附近に孔６を形成しである。例えば半導体素子１の下
層に半導体素子１′が載置され半導体素子１のフィルム
リード３の孔６と半導体素子１′のフィルムリード３′
の孔６とは金属で構成された導電材７で貫通され（ｂ）
図に示される如く半田づけ８，８′が固定されるもので
ある。Structure of the Invention The present invention connects a film lead having a hole or notch to an electrode of a semiconductor element, stacks the semiconductor elements, and connects arbitrary holes or notches of the film lead to each other at the shortest distance in the thickness direction of the semiconductor element. Description of Embodiment A first embodiment is explained with reference to FIG. 1. A group of film leads 3, 3' joined to electrodes 2, 2' of semiconductor elements 1, 1'. , 4.4', and 5 have holes 6 formed near the ends of the semiconductor element. For example, the semiconductor element 1' is placed on the lower layer of the semiconductor element 1, and the hole 6 of the film lead 3 of the semiconductor element 1 and the film lead 3' of the semiconductor element 1' are connected to each other.
The hole 6 is penetrated by a conductive material 7 made of metal (b).
As shown in the figure, solders 8, 8' are fixed.
フィルムリード３，３′の場合には、フィルムリード３
，３′が相対する構成であるが、フィルムリード４と４
′の孔は相対していす、フィルムリード６と４′が相対
する様にフィルムリード４′を加工しである。この様な
構成であれば、自由に接続位置を換えることができ、フ
ィルムリード５と４′の孔６は導電材７′で貫通され、
これ捷た半田づけ固定されるものである。In the case of film leads 3 and 3', film lead 3
, 3' are opposite to each other, but the film leads 4 and 4 are opposite to each other.
The holes ' are opposite to each other, and the film leads 4' are machined so that the film leads 6 and 4' are opposite to each other. With such a configuration, the connection position can be changed freely, and the holes 6 of the film leads 5 and 4' are penetrated by the conductive material 7'.
This is fixed by soldering.
この様な構成であれば、例えば半導体素子からフィルム
リードの孔までの長さは、わずか５０〜２ｏＯμｍ、半
導体素子の厚さを２００〜４００μｍと仮定すれば、半
導体素子１の電極２がら半導体素子１′の電極２′まで
の接続距離は叢大でもＳＯＯμｍにしかならない。また
、実装体の平面積は、半導体素子の寸法より最大４００
μｍ大きくなるばかりか、厚さ方向も半導体素子の厚み
で制限され、著しるしく薄型、小型に搭載できるもので
ある。With such a configuration, for example, assuming that the length from the semiconductor element to the hole of the film lead is only 50 to 200 μm, and the thickness of the semiconductor element is 200 to 400 μm, the semiconductor element can be removed from the electrode 2 of the semiconductor element 1. The connection distance between electrode 1' and electrode 2' is only SOO μm even if the cluster is large. Furthermore, the planar area of the mounting body is up to 400 mm larger than the dimensions of the semiconductor element.
Not only does it increase in μm, but the thickness direction is also limited by the thickness of the semiconductor element, and it can be mounted in a significantly thinner and smaller size.
次に、半導体素子の電極にフィルムリードを接続する方
法について第２図でのべる。Next, a method for connecting film leads to electrodes of a semiconductor element will be described with reference to FIG.
可撓性フィルム１０上に形成されたフィルムリード３は
、半導体素子１の電極２と対応する如くら
設は乍、半導体素子１の端部附近に孔６を形成しである
。先ず、半導体素子１の電極２とフィルムリード３とを
位置合せし、ボンディングツール１１で加圧・加熱（第
２図ａ）Ｌ、電極２とフィルムリード３とを接合し、電
気的検査を行ない、破線１２の位置（第２図ｂ）で切断
し、フィルムリード３の孔に導電材７，７′を挿入、固
定するものである。また導電材を挿入、固定するだめの
前記フィルムリードに形成する孔は、穴に限定されるも
のではなく、第３図に示す様に、切欠き１３ 、１４を
設けた形状であっても良いし、孔も円形と限定するもの
ではなく、六角形、四角形等を選択でき人家のでもスへ
次に他の実施例を第４図で説明する。第４図の構成は、
積層した半導体素子の電極間の自由な接続方法に関する
もので、半導体素子１のフィルムリード３には２箇所の
孔６，６′を有し、孔６は半導体素子１′のフィルムリ
ード３′の孔６と接続され、フィルムリード３の孔６′
は半導体素子１″のフィルムリード３″の孔６′と導電
側７で接続される。また半導体素子１のフィルムリード
４の孔と半導体素子１′のフィルムリード４′の孔およ
び半導体素子１＃のフィルムリード４″の孔とは導電材
７′で連続的に接続されている。The film lead 3 formed on the flexible film 10 is arranged so as to correspond to the electrode 2 of the semiconductor element 1, and has a hole 6 formed near the end of the semiconductor element 1. First, the electrode 2 of the semiconductor element 1 and the film lead 3 are aligned, and the bonding tool 11 is used to apply pressure and heat (FIG. 2a) L to bond the electrode 2 and the film lead 3, and an electrical test is performed. , the conductive material 7, 7' is inserted into the hole of the film lead 3 and fixed. Further, the holes formed in the film lead through which the conductive material is inserted and fixed are not limited to holes, but may have a shape with cutouts 13 and 14 as shown in FIG. However, the hole is not limited to a circular shape, but may be hexagonal, quadrangular, etc., and can be used for people's houses.Next, another embodiment will be described with reference to FIG. 4. The configuration of Figure 4 is
This relates to a method of free connection between electrodes of stacked semiconductor elements, and the film lead 3 of the semiconductor element 1 has two holes 6 and 6', and the hole 6 is connected to the film lead 3' of the semiconductor element 1'. Connected to hole 6, hole 6' of film lead 3
is connected to the hole 6' of the film lead 3'' of the semiconductor element 1'' at the conductive side 7. Further, the hole in the film lead 4 of the semiconductor element 1, the hole in the film lead 4' of the semiconductor element 1', and the hole in the film lead 4'' of the semiconductor element 1# are continuously connected by a conductive material 7'.
同様に、フィルムリード１４の孔とフィルムリード１４
′の孔が接続され、フィルムリード１４″の孔は別のフ
ィルムリードの孔に接続されるものである。Similarly, the holes in the film lead 14 and the film lead 14
The holes in the film lead 14'' are connected to the holes in another film lead.
また、フィルムリードの孔同志を接続するための導電材
は、これまで述べてきた如く、全体が導を有する一体形
状のものでも良いし、第６図すの如く、導電体２２′が
絶縁体２３．２３’で覆われ、任意の部分で前記導電体
２２′に継続した部分が露出し導電領域２２を形成した
構成であっても良い。第５図すの構成で導電領域と絶縁
領域が入れ換った構成でも本発明の効果を期待できる。Further, the conductive material for connecting the holes of the film lead may be of an integral shape having conductivity as a whole as described above, or as shown in Fig. 6, the conductive material 22' may be an insulator. 23 and 23', and a portion continuing to the conductor 22' may be exposed at an arbitrary portion to form the conductive region 22. The effects of the present invention can also be expected in the structure shown in FIG. 5, in which the conductive region and the insulating region are interchanged.
この様な構成であれば、第４図に示す導電材の如く、途
中で切断する必要がなく、フィルムリードの孔に連続し
て挿入し、固定できるものである。With such a structure, unlike the conductive material shown in FIG. 4, there is no need to cut the conductive material in the middle, and it can be continuously inserted into the hole of the film lead and fixed.
次に他の実施例を示す。第６図において、積層にした半
導体素子１．１’、１″′の各々の間にポリイミド、エ
ポキシガラス、セラミック等の絶縁体もしくは熱伝導材
料３０．３０’を介在させたものである。この様な構成
により、各々の半導体素子間を絶縁し、かつ固定できる
と共に、放熱効果を高めることができるものである。図
においては各々の半導体素子の表面が、一定方向にある
が、第７図は半導体素子の同一面同志を対向させた構成
である。Next, another example will be shown. In FIG. 6, an insulator or heat conductive material 30, 30' such as polyimide, epoxy glass, ceramic, etc. is interposed between each of the stacked semiconductor elements 1.1', 1''. With various configurations, it is possible to insulate and fix each semiconductor element and to improve the heat dissipation effect.In the figure, the surface of each semiconductor element is in a fixed direction, but as shown in Fig. 7. is a configuration in which semiconductor elements on the same surface are opposed to each other.
発明の効果
■ 本発明は、半導体素子の電極から孔もしくは切欠き
を有するフィルムリードを延在させ、前記半導体素子を
積層させ、前記フィルムリードの孔もしくは切欠きに導
電材を挿入、固定し、これにより各半導体素子間の電気
的接続を行なわしめるものである。したがって、接続距
離が短かいため高い周波数で駆動するもしくは応答速度
の早いＩＣ，ＬＳＩに著しるしい効果を期待できるもの
である。Effects of the Invention ■ The present invention extends a film lead having a hole or notch from an electrode of a semiconductor element, stacks the semiconductor element, inserts and fixes a conductive material into the hole or notch of the film lead, This establishes electrical connection between each semiconductor element. Therefore, since the connection distance is short, a remarkable effect can be expected on ICs and LSIs that are driven at high frequencies or have fast response speeds.
■ 捷た、半導体素子間の接続が従来のフラットバック
型パッケージだと、６箇所必要だが、本発明の構成では
４箇所で良いから、接続の信頼性も高いものである。■ In the conventional flat back package, six connections between the twisted semiconductor elements are required, but in the configuration of the present invention, only four connections are required, so the reliability of the connection is also high.
■ 更に、本発明の構成では半導体素子のチップ寸法に
近い領域で相互の接続を行なわしめるので、いわゆるチ
ップサイズ実装が実現でき、著じるしく小型で薄型の半
導体装置を実用化で明では、半導体素子のチップ側面領
域でフィルムリード同志の接続ができるので、前記プリ
ント配線基板を必要としな・い。このために半導体装置
の製造コストを低減できるものである。Furthermore, in the configuration of the present invention, mutual connections are made in an area close to the chip size of the semiconductor element, so it is possible to realize so-called chip size mounting, and it is possible to realize a significantly smaller and thinner semiconductor device. Since the film leads can be connected to each other in the chip side area of the semiconductor element, the printed wiring board is not required. Therefore, the manufacturing cost of the semiconductor device can be reduced.
■ 本発明では半導体素子の表面から延在したフィルム
リードを前記半導体素子の積層方向に接続するので、無
数の半導体素子を積層し、接続を行なわしめることがで
きるから、小型で高密度の半導体装置を実現できるもの
である。■ In the present invention, since the film leads extending from the surface of the semiconductor element are connected in the stacking direction of the semiconductor elements, it is possible to stack and connect an infinite number of semiconductor elements. It is possible to realize this.
第１図（−） 、 （ｂ）は本発明の一実施例の構成を
示す斜視図および断面図、第２図（ａ）〜（ｃ）は本発
明の製造工程を示す断面図、第３図はフィルムリードの
平面図、第４図は他の実施例の構成を示す斜視図、第６
図（ａ）、■）は導電材の他の実施例を示す斜視図、第
６図、第７図は本発明の他の実施例を示す断面図である
。
１・・−・−半導体素子、２・・・・・・電極、３・・
・・・・フィルムリード、６・・・・・・孔もしくは切
欠き、７・・・・・・導電材、３ｏ・・・・・・絶縁材
または放熱材。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図 （α）
第２図 （（Ｌ）
ｌ
（１負）
第３図FIGS. 1(-) and 1(b) are a perspective view and a sectional view showing the configuration of an embodiment of the present invention, FIGS. 2(a) to (c) are sectional views showing the manufacturing process of the present invention, and FIG. The figure is a plan view of the film lead, Figure 4 is a perspective view showing the configuration of another embodiment, and Figure 6 is a plan view of the film lead.
Figures (a) and 2) are perspective views showing other embodiments of the conductive material, and Figures 6 and 7 are sectional views showing other embodiments of the present invention. 1...-Semiconductor element, 2... Electrode, 3...
... Film lead, 6 ... Hole or notch, 7 ... Conductive material, 3o ... Insulating material or heat dissipation material. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (α) Figure 2 ((L) l (1 negative) Figure 3
Claims (2)
部外へ延在し任意の位置に孔または切欠きを設けたリー
ド群を有する前記半導体素子が複数個積層され、前記リ
ード群の孔または切欠きに導電材が積層方向に挿入、接
合されたことを特徴とする半導体装置。(1) A plurality of the semiconductor elements having a lead group connected to an electrode of the semiconductor element, extending outside the end of the semiconductor element, and provided with a hole or notch at an arbitrary position are stacked, Alternatively, a semiconductor device characterized in that a conductive material is inserted and bonded to the notch in the stacking direction.
挿入されていることを特徴とする特許請求の範囲第１項
記載の半導体装置。(2) The semiconductor device according to claim 1, wherein an insulator or a heat dissipating material is inserted between the stacked semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15434884A JPS6132560A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15434884A JPS6132560A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132560A true JPS6132560A (en) | 1986-02-15 |
Family
ID=15582195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15434884A Pending JPS6132560A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132560A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
| WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59138355A (en) * | 1983-01-27 | 1984-08-08 | Sanyo Electric Co Ltd | Multi-layer mounting structure of memory device |
-
1984
- 1984-07-25 JP JP15434884A patent/JPS6132560A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59138355A (en) * | 1983-01-27 | 1984-08-08 | Sanyo Electric Co Ltd | Multi-layer mounting structure of memory device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
| WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| US5463253A (en) * | 1990-03-15 | 1995-10-31 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
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