JPS5896756A - Mounting method of multichip package - Google Patents
Mounting method of multichip packageInfo
- Publication number
- JPS5896756A JPS5896756A JP19442881A JP19442881A JPS5896756A JP S5896756 A JPS5896756 A JP S5896756A JP 19442881 A JP19442881 A JP 19442881A JP 19442881 A JP19442881 A JP 19442881A JP S5896756 A JPS5896756 A JP S5896756A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- holes
- chip package
- chip
- cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は、配線括板上に複数個の亀子的機能要素をチッ
プ状態で実装し、全体を気密封止すべくキャップ等の基
体を塔載したマルチチップパッケージの実装方法に関す
るものである。[Detailed Description of the Invention] Technical field to which the invention pertains The present invention is directed to a circuit board in which a plurality of functional elements are mounted in the form of chips on a wiring board, and a base such as a cap is mounted on the board to hermetically seal the whole. The present invention relates to a method for mounting a multi-chip package.
従来技術とその問題点
近年、電子機器の小型、軽量化、高速化、高信頼性化の
要求が著しく高まって来てお・リ、それ等の要求を満足
すべく例えばアルミナセラミック痛板上に導体ペースト
及び絶縁体ペーストを印刷乾燥、焼成を繰り返し、積層
する事により特定の回路機能を持たせる所謂厚膜配線基
板法、あるいはグリーンシート上に導体ペーストと絶縁
体ペーストを乾燥状態で繰り返し積層した後、還元雰囲
気炉で同時焼成する事に依り特定の回路機能を持たせる
所謂る印刷積層メタライズドセラミック基板法、あるい
はグリーンシートに金型パンチング等に上り通孔を形成
し、その上に導体ペーストを印刷、乾燥し、それ等のグ
リーンシートを複数枚重ね合わせ加圧した後、還元雰囲
気炉で同時焼成する事に依り特定の回路機能を持たせる
所謂るシート積層法等により形成］一た高密度配線基板
上にＩＣチップ等のチップ部品を複数個実装し、全体を
気密封止する所謂るマルチチップパッケージング技術が
開発されつつある，、
この様なマルチチップパッケージの外観構造としては、
第１図に示す如く高密度配線基板１−１及び全体を気密
封止しすべく配線基板１−１上に例えばハンダ付けある
いはウェルディング４によシ支持固定されたキャップ等
の基体１−２、及び配線基板１−１の周辺部に例えばハ
ンダ付けあるいは銀ロー付は等により形成された入出力
端子１一３から構成されている。図において１−４は電
子的機能要素であるＩＣ−チップを、１−５ｉｄ同じく
コンデンサーチップを示しており、またｌ−６は、それ
等のＩＣチップ１−５と配線基板ｌ−１との電気的接続
を形成する例えばＡｌ１線等のワイヤーを示している。Conventional technology and its problems In recent years, the demand for electronic devices to be smaller, lighter, faster, and more reliable has increased significantly.In order to satisfy these demands, for example, alumina ceramic plates have been The so-called thick film wiring board method is used to give a specific circuit function by repeatedly printing, drying, and baking conductive paste and insulating paste, and laminating them, or by repeatedly laminating conductive paste and insulating paste in a dry state on a green sheet. After that, we use the so-called printed laminated metallized ceramic substrate method to give specific circuit functions by co-firing in a reducing atmosphere furnace, or we form through holes in the green sheet by punching a mold, and then apply conductive paste on top of it. It is formed by the so-called sheet lamination method, etc., which prints, dries, stacks multiple green sheets, pressurizes them, and then simultaneously fires them in a reducing atmosphere furnace to give them a specific circuit function. A so-called multi-chip packaging technology is being developed in which multiple chip components such as IC chips are mounted on a wiring board and the whole is hermetically sealed.The external structure of such a multi-chip package is as follows.
As shown in FIG. 1, a high-density wiring board 1-1 and a base 1-2 such as a cap are supported and fixed on the wiring board 1-1 by, for example, soldering or welding 4 in order to hermetically seal the whole. , and input/output terminals 1-3 formed on the periphery of the wiring board 1-1 by, for example, soldering or silver brazing. In the figure, 1-4 shows an IC chip which is an electronic functional element, 1-5id also shows a capacitor chip, and l-6 shows the connection between the IC chip 1-5 and the wiring board l-1. A wire, for example an Al1 wire, is shown forming the electrical connection.
この様なマルチチップパッケージを複数個使用１−で１
つのシステムを形成するわけであるが、この様な場合、
従来８２図（（ａ）は平面図、（ｂ）は側面図）に示す
如く所謂るプリント配線基板２−４上に第１図に示すマ
ルチチップパッケージの入出力端子１−３を折シ曲げ成
形し、その入出力端子２−３を前記プリント配線基板２
−１のスルーホール内に挿入し、例えばハンダ付け２−
５等で支持固定する事によりマルチチップパッケージを
複数個プリント配線基板上に実装し、各々のマルチチッ
プパッケージの眠気的接続全形成する事により１つのシ
ステムを形成していた。Using multiple multi-chip packages like this 1-in-1
However, in such a case,
Conventionally, as shown in Fig. 82 ((a) is a plan view, (b) is a side view), input/output terminals 1-3 of a multi-chip package shown in Fig. 1 are bent onto a so-called printed wiring board 2-4. The input/output terminals 2-3 are molded onto the printed wiring board 2.
-1 into the through hole, for example, solder 2-
A plurality of multi-chip packages are mounted on a printed wiring board by supporting and fixing them with 5 etc., and one system is formed by forming all the connections of each multi-chip package.
ここに於で、２−１はマルチチップパッケージの配線基
板、２−２は気密封止用のキャップ等の基体をそれぞれ
示しているのしかしながらこの様な方法では、形成すべ
き１つのシステムを組み込む筐体等の基体の平面的な面
積が前記マルチチップパッケージ（第１図）を複数個塔
載できる程大きな面積を有する場合は問題はないが、前
記筐体等の基体の平面的な面積がマルチチップパッケー
ジ（第１図）の平面的な面積とほぼ同等な面積しか存在
しない場合には、その筐体等の基体内に複数個のマルチ
チップパッケージを実装する事は、はなはだ困難であ９
成すすべも無かった。Here, 2-1 indicates a wiring board for a multi-chip package, and 2-2 indicates a base such as a hermetic sealing cap. However, in this method, only one system to be formed is incorporated. There is no problem if the planar area of the base such as the casing is large enough to mount a plurality of the multi-chip packages (Fig. 1), but if the planar area of the base such as the casing is If there is only an area that is approximately the same as the planar area of a multi-chip package (Figure 1), it is extremely difficult to mount multiple multi-chip packages within a base such as a casing9.
There was nothing I could do.
発明の目的
本発明はこの様な事情を考慮して成されたものであり、
その目的とする所は、平面的な面積の小さな筐体等の木
本に効率良く故多くのマルチチップパッケージを実装す
る方法を提供する事に有る。Purpose of the Invention The present invention has been made in consideration of such circumstances,
The purpose is to provide a method for efficiently mounting a large number of multi-chip packages in a wooden case or the like with a small planar area.
尚、本発明は前記筐体等の基体の平面的な面積を有する
千面さ垂直な方向には、酌記マルチチップパッケージの
配線基板１−１の厚さとキャップ等の基体１−２の昼さ
の和の数倍のスペースが存在する様な場合に特に有効で
ある。In addition, in the present invention, the thickness of the wiring board 1-1 of the multi-chip package and the thickness of the base 1-2 such as the cap are determined in the direction perpendicular to the planar area of the base such as the casing. This is particularly effective when there is a space several times the sum of the numbers.
発明の実施例
以下、本発明の一実施例を図面を参照しながら説明する
。第３ ＩＱ （（ａ）平面図、（ｂ）側面図）は１本
発明によるマルチチップパッケージの構造を示すもので
あり、３−１は山：予約機能要素であるＩＣチップ等の
チップ部品は支持固定する配線基板、３−２はそれらの
チップ部品全体を気密封止すべく配線基板３−１上に・
・ンダ付けあるいはウェルディング等の手法に上り形：
１ｚされたキャップ等の基体を示す。神た３−３は、マ
ルチチツプノくツケージのチップ部品搭載面に平行に外
向きに・・ンダ付けあるいは銀ロー ３−５付は等の手
法により形成された入出力端子を示すものである。布た
３−４は本発明による気密封止すべく形成さｎたキャッ
プ等の基体３−２の周辺部の配線基板３−１に形成され
た少なくとも２ケ所以上（図においては４ケ所）の通孔
を示している。第４図（（ａ）は平面図、（ｂ）は側面
図）は、本発明による配線基板３−１を傷つける事のな
い様な多少弾力性を有する例えばテフロン等の樹脂ブロ
ックを示しており、その例えばテフロン等の樹脂ブロッ
クには、前記配線基板３−１の周辺部に形成された通孔
３−４とほぼ同一サイズの通孔４−１が形成されている
。第５図は本発明によるマルチチップパッケージ（第３
図）を筐体等の基体５−７に実装した実装方法を示す側
面図である。すなわち第１のマルチチップパッケージか
ら第Ｎのマルチチップパッケージの各々の間及び第Ｎの
マルチチップパッケージと筐体との間に、前記マルチチ
ップパッケージの周辺部に設けた少なくとも２ケ所以上
の通孔３−４の存在する位置に前記例えばテフロン等の
樹脂ブロック５−５の通孔４−１の位置を合わせ当該テ
フロン等の樹脂ブロック５−５ （第４図）を挿入し、
これ等の通孔、複数個の３−４及び４−１を光通する様
な例えば金属等の剛体棒５−６を挿入し、その先端をネ
ジ止め等の方法にて筐体等の基体５−７に支持固定する
事により第１から第Ｎまでのマルチチップパッケージを
効率良く実装する事が可能となった。５−１はマルチチ
ップパッケージの配線基板、５−２は気密封止すべく形
成されたキャップ等の基体、５−３はマルチチップパッ
ケージの入出力端子を示す。また５−８は前記金属等の
剛体棒の先端を例えばボルト等によりネジ止めしたその
ボルトを示す。ここに於て、各々の第１から第Ｎまでの
マルチチップパッケージの入出力端子５−３の電気的接
続の形成方法としては、単に金属ワイヤー等を短絡事故
を起こす事なく、ハンダ付けする事によって形成しても
良いが、例えば可撓成配線基板（フレキシブルプリント
配線基板）にあらかじめ各々のマルチチップパッケージ
の入出力端子５−３の存在する位置に通孔を設け、所定
の各入出力端子５−３間の配線を形成しておき、当該可
焼成配線基板（フレキシブルプリント配線基板）をマル
チチップパッケージの入出力端子５−３に挿入し、ノ・
ンダ付は等の方法により支持固定し、電気的接続を形成
するとより容易にかつ信頼性良く各々のマルチチップパ
ッケージの入出力端子５−３間の電気的接続が形成され
得るであろう。Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. 3rd IQ ((a) top view, (b) side view) shows the structure of the multi-chip package according to the present invention, 3-1 is a mountain: chip components such as IC chips that are reserved functional elements are The wiring board 3-2 to be supported and fixed is placed on the wiring board 3-1 in order to hermetically seal the entire chip components.
・Additional methods such as soldering or welding:
1z is shown for a base such as a cap. 3-3 indicates an input/output terminal formed outward parallel to the chip component mounting surface of the multi-chip cage by a method such as soldering or silver soldering. The cloth plate 3-4 is formed at at least two places (four places in the figure) on the wiring board 3-1 around the base body 3-2, such as a cap formed for airtight sealing according to the present invention. It shows a through hole. FIG. 4 ((a) is a plan view, (b) is a side view) shows a resin block made of, for example, Teflon, which has some elasticity so as not to damage the wiring board 3-1 according to the present invention. A through hole 4-1, which is approximately the same size as the through hole 3-4 formed at the periphery of the wiring board 3-1, is formed in the resin block such as Teflon. FIG. 5 shows a multi-chip package (third chip package) according to the present invention.
FIG. 4 is a side view showing a mounting method in which the device shown in FIG. That is, at least two or more through holes are provided in the periphery of the multi-chip package between each of the first multi-chip package to the N-th multi-chip package and between the N-th multi-chip package and the housing. Align the through hole 4-1 of the resin block 5-5 made of Teflon or the like with the position where the resin block 3-4 exists, and insert the resin block 5-5 made of Teflon or the like (Fig. 4),
Insert a rigid rod 5-6 made of metal or the like that allows light to pass through these through holes and the plurality of 3-4 and 4-1, and attach the tip of the rod 5-6 to a base such as a casing by screwing or other methods. By supporting and fixing to 5-7, it became possible to efficiently mount the first to Nth multi-chip packages. 5-1 is a wiring board of the multi-chip package, 5-2 is a base such as a cap formed for airtight sealing, and 5-3 is an input/output terminal of the multi-chip package. Reference numeral 5-8 indicates a bolt in which the tip of the rigid rod made of metal or the like is screwed, for example, with a bolt. Here, the method for forming electrical connections between the input/output terminals 5-3 of each of the first to Nth multi-chip packages is to simply solder metal wires etc. without causing short-circuit accidents. However, for example, through holes may be provided in advance in a flexible wiring board (flexible printed wiring board) at the positions where the input/output terminals 5-3 of each multi-chip package exist, and each predetermined input/output terminal 5-3, and insert the sinterable wiring board (flexible printed wiring board) into the input/output terminal 5-3 of the multi-chip package.
If the multi-chip package is supported and fixed by a method such as soldering and electrical connection is formed, electrical connection between the input and output terminals 5-3 of each multi-chip package can be formed more easily and with high reliability.
発明の効果
本発明を採用する事によシ、平面的には小さな面積しか
有さないが、それに垂直な方向にはある程度のスペース
を有する筐体等の基体に多数のマルチチップパッケージ
を効率よく非常に高密度に実装する事が可能と成った。Effects of the Invention By adopting the present invention, it is possible to efficiently mount a large number of multi-chip packages on a base such as a casing that has only a small surface area but a certain amount of space in the perpendicular direction. This makes it possible to implement extremely high-density packaging.
発明の変形例
尚、本発明の一実施例の図面による説明で、第４図の例
えばテフロン等の樹脂ブロックは、第６図（（ａ）平面
図、（ｂ）側面図）に示す如く、前記マルチチップパッ
ケージの気密封止すべく形成されたキャップ等の基体の
周囲を囲む様な環状構造にしてもよい。但し通孔６−１
は、マルチチップパッケージの配線基板の周辺部に設け
た通孔と同一位置にほぼ同一サイズで形成する事が必要
である。Modifications of the Invention In the drawings for explaining one embodiment of the present invention, the resin block made of, for example, Teflon in FIG. 4 is as shown in FIG. It may be an annular structure that surrounds a base such as a cap formed to hermetically seal the multi-chip package. However, through hole 6-1
It is necessary to form the through hole in the same position and approximately the same size as the through hole provided in the peripheral part of the wiring board of the multi-chip package.
また、本発明のマルチチップパッケージの配線基板及び
気密封止すべきキャップ等の基体は、すべて長方形にて
説明して来たが、これは円形あるい楕円形であっても良
く、その場合は、本発明を採用する事により円筒状ある
いは楕円筒状の筐体等の基体を有する場所に、非常に高
密度に効率良くマルチチップパッケージを実装する事が
可能と成り、ひいては電子機器の超小型化に貢献する事
を可能成らしむる事ができた。In addition, although the base bodies such as the wiring board and the cap to be hermetically sealed in the multi-chip package of the present invention have all been described as being rectangular, they may also be circular or oval. By adopting the present invention, it becomes possible to efficiently mount multi-chip packages at extremely high density in locations with base bodies such as cylindrical or elliptical casings, which in turn allows for ultra-compact electronic devices. We were able to make it possible to contribute to the development of society.
第１図は従来のマルチチップパッケージの斜視図、Ｍ２
図（ａ） （ｂ）は従来のマルチチップパッケージの実
装方法を示す図、第３図（ａ） （ｂ）は本発明による
マルチチップパッケージを説明するだめの図、第４図（
ａ）（ｂ）は本発明によるテフロン等の樹脂ブロックを
示す図、第５図は本発明によるマルチチップパッケージ
の実装方法を示す図、第６図は第４図に示すテフロン等
の樹脂ブロックの他の変形例を示す図である。
１−１．２−１ 、３−１ 、５−１・・アルミナセラ
ミック等のマルチチップ用高密度配線基板、
１−２．２−２．３−２．５−２・・・マルチチップパ
ッケージの気密封止用のキャップ寺の基体、
１−３．２−３．３−３．５−３・・・マルチチップパ
ッケージの入出力端子、
２−４・・・プリント配線基板、
３−４．５−４・・本発明によシ形成されたマルチチッ
プパッケージ用配線基板周辺の通孔、
５−６・・・本発明（Ｃよる金属等の剛体棒、５−７・
・・筐体等の基体。
第３図
第５図
１−／ ｌ’−／Figure 1 is a perspective view of a conventional multi-chip package, M2
Figures (a) and (b) are diagrams showing a conventional multi-chip package mounting method, Figures 3 (a) and (b) are diagrams for explaining the multi-chip package according to the present invention, and Figure 4 (
a) and (b) are diagrams showing a resin block such as Teflon according to the present invention, FIG. 5 is a diagram showing a mounting method of a multi-chip package according to the present invention, and FIG. It is a figure which shows another modification. 1-1.2-1, 3-1, 5-1... High-density wiring board for multi-chip such as alumina ceramic, 1-2.2-2.3-2.5-2... Multi-chip package 1-3.2-3.3-3.5-3... Input/output terminal of multi-chip package, 2-4... Printed wiring board, 3-4 .5-4...Through hole around wiring board for multi-chip package formed according to the present invention, 5-6...Rigid rod of metal etc. according to the present invention (C), 5-7...
・・Base body such as casing etc. Figure 3 Figure 5 1-/l'-/
Claims (3)
態で実装し、当該配線基板の周辺部に電子的機能要素で
あるチップ部品塔載面に平行に配線基板の外向きに入出
力端子を形成し、全体を気密封、止すべくキャップ等の
基体を塔載したマルチチップパッケージの実装方法に於
て、前記第１の配線基板の気密封止すべく形成されたキ
ャップ等の基体の外側の周辺部の少なくとも２ケ所以上
に通孔を設け、第２〜第Ｎの配線基板の周辺部にも第１
の配線基板と同一箇所に同一サイズの通孔を設け、それ
等の通孔よりも大きな大きさを有し、それ等の通孔とほ
ぼ同一サイズの用孔を具備してなる高さが前記マルチチ
ップパッケージの気密封止用のキャップ等の基体の前記
配線基板表面からの高さよりも多少高めの多少弾力性を
有するブロックを形成し、該ブロックを各々の配線基板
間及び配線基板と筐体等の基本との間に挿入し、第１か
ら第Ｎまでの配線基板のすべての通孔と、各々の配線様
な少なくとも２本以上の剛体棒を、前記すべての通孔に
挿入し、その剛体棒の先端部を筐体等の基体に固着せし
める事により、第１から第Ｎまでのマルチチップパッケ
ージを支持固定せしめる事を特徴とするマルチチップパ
ッケージの実装方法。(1) Multiple functional elements are mounted in the form of chips on a wiring board, and input/output is directed outward from the wiring board parallel to the mounting surface of the chip components, which are electronic functional elements, on the periphery of the wiring board. In a method for mounting a multi-chip package on which a base body such as a cap is mounted to form terminals and to hermetically seal the whole, the base body such as a cap formed to hermetically seal the first wiring board. Through holes are provided in at least two places on the outer peripheral part of the wiring board, and the first through hole is provided in the peripheral part of the second to Nth wiring boards.
A through hole of the same size is provided at the same location as the wiring board, and the height is larger than that of the wiring board, and has a hole of approximately the same size as those through holes. A somewhat elastic block is formed that is slightly higher than the height from the surface of the wiring board of a base such as a cap for airtight sealing of a multi-chip package, and the block is placed between each wiring board and between the wiring board and the housing. etc., and insert all the through holes of the wiring board from the first to the Nth and at least two or more rigid rods like each wiring into all the through holes, and A multi-chip package mounting method characterized in that first to Nth multi-chip packages are supported and fixed by fixing the tip of a rigid rod to a base such as a casing.
各々のマルチチップパッケージの配線基板の電子的機能
要素であるチップ部品塔載面と平行に配線基板の外向き
に形成された前記各々の入出力端子の存在している位置
と同一位置配置を有する入出力端子の大きさより多少大
きめの通孔を有し、特定の回路機能を有すべく配線を形
成したフレキシブル配線基板を形成し、該フレキシブル
配線基板上ｇ １〜第Ｎのマルチチップパッケージの各
々の入出力端子に挿入し、接着する事により、第１〜第
Ｎまでのマルチチップパッケージ相互間の電戯曲接続を
形成する事を特徴とする特許の範囲第１項記載のマルチ
チップパッケージの実装方法。(2) Formed outward of the wiring board parallel to the chip component mounting surface, which is the electronic functional element of the wiring board of each of the first to Nth multi-chip packages supported and fixed on a base such as a casing. A flexible wiring board having a through hole slightly larger than the size of the input/output terminals having the same positional arrangement as each of the above-mentioned input/output terminals, and having wiring formed to have a specific circuit function. is formed, inserted into the input/output terminal of each of the 1st to Nth multichip packages on the flexible wiring board, and bonded to connect the first to Nth multichip packages to each other. 1. A method for mounting a multi-chip package according to item 1 of the patent, characterized in that the multi-chip package is formed.
ではなく、前記配線基板のキャップ等の基体の周辺部に
設けた少なくとも２ケ所以上の通孔と同一位置にほぼ同
一の太ささの通孔を設け、前記気密封止すべきキャップ
等の基体の周辺を囲む様な環状構造を有する事を特徴と
する前記特許請求の範囲第１項記載のマルチチップパッ
ケージの実装方法。(3) The block having multiple elasticity is not block-shaped, and has through holes in the same position and approximately the same diameter as at least two through holes provided in the periphery of the base such as the cap of the wiring board. 2. The method of mounting a multi-chip package according to claim 1, further comprising a ring-shaped structure that surrounds the periphery of the base such as the cap to be hermetically sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19442881A JPS5896756A (en) | 1981-12-04 | 1981-12-04 | Mounting method of multichip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19442881A JPS5896756A (en) | 1981-12-04 | 1981-12-04 | Mounting method of multichip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5896756A true JPS5896756A (en) | 1983-06-08 |
| JPH0316785B2 JPH0316785B2 (en) | 1991-03-06 |
Family
ID=16324430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19442881A Granted JPS5896756A (en) | 1981-12-04 | 1981-12-04 | Mounting method of multichip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5896756A (en) |
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208851A (en) * | 1984-03-31 | 1985-10-21 | Toshiba Corp | Multiple-chip type memory circuit device |
| JPS60187543U (en) * | 1984-05-21 | 1985-12-12 | セイコーエプソン株式会社 | High-density mounting method for semiconductor integrated circuit elements |
| JPS63299256A (en) * | 1987-05-29 | 1988-12-06 | Toshiba Corp | Electric component |
| WO1992003035A1 (en) * | 1990-08-01 | 1992-02-20 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
| US5367766A (en) * | 1990-08-01 | 1994-11-29 | Staktek Corporation | Ultra high density integrated circuit packages method |
| US5369058A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US5377077A (en) * | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5448450A (en) * | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| US5455740A (en) * | 1994-03-07 | 1995-10-03 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages |
| US5475920A (en) * | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
| US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
| US5499160A (en) * | 1990-08-01 | 1996-03-12 | Staktek Corporation | High density integrated circuit module with snap-on rail assemblies |
| US5541812A (en) * | 1995-05-22 | 1996-07-30 | Burns; Carmen D. | Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame |
| US5572065A (en) * | 1992-06-26 | 1996-11-05 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package |
| US5585668A (en) * | 1995-01-30 | 1996-12-17 | Staktek Corporation | Integrated circuit package with overlapped die on a common lead frame |
| US5588205A (en) * | 1995-01-24 | 1996-12-31 | Staktek Corporation | Method of manufacturing a high density integrated circuit module having complex electrical interconnect rails |
| US5644161A (en) * | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5783464A (en) * | 1992-06-26 | 1998-07-21 | Staktek Corporation | Method of forming a hermetically sealed circuit lead-on package |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
| US6025642A (en) * | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
| US6205654B1 (en) | 1992-12-11 | 2001-03-27 | Staktek Group L.P. | Method of manufacturing a surface mount package |
| US6572387B2 (en) | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
| US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
-
1981
- 1981-12-04 JP JP19442881A patent/JPS5896756A/en active Granted
Cited By (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208851A (en) * | 1984-03-31 | 1985-10-21 | Toshiba Corp | Multiple-chip type memory circuit device |
| JPS60187543U (en) * | 1984-05-21 | 1985-12-12 | セイコーエプソン株式会社 | High-density mounting method for semiconductor integrated circuit elements |
| JPS63299256A (en) * | 1987-05-29 | 1988-12-06 | Toshiba Corp | Electric component |
| US5420751A (en) * | 1990-08-01 | 1995-05-30 | Staktek Corporation | Ultra high density modular integrated circuit package |
| WO1992003035A1 (en) * | 1990-08-01 | 1992-02-20 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
| US5566051A (en) * | 1990-08-01 | 1996-10-15 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US6168970B1 (en) | 1990-08-01 | 2001-01-02 | Staktek Group L.P. | Ultra high density integrated circuit packages |
| US5377077A (en) * | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5543664A (en) * | 1990-08-01 | 1996-08-06 | Staktek Corporation | Ultra high density integrated circuit package |
| US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5499160A (en) * | 1990-08-01 | 1996-03-12 | Staktek Corporation | High density integrated circuit module with snap-on rail assemblies |
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| US5475920A (en) * | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
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| US5550711A (en) * | 1990-08-01 | 1996-08-27 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5448450A (en) * | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| US5783464A (en) * | 1992-06-26 | 1998-07-21 | Staktek Corporation | Method of forming a hermetically sealed circuit lead-on package |
| US5702985A (en) * | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
| US5572065A (en) * | 1992-06-26 | 1996-11-05 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package |
| US5631193A (en) * | 1992-12-11 | 1997-05-20 | Staktek Corporation | High density lead-on-package fabrication method |
| US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
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| US5828125A (en) * | 1993-03-29 | 1998-10-27 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5843807A (en) * | 1993-03-29 | 1998-12-01 | Staktek Corporation | Method of manufacturing an ultra-high density warp-resistant memory module |
| US5369058A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US6194247B1 (en) | 1993-03-29 | 2001-02-27 | Staktek Group L.P. | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US5369056A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US5978227A (en) * | 1993-03-29 | 1999-11-02 | Staktek Corporation | Integrated circuit packages having an externally mounted lead frame having bifurcated distal lead ends |
| US5644161A (en) * | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5895232A (en) * | 1993-03-29 | 1999-04-20 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5864175A (en) * | 1993-03-29 | 1999-01-26 | Staktek Corporation | Wrap-resistant ultra-thin integrated circuit package fabrication method |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5581121A (en) * | 1993-03-29 | 1996-12-03 | Staktek Corporation | Warp-resistant ultra-thin integrated circuit package |
| US5552963A (en) * | 1994-03-07 | 1996-09-03 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages |
| US5493476A (en) * | 1994-03-07 | 1996-02-20 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends |
| US5479318A (en) * | 1994-03-07 | 1995-12-26 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages with trifurcated distal lead ends |
| US5455740A (en) * | 1994-03-07 | 1995-10-03 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages |
| US5588205A (en) * | 1995-01-24 | 1996-12-31 | Staktek Corporation | Method of manufacturing a high density integrated circuit module having complex electrical interconnect rails |
| US5615475A (en) * | 1995-01-30 | 1997-04-01 | Staktek Corporation | Method of manufacturing an integrated package having a pair of die on a common lead frame |
| US5585668A (en) * | 1995-01-30 | 1996-12-17 | Staktek Corporation | Integrated circuit package with overlapped die on a common lead frame |
| US5541812A (en) * | 1995-05-22 | 1996-07-30 | Burns; Carmen D. | Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame |
| US6025642A (en) * | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
| US6190939B1 (en) | 1997-03-12 | 2001-02-20 | Staktek Group L.P. | Method of manufacturing a warp resistant thermally conductive circuit package |
| US6572387B2 (en) | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
| US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0316785B2 (en) | 1991-03-06 |
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