JPS6130431B2 - - Google Patents
Info
- Publication number
- JPS6130431B2 JPS6130431B2 JP50048666A JP4866675A JPS6130431B2 JP S6130431 B2 JPS6130431 B2 JP S6130431B2 JP 50048666 A JP50048666 A JP 50048666A JP 4866675 A JP4866675 A JP 4866675A JP S6130431 B2 JPS6130431 B2 JP S6130431B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- conductivity type
- diode
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 20
- 230000000295 complement effect Effects 0.000 claims description 16
- 230000000694 effects Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 description 18
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000000969 carrier Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は相補型MIS半導体集積回路装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MIS semiconductor integrated circuit device.
従来、電池駆動される電子式腕時計用回路は、
その消費電力が少ないことから、相補型MIS論理
回路で構成されるものである。この相補型MIS型
論理回路のうち、論理回路用と表示回路用との電
源電圧が異なるものにおいては、従来、二つの電
源を用いるか、あるいは論理回路用の電源電圧を
昇圧回路を用いて昇圧し、表示回路用の電源電圧
を得るものが知られている。この昇圧回路として
は、一般にシエンケル型昇圧回路が用いられ、こ
の回路はダイオードを必要とする。 Conventionally, battery-powered electronic watch circuits are
Because of its low power consumption, it is constructed from complementary MIS logic circuits. Among these complementary MIS type logic circuits, in those with different power supply voltages for the logic circuit and the display circuit, conventionally, two power supplies are used or the power supply voltage for the logic circuit is boosted using a booster circuit. However, devices for obtaining power supply voltage for display circuits are known. A Schienkel type booster circuit is generally used as this booster circuit, and this circuit requires a diode.
ところで、従来、相補型MIS論理回路装置にお
いては、必然的に形成される寄生ダイオードの逆
特性を利用し、MISFETのゲート絶縁破壊の防
止に供せられることはある。しかし、相補型MIS
半導体集積回路装置内にダイオードを形成し、こ
れを順バイアスで動作させることは半導体基板
ｎ、ウエル領域ｐ、ウエル内に形成されたたn+
領域および基板表面部に形成されたｐ型領域（接
地）により生じるサイリスタ効果によつて、回路
の誤動作、あるいは素子の破壊をきたすおそれが
あるため、相補型MIS半導体集積回路を設計する
うえで特に避けるべきこととされていた。また、
ウエル領域に接合ダイオードを形成すると、基板
をコレクタとする寄生トランジスタが構成される
ことにより、基板に漏れ電流が流れ電力損失が生
じるので、低消費電力という相補型MIS論理回路
の利点を活かすことができないと考えられてい
た。 By the way, conventionally, in complementary MIS logic circuit devices, the reverse characteristics of parasitic diodes that are inevitably formed are sometimes used to prevent gate dielectric breakdown of MISFETs. However, complementary MIS
Forming a diode in a semiconductor integrated circuit device and operating it with a forward bias means that the diode formed in the semiconductor substrate n, the well region p, and the well n +
When designing complementary MIS semiconductor integrated circuits, there is a risk that the thyristor effect caused by the p-type region (ground) formed on the area and the substrate surface may cause circuit malfunction or element destruction. It was considered something to be avoided. Also,
When a junction diode is formed in the well region, a parasitic transistor is formed with the substrate as the collector, which causes leakage current to flow into the substrate and causes power loss. Therefore, it is difficult to take advantage of the low power consumption of complementary MIS logic circuits. It was thought that it could not be done.
以上のことから、従来は二つの電池を時計に内
蔵させるか、あるいは時計用相補型MIS半導体集
積回路の外部回路として昇圧回路を構成して―電
源により行なうものであつた。このため、特に実
装スペースが限られる電子式腕時計においては上
記一電源方式あるいは二電源方式のいずれも実装
スペースの点で問題があつた。 For this reason, conventionally, two batteries were built into the watch, or a booster circuit was configured as an external circuit to the complementary MIS semiconductor integrated circuit for the watch, and the power supply was used to operate the watch. For this reason, both the single power supply system and the dual power supply system have problems in terms of mounting space, especially in electronic wristwatches where mounting space is limited.
本発明は上記問題を解決すべくなされたもので
この目的はスイツチング素子として作用するダイ
オードが構成された相補型MIS半導体集積回路装
置を提供することにある。 The present invention has been made to solve the above problems, and its object is to provide a complementary MIS semiconductor integrated circuit device that includes a diode that functions as a switching element.
上記目的を達成するために、本発明に従えば、
第１導電型の半導体基板に形成された第１導電型
と逆導電型である第２導電型のウエル領域と、前
記ウエル領域内に形成され、該ウエル領域ととも
に接合ダイオードとして動作させるための第１導
電型のダイオード用領域と、前記半導体基板に前
記ウエル領域から離間されて形成された第２導電
型の第１の半導体領域とを具備して成る相補型
MIS半導体集積回路装置において、前記ウエル領
域と前記第１の半導体領域との間の前記半導体基
板に、第１導電型の第２の半導体領域を形成し、
該第２の半導体領域に前記第１の半導体領域と同
一の電位を与えるように成し、これによつて、前
記ダイオード用領域と、前記ウエル領域と、前記
半導体基板と、前記第１の半導体領域との相互間
で発生するサイリスタ効果を防止するようにした
ことを特徴とする。 In order to achieve the above object, according to the present invention,
a well region of a second conductivity type, which is formed in a semiconductor substrate of a first conductivity type and is of a conductivity type opposite to the first conductivity type; A complementary type comprising a diode region of one conductivity type and a first semiconductor region of a second conductivity type formed in the semiconductor substrate at a distance from the well region.
In the MIS semiconductor integrated circuit device, a second semiconductor region of a first conductivity type is formed in the semiconductor substrate between the well region and the first semiconductor region;
The second semiconductor region is provided with the same potential as the first semiconductor region, whereby the diode region, the well region, the semiconductor substrate, and the first semiconductor region are connected to each other. It is characterized by preventing the thyristor effect occurring between the regions.
以下、実施例にそつて図面を参照し、本発明を
具体的に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments and drawings.
第１図、第２図は本発明の一実施例を示すもの
である。相補型MIS半導体集積回路にスイツチン
グ素子として作用するダイオードを構成するにあ
たり、ｎ型半導体基板１に形成されたｐ型ウエル
（well）領域２にn+領域３を形成することにより
接合ダイオードＤを得る。なお、上記ウエル領域
２にコンタクトを得るためのp+領域４を形成
し、このp+領域４とn+領域３に電極を設けてこ
の間にダイオードを得る。 FIGS. 1 and 2 show an embodiment of the present invention. In configuring a diode that acts as a switching element in a complementary MIS semiconductor integrated circuit, a junction diode D is obtained by forming an n + region 3 in a p-type well region 2 formed in an n-type semiconductor substrate 1. . Note that a p + region 4 for obtaining a contact is formed in the well region 2, and electrodes are provided in the p + region 4 and n + region 3 to form a diode therebetween.
５はp+拡散層で接地されている。例えば、p+
拡散層５はMISFETのソースとして形成され
る。そして、７は寄生サイリスタ効果を防止する
ために上記ウエル２とp+拡散層との間に設けた
n+拡散層で、接地されている。 5 is grounded with a p + diffusion layer. For example, p +
Diffusion layer 5 is formed as a source of MISFET. 7 is provided between the well 2 and the p + diffusion layer to prevent the parasitic thyristor effect.
n + diffusion layer, grounded.
このn+拡散層を設けかつこれを接地すること
により、接合ダイオードに順方向バイアスが加わ
つてウエル２内のn+拡散層３からウエル２へキ
ヤリアが注入され、その一部がウエル２と半導体
基体１で構成される接合を越えて基板１に収集さ
れる場合においても、n+拡散層７によりp+拡散
層に流れんとするキヤリアを吸収するので、p+
型拡散層５、ｎ型半導体基板１、ｐ型ウエル２に
より構成されるpnp型寄生トランジスタがターン
オンするのを防止することができる。したがつ
て、接合ダイオードが順バイアスされてもサイリ
スタ効果は生じない。 By providing this n + diffusion layer and grounding it, forward bias is applied to the junction diode, carriers are injected from the n + diffusion layer 3 in the well 2 to the well 2, and a part of the carriers are transferred to the well 2 and the semiconductor. Even when the carriers flowing into the p + diffusion layer are absorbed by the n + diffusion layer 7, the p +
It is possible to prevent the pnp type parasitic transistor formed by the type diffusion layer 5, the n type semiconductor substrate 1, and the p type well 2 from turning on. Therefore, no thyristor effect occurs even if the junction diode is forward biased.
すなわち、n+拡散層７は接地されるから、予
め接地されているp+拡散層５と同一電位とな
り、上記pnp型寄生トランジスタの等価ベース
（基板）と等価エミツタ（p+拡散層５）は同電位
にされて、そのベース、エミツタ接合は実質的に
短絡されることになる。これによつて、n+拡散
層３から基板１に流れたキヤリアは、pnp型寄生
トランジスタのベース、エミツタ接合を通過する
ことなく接地に側路される。一方、pnp型寄生ト
ランジスタのベース、エミツタ接合は短絡される
こととなるので、p+拡散層５から基板へのキヤ
リア（ホール）の注入が防止される。結果的に
pnp型寄生トランジスタはターンオンしないこと
となる。従つて、接合ダイオードと基板とが構成
するnpn型寄生トランジスタはターンオンして
も、pnp型寄生トランジスタはターンオンしない
ので、サイリスタ効果は生じない。 That is, since the n + diffusion layer 7 is grounded, it has the same potential as the p + diffusion layer 5, which is grounded in advance, and the equivalent base (substrate) and equivalent emitter (p + diffusion layer 5) of the above pnp parasitic transistor are When brought to the same potential, their base-emitter junctions become essentially short-circuited. As a result, carriers flowing from the n + diffusion layer 3 to the substrate 1 are bypassed to the ground without passing through the base-emitter junction of the PNP parasitic transistor. On the other hand, since the base and emitter junctions of the pnp parasitic transistor are short-circuited, injection of carriers (holes) from the p + diffusion layer 5 into the substrate is prevented. as a result
The pnp parasitic transistor will not turn on. Therefore, even if the npn parasitic transistor constituted by the junction diode and the substrate is turned on, the pnp parasitic transistor is not turned on, so no thyristor effect occurs.
以上説明したように、本発明によればスイツチ
ング素子として動作するダイオードを相補型MIS
半導体集積回路に支障なく構成することができる
ので、本発明を例えば電子式腕時計に適用した場
合、昇圧回路を集積回路内に形成でき―電源―チ
ツプの論理回路が得られる。したがつて、装置の
小型化を図ることができ、集装スペース、および
コストの面で極めて大きな効果が得られる。 As explained above, according to the present invention, a diode that operates as a switching element is connected to a complementary MIS.
Since it can be configured in a semiconductor integrated circuit without any problems, when the present invention is applied to, for example, an electronic wristwatch, a booster circuit can be formed within the integrated circuit, resulting in a power supply-chip logic circuit. Therefore, it is possible to downsize the device, and a significant effect can be obtained in terms of assembly space and cost.
なお、本発明はバイアスの極性をすべて逆にす
ればｐ型半導体を基板とする相補型MIS半導体集
積回路にも適用することができるこというまでも
ない。 It goes without saying that the present invention can also be applied to a complementary MIS semiconductor integrated circuit using a p-type semiconductor as a substrate by reversing the polarities of all biases.
また、本発明は相補型MIS半導体集積回路にス
イツチングダイオードを構成する場合にすべて適
用し得るもので、電子式腕時計に適用範囲が限定
されることはない。 Further, the present invention can be applied to any case where a switching diode is configured in a complementary MIS semiconductor integrated circuit, and the scope of application is not limited to electronic wristwatches.
第１図、第２図は本発明の一実施例を示すもの
で、第１図は断面図、第２図は部分断面斜視図で
ある。
１……ｎ型半導体基板、２，２ａ……ｐ型半導
体ウエル、３……ダイオード形成用n+拡散層、
４……コンタクト用p+型拡散層、５……接地p+
拡散層、６……絶縁膜、７……サイリスタ効果発
生防止用n+拡散層。
1 and 2 show an embodiment of the present invention, with FIG. 1 being a sectional view and FIG. 2 being a partially sectional perspective view. 1...n-type semiconductor substrate, 2, 2a...p-type semiconductor well, 3...n + diffusion layer for diode formation,
4...P + type diffusion layer for contact, 5...Grounding p +
Diffusion layer, 6... Insulating film, 7... n + diffusion layer for preventing the occurrence of thyristor effect.
Claims (1)
１導電型と逆導電型である第２導電型のウエル領
域と、前記ウエル領域内に形成され、該ウエル領
域とともに接合ダイオードとして動作させるため
の第１導電型のダイオード用領域と、前記半導体
基板に前記ウエル領域から離間されて形成された
第２導電型の第１の半導体領域とを具備して成る
相補型MIS半導体集積回路装置において、前記ウ
エル領域と前記第１の半導体領域との間の前記半
導体基板に、第１導電型の第２の半導体領域を形
成し、該第２の半導体領域に前記第１の半導体領
域と同一の電位を与えるように成し、これによつ
て、前記ダイオード用領域と、前記ウエル領域
と、前記半導体基板と、前記第１の半導体領域と
の相互間で発生するサイリスタ効果を防止するよ
うにしたことを特徴とする相補型MIS半導体集積
回路装置。1. A well region of a second conductivity type, which is of a conductivity type opposite to the first conductivity type, formed on a semiconductor substrate of a first conductivity type; and a well region formed within the well region to operate as a junction diode together with the well region. A complementary MIS semiconductor integrated circuit device comprising: a diode region of a first conductivity type; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate at a distance from the well region; A second semiconductor region of a first conductivity type is formed in the semiconductor substrate between the well region and the first semiconductor region, and the second semiconductor region is provided with the same potential as the first semiconductor region. and thereby prevent a thyristor effect occurring between the diode region, the well region, the semiconductor substrate, and the first semiconductor region. A complementary MIS semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50048666A JPS51124385A (en) | 1975-04-23 | 1975-04-23 | Complementary type mis semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50048666A JPS51124385A (en) | 1975-04-23 | 1975-04-23 | Complementary type mis semiconductor integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57067300A Division JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS51124385A JPS51124385A (en) | 1976-10-29 |
| JPS6130431B2 true JPS6130431B2 (en) | 1986-07-14 |
Family
ID=12809644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50048666A Granted JPS51124385A (en) | 1975-04-23 | 1975-04-23 | Complementary type mis semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS51124385A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62297575A (en) * | 1986-05-01 | 1987-12-24 | シ−ルド・パワ−・コ−ポレ−シヨン | Electrohydraulic type control system |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5844763A (en) * | 1982-04-23 | 1983-03-15 | Hitachi Ltd | Complementary mis semiconductor integrated circuit device |
| US4626882A (en) * | 1984-07-18 | 1986-12-02 | International Business Machines Corporation | Twin diode overvoltage protection structure |
| JPH06216380A (en) * | 1992-10-07 | 1994-08-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP2783191B2 (en) * | 1995-06-15 | 1998-08-06 | 日本電気株式会社 | Semiconductor device protection circuit |
-
1975
- 1975-04-23 JP JP50048666A patent/JPS51124385A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62297575A (en) * | 1986-05-01 | 1987-12-24 | シ−ルド・パワ−・コ−ポレ−シヨン | Electrohydraulic type control system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51124385A (en) | 1976-10-29 |
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