JPH0221660B2 - - Google Patents
Info
- Publication number
- JPH0221660B2 JPH0221660B2 JP57067300A JP6730082A JPH0221660B2 JP H0221660 B2 JPH0221660 B2 JP H0221660B2 JP 57067300 A JP57067300 A JP 57067300A JP 6730082 A JP6730082 A JP 6730082A JP H0221660 B2 JPH0221660 B2 JP H0221660B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor
- substrate
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 19
- 230000000295 complement effect Effects 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は相補型MIS半導体集積回路装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MIS semiconductor integrated circuit device.
従来、電池駆動される電子式腕時計用回路は、
その消費電力が少ないことから、相補型MIS論理
回路で構成されるものである。この相補型MIS型
論理回路のうち、論理回路用と表示回路用との電
源電圧が異なるものにおいては、従来、二つの電
源を用いるか、あるいは論理回路用の電源電圧を
昇圧回路を用いて昇圧し、表示回路用の電源電圧
を得るものが知られている。この昇圧回路として
は、一般にシエンケル型昇圧回路が用いられ、こ
の回路はダイオードを必要とする。 Conventionally, battery-powered electronic watch circuits are
Because of its low power consumption, it is constructed from complementary MIS logic circuits. Among these complementary MIS type logic circuits, in those with different power supply voltages for the logic circuit and the display circuit, conventionally, two power supplies are used or the power supply voltage for the logic circuit is boosted using a booster circuit. However, devices for obtaining power supply voltage for display circuits are known. A Schienkel type booster circuit is generally used as this booster circuit, and this circuit requires a diode.
ところで、従来、相補型MIS論理回路装置にお
いては、必然的に形成される寄生ダイオードの逆
特性を利用し、MISFETのゲート絶縁破壊の防
止に供せられることはある。しかし、相補型MIS
半導体集積回路装置内にダイオードを形成し、こ
れを順バイアスで動作させることは半導体基板
（ｎ）、ウエル領域（ｐ）、ウエル内に形成された
n+領域および基板表面部に形成されたｐ型領域
（接地）により生じるサイリスタ効果によつて、
回路の誤動作、あるいは素子の破壊をきたすおそ
れがあるため、相補型MIS半導体集積回路を設計
するうえで特に避けるべきこととされていた。ま
た、ウエル領域に接合ダイオードを形成すると、
基板をコレクタとする寄生トランジスタが構成さ
れることにより、基板に漏れ電流が流れ電力損失
が生じるので、低消費電力という相補型MIS論理
回路の利点を活かすことができないと考えられて
いた。 By the way, conventionally, in complementary MIS logic circuit devices, the reverse characteristics of parasitic diodes that are inevitably formed are sometimes used to prevent gate dielectric breakdown of MISFETs. However, complementary MIS
Forming a diode in a semiconductor integrated circuit device and operating it with a forward bias is a method of forming a diode in a semiconductor substrate (n), a well region (p), and a diode formed in a well.
Due to the thyristor effect caused by the n + region and the p-type region (grounded) formed on the substrate surface,
This should be particularly avoided when designing complementary MIS semiconductor integrated circuits because it may cause circuit malfunction or element destruction. Also, if a junction diode is formed in the well region,
The configuration of a parasitic transistor with the substrate as its collector causes leakage current to flow through the substrate, resulting in power loss, so it was thought that the low power consumption advantage of complementary MIS logic circuits could not be utilized.
以上のことから、従来は二つの電池を時計に内
蔵させるか、あるいは時計用相補型MIS半導体集
積回路の外部回路として昇圧回路を構成して一電
源により行なうものであつた。このため、特に実
装スペースが限られる電子式腕時計においては上
記一電源方式あるいは二電源方式のいずれも実装
スペースの点で問題があつた。 For the above reasons, conventionally, two batteries have been built into a watch, or a booster circuit has been configured as an external circuit of a complementary MIS semiconductor integrated circuit for a watch, and operation has been performed using a single power source. For this reason, both the single power supply system and the dual power supply system have problems in terms of mounting space, especially in electronic wristwatches where mounting space is limited.
本発明は上記問題を解決すべくなされたもので
この目的はスイツチング素子として作用するダイ
オードが構成された相補型MIS半導体集積回路装
置においてサイリスタ効果を防止することにあ
る。 The present invention has been made to solve the above problems, and its purpose is to prevent the thyristor effect in a complementary MIS semiconductor integrated circuit device that includes a diode that functions as a switching element.
上記目的を達成するために、本発明によれば、
相補型MIS半導体集積回路装置において、ｎ型半
導体基板の一部に形成されたｐ型ウエル領域と該
ｐ型ウエル領域内に形成されたｎ型領域とを有
し、これらｐ型ウエル領域とｎ型領域との間に形
成されるpn接合が順バイアスされる可能性のあ
るpn接合ダイオードと前記ウエル領域から離間
して前記半導体基板に形成され、前記基板と同一
電位とされるｐ型の第１の半導体領域とを有し前
記pn接合ダイオードが形成された前記ウエル領
域と前記第１の半導体領域との間のｎ型半導体基
板領域に前記基板に対し逆バイアスされるｐ型の
第２の半導体領域を形成し、かつ該第２の半導体
領域内に前記第２の半導体領域に対し逆バイアス
されるｎ型の第３の半導体領域を形成して成るこ
とを特徴とする。 In order to achieve the above object, according to the present invention,
A complementary MIS semiconductor integrated circuit device has a p-type well region formed in a part of an n-type semiconductor substrate and an n-type region formed within the p-type well region, and the p-type well region and the n-type a p-n junction diode whose p-n junction formed between the well region and the well region may be forward biased; an n-type semiconductor substrate region between the well region in which the p-n junction diode is formed and the first semiconductor region, a p-type second semiconductor region that is reverse biased with respect to the substrate; A semiconductor region is formed, and an n-type third semiconductor region that is reverse biased with respect to the second semiconductor region is formed within the second semiconductor region.
本発明の具体的実施例を説明するに際し、本発
明者によつて予め完成せられたサイリスタ防止構
造を第１図と第２図について説明する。 When describing a specific embodiment of the present invention, a thyristor prevention structure previously completed by the inventor will be described with reference to FIGS. 1 and 2.
第１図、第２図において、相補型MIS半導体集
積回路にスイツチング素子として作用するダイオ
ードを構成するにあたり、ｎ型半導体基板１に形
成されたｐ型ウエル（well）領域２にn+領域３
を形成することにより接合ダイオードＤを得る。
なお、上記ウエル領域２にコンタクトを得るため
のp+領域４を形成し、このp+領域４とn+領域３
に電極を設けてこの間にダイオードを得る。 1 and 2, in configuring a diode that acts as a switching element in a complementary MIS semiconductor integrated circuit, an n + region 3 is placed in a p-type well region 2 formed in an n-type semiconductor substrate 1.
A junction diode D is obtained by forming .
Note that a p + region 4 for obtaining a contact is formed in the well region 2, and this p + region 4 and n + region 3
An electrode is provided between the electrodes and a diode is obtained between the electrodes.
５はp+拡散層で接地されている。そして、７
は寄生サイリスタ効果を防止するために上記ウエ
ル２とp+拡散層との間に設けたn+拡散層で、接
地されている。 5 is grounded with a p + diffusion layer. And 7
is an n + diffusion layer provided between the well 2 and the p + diffusion layer to prevent a parasitic thyristor effect, and is grounded.
このn+拡散層を設けかつこれを接地すること
により、接合ダイオードに順方向バイアスが加わ
つてウエル２内のn+拡散層３からウエル２へキ
ヤリアが注入され、その一部がウエル２と半導体
基板１で構成される接合を越えて基板１に収集さ
れる場合においても、n+拡散層によりp+拡散層
に流れんとするキヤリアを吸収するので、p+拡
散層６、ｎ型半導体基板１、ｐ型ウエル２により
構成されるpnp型寄生トランジスタがターンオン
するのを防止することができる。したがつて、接
合ダイオードが順バイアスされてもサイリスタ効
果は生じない。本発明はこのような構造をさらに
変形したもので、具体的実施例を第３図および第
４図を参照に説明する。 By providing this n + diffusion layer and grounding it, forward bias is applied to the junction diode, carriers are injected from the n + diffusion layer 3 in the well 2 to the well 2, and a part of the carriers are transferred to the well 2 and the semiconductor. Even when the carriers are collected on the substrate 1 across the junction formed by the substrate 1, the n + diffusion layer absorbs the carriers flowing into the p+ diffusion layer. 1. It is possible to prevent the pnp type parasitic transistor formed by the p type well 2 from turning on. Therefore, no thyristor effect occurs even if the junction diode is forward biased. The present invention is a further modification of such a structure, and a specific embodiment will be described with reference to FIGS. 3 and 4.
この実施例はサイリスタ防止用の拡散層として
ｐ型半導体領域２ａ（ウエル２と同時に形成する
ことができる。）を形成し、このｐ型半導体領域
２ａを電源電圧端子（−VDD）に接続してなるも
のである。こうすることによりn+拡散層７をｐ
型半導体領域２ａ内に形成し、それ自体を接地ラ
インの配線として利用することができ、他の配線
８ｂと支障なくクロスさせることが可能となる。
従つて、配線パターンの設計自由度を損うことな
く本発明を実施することができる。 In this embodiment, a p-type semiconductor region 2a (which can be formed at the same time as the well 2) is formed as a diffusion layer for preventing a thyristor, and this p-type semiconductor region 2a is connected to a power supply voltage terminal (-V DD ). This is what happens. By doing this, the n + diffusion layer 7 becomes p
It can be formed in the type semiconductor region 2a and used as a ground line wiring, and can be crossed with other wiring 8b without any trouble.
Therefore, the present invention can be implemented without impairing the degree of freedom in designing the wiring pattern.
第３図および第４図の図面から明らかなよう
に、本実施例によれば、基板１とｐ型領域２ａと
の間のpn接合は逆バイアスされるので、寄生pnp
トランジスタのベース領域（ｎ型基板１）に注入
される少数キヤリアがこのｐ型領域２ａに吸収さ
れることとなる。しかも、この時、n+型領域７
とｐ型領域２ａとの間のpn接合と逆バイアスさ
れるので、このｐ型領域２ａの挿入によつてサイ
リスタを発生させることなく、n+型領域７を配
線として利用できる。 As is clear from the drawings of FIGS. 3 and 4, according to this embodiment, the pn junction between the substrate 1 and the p-type region 2a is reverse biased, so that the parasitic pnp
Minority carriers injected into the base region (n-type substrate 1) of the transistor are absorbed into this p-type region 2a. Moreover, at this time, n + type region 7
Since the pn junction between the p-type region 2a and the p-type region 2a is reverse biased, the n +-type region 7 can be used as a wiring without generating a thyristor by inserting the p-type region 2a.
以上説明したように、本発明によればスイツチ
ング素子として動作するダイオードを相補型MIS
半導体集積回路に支障なく構成することができる
ので、本発明を例えば電子式腕時計に適用した場
合、昇圧回路を集積回路内に形成でき一電源一チ
ツプの論理回路が得られる。したがつて、装置の
小型化を図ることができ、集装スペース、および
コストの面で極めて大きな効果が得られる。 As explained above, according to the present invention, a diode that operates as a switching element is connected to a complementary MIS.
Since it can be configured in a semiconductor integrated circuit without any problems, when the present invention is applied to, for example, an electronic wristwatch, the booster circuit can be formed within the integrated circuit, and a logic circuit with one power supply and one chip can be obtained. Therefore, it is possible to downsize the device, and a significant effect can be obtained in terms of assembly space and cost.
なお、本発明はバイアスの極性をすべて逆にす
ればｐ型半導体を基板とする相補型MIS半導体集
積回路にも適用することができることはいうまで
もない。 It goes without saying that the present invention can also be applied to a complementary MIS semiconductor integrated circuit using a p-type semiconductor as a substrate by reversing the polarities of all biases.
また、本発明は相補型MIS半導体集積回路にス
イツチングダイオードを構成する場合にすべて適
用し得るもので、電子式腕時計に適用範囲が限定
されることはない。 Further, the present invention can be applied to any case where a switching diode is configured in a complementary MIS semiconductor integrated circuit, and the scope of application is not limited to electronic wristwatches.
第１図、第２図は本発明者が検討した半導体集
積回路装置の構造を示し、第１図は断面図、第２
図は部分断面斜視図である。第３図、第４図は本
発明の実施例を示すもので、第３図は断面図（Ａ
−Ａ視）、第４図は配線、半導体領域の平面的位
置を示す平面図である。
１……ｎ型半導体基板、２，２ａ……ｐ型半導
体ウエル、３……ダイオード形成用n+拡散層、
４……コンタクト用p+型拡散層、５……接地p+
拡散層、６……絶縁膜、７……サイリスタ効果発
生防止用n+拡散層、８ａ……接地ライン配線膜、
８ｂ……クロスオーバー配線膜、８ｃ……電源端
子接続用配線膜。
1 and 2 show the structure of a semiconductor integrated circuit device studied by the present inventor, and FIG. 1 is a cross-sectional view, and FIG.
The figure is a partially sectional perspective view. 3 and 4 show embodiments of the present invention, and FIG. 3 is a cross-sectional view (A
-A view), FIG. 4 is a plan view showing the planar positions of wiring and semiconductor regions. 1...n-type semiconductor substrate, 2, 2a...p-type semiconductor well, 3...n + diffusion layer for diode formation,
4...P + type diffusion layer for contact, 5...Grounding p +
Diffusion layer, 6... Insulating film, 7... n + diffusion layer for preventing the occurrence of thyristor effect, 8a... Ground line wiring film,
8b... Crossover wiring film, 8c... Wiring film for power terminal connection.
Claims (1)
ル領域と該ｐ型ウエル領域内に形成されたｎ型領
域とを有し、これらｐ型ウエル領域とｎ型領域と
の間に形成されるpn接合が順バイアスされる可
能性のあるpn結合ダイオードと、前記ウエル領
域から離間して前記半導体基板に形成され、前記
基板と同一電位とされるｐ型の第１の半導体領域
とを有し、前記pn接合ダイオードが形成された
前記ウエル領域と前記第１の半導体領域との間の
ｎ型半導体基板領域に前記基板に対し逆バイアス
されるｐ型の第２の半導体領域を形成し、かつ該
第２の半導体領域内に前記第２の半導体領域に対
し逆バイアスされるｎ型の第３の半導体領域を形
成して成ることを特徴とする相補型MIS半導体集
積回路装置。 ２ 前記ｎ型の第３の半導体領域は配線の一部と
して使用されて成ることを特徴とする特許請求の
範囲第１項記載の相補型MIS半導体集積回路装
置。[Claims] 1. A p-type well region formed in a part of an n-type semiconductor substrate and an n-type region formed within the p-type well region, the p-type well region and the n-type region a p-n coupled diode whose p-n junction may be forward biased; and a p-type first diode formed in the semiconductor substrate apart from the well region and having the same potential as the substrate and a p-type second semiconductor region reverse biased with respect to the substrate in an n-type semiconductor substrate region between the well region in which the p-n junction diode is formed and the first semiconductor region. A complementary MIS semiconductor integrated circuit comprising a semiconductor region and an n-type third semiconductor region reverse biased with respect to the second semiconductor region formed within the second semiconductor region. circuit device. 2. The complementary MIS semiconductor integrated circuit device according to claim 1, wherein the n-type third semiconductor region is used as a part of wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067300A JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067300A JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50048666A Division JPS51124385A (en) | 1975-04-23 | 1975-04-23 | Complementary type mis semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5844763A JPS5844763A (en) | 1983-03-15 |
| JPH0221660B2 true JPH0221660B2 (en) | 1990-05-15 |
Family
ID=13341006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57067300A Granted JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844763A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51124385A (en) * | 1975-04-23 | 1976-10-29 | Hitachi Ltd | Complementary type mis semiconductor integrated circuit |
-
1982
- 1982-04-23 JP JP57067300A patent/JPS5844763A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51124385A (en) * | 1975-04-23 | 1976-10-29 | Hitachi Ltd | Complementary type mis semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5844763A (en) | 1983-03-15 |
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