JPS5844763A - Complementary mis semiconductor integrated circuit device - Google Patents
Complementary mis semiconductor integrated circuit deviceInfo
- Publication number
- JPS5844763A JPS5844763A JP57067300A JP6730082A JPS5844763A JP S5844763 A JPS5844763 A JP S5844763A JP 57067300 A JP57067300 A JP 57067300A JP 6730082 A JP6730082 A JP 6730082A JP S5844763 A JPS5844763 A JP S5844763A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- well
- semiconductor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 230000000295 complement effect Effects 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000000694 effects Effects 0.000 claims abstract description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000002265 prevention Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は相補型ＭＩＳ半導半導体集積回置装置するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a complementary MIS semiconductor integrated rearrangement device.
従来、電池駆動される電子式腕時計用回路は、その消費
電力が少ないことから、相補型ＭＩＳ論垣回路で構成さ
れるものである。この相補型ＭＩＳ型論理回路のうち、
論理回路用と表示回路用との電源電圧が異なるものにお
いては、従来、二つの電源を用いるか、あるいは論珈回
銘用の電源電圧を昇圧回路を用いて昇圧し、表示回路用
の電源電圧を＊るものが知られている。この昇圧回路と
しては、一般にジエンケル型昇圧回路が用いられ、この
回路はダイオードを必要とする。Conventionally, battery-powered electronic wristwatch circuits have been constructed from complementary MIS logic circuits because of their low power consumption. Of this complementary MIS type logic circuit,
Conventionally, when the power supply voltage for the logic circuit and the display circuit are different, two power supplies are used, or the power supply voltage for the logic circuit is boosted using a booster circuit, and the power supply voltage for the display circuit is increased. It is known that there are *. As this booster circuit, a Jenkel type booster circuit is generally used, and this circuit requires a diode.
ところで、従来、相補型ＭＩＳ論珈回路装置においては
、必然的に形成される寄生ダイオードの逆％性を利用し
、ＭＩＳＦＥＴのゲート絶縁破壊の防止に供せられるこ
とはある。しかし、相補型ＭＩＳ半導体集積回路装置内
にダイオードを形成し、これをＩｌｉ！バイアスで動作
させることは半導体基板（ｎ）、ウェル領域（ｐ）、ウ
ェル内に形成されたｎ＋領領域よび基板表面部に形成さ
れたｐ型領域（接地）により生じるサイリスタ効果によ
って、回路の誤動作、あるいは素子の破壊をきたすおそ
れがあるため、相補！！！！Ｍ Ｉ Ｓ半導体集積回路
を設計するうえで特に避けるべきこととされていた。By the way, conventionally, in a complementary MIS logic circuit device, the reverse % property of the parasitic diode that is inevitably formed is sometimes used to prevent the gate dielectric breakdown of the MISFET. However, a diode is formed in a complementary MIS semiconductor integrated circuit device, and this Ili! Operating with bias can cause circuit malfunction due to the thyristor effect caused by the semiconductor substrate (n), the well region (p), the n+ region formed in the well, and the p-type region (ground) formed on the surface of the substrate. , or because there is a risk of damaging the element, use complementary! ! ! ! This was considered to be something that should be particularly avoided when designing an MIS semiconductor integrated circuit.
また、ウェル領域に接合ダイオードを形成すると、基板
をコレクタとする寄生トランジスタが構成されることに
より、基板に漏れ電流が流れ電力損失が生じるので、低
消費電力という相補型ＭＩＳ論理回路の利点を活かすこ
とができないと考えられていた。In addition, when a junction diode is formed in the well region, a parasitic transistor is formed with the substrate as the collector, which causes leakage current to the substrate and causes power loss. It was thought that it could not be done.
以上のことから、従来は二つの電池を時計に内蔵させる
か、あるいは時計用相補型ＭＩ８半導体集積回路の外部
回路として昇圧回路を構成して一電源により行なうもの
であった。このため、特に実装スペースが限られる電子
式腕時計においては上記−電源方式あるいは二電源方式
のいずれも実装スペースの点で問題があった。For the above reasons, conventionally, two batteries have been built into the watch, or a booster circuit has been constructed as an external circuit of the complementary MI8 semiconductor integrated circuit for the watch, and operation has been performed using a single power source. For this reason, both the above-mentioned one-power supply system and two-power supply system have problems in terms of mounting space, especially in electronic wristwatches where mounting space is limited.
本発明は上記問題を解決すべくなされたものでこの目的
はスイッチング素子として作用するダイオードが構成さ
れた相補型ＭＩＳ半導体集積回路装置においてサイリス
タ効果を防止することにある。The present invention has been made to solve the above problems, and its purpose is to prevent the thyristor effect in a complementary MIS semiconductor integrated circuit device that includes diodes that function as switching elements.
上記目的を達成するために、本発明によれば、相補型Ｍ
ＩＳ半導体集積回路装置において、ウエアスされる接合
ダイオードを構成するとともに、この接合ダイオードが
形成されたウェル領域と、このウェル領域と同導電型で
かつ接地された半導体領域との間に、ウェルと逆導電型
の半導体領域☆Ｖ
翫ウェルと同一導電型の半導体領域内に形成され！
る。In order to achieve the above object, according to the present invention, complementary type M
In an IS semiconductor integrated circuit device, a junction diode to be worn is formed, and a semiconductor region opposite to the well is formed between a well region in which this junction diode is formed and a semiconductor region that is of the same conductivity type as this well region and is grounded. Semiconductor region of conductivity type☆V Formed in a semiconductor region of the same conductivity type as the well! Ru.
本発明の具体的実施例を説明するに際し、本発明省によ
って予め完成せられたサイリスタ防止構造を第１図と第
２図について説明する。In describing a specific embodiment of the present invention, a thyristor prevention structure previously completed by the Ministry of the Invention will be described with reference to FIGS. 1 and 2.
第１図、第２図において、相補型ＭＩＳ半導体集積回路
にスイッチング素子として作用するダイオードを構成す
るにあたり、ｎ型半導体基板１に形成されたｐ型ウェル
（ｗｅ！ｌｌ）領域２にｎ＋＋域３を形成することによ
り接合ダイオードＤを得る。1 and 2, in configuring a diode that acts as a switching element in a complementary MIS semiconductor integrated circuit, an n++ region 3 is placed in a p-type well (we!ll) region 2 formed in an n-type semiconductor substrate 1. A junction diode D is obtained by forming .
なお、上記ウェル領域２にコンタクトを得るためのｐ＋
＋域４を形成腰このｐ＋＋域４とｎ＋＋域３に電極を設
けてこの間にダイオードを得る。Note that p+ for contacting the well region 2 is
Electrodes are provided in the p++ region 4 and the n++ region 3 to form a diode between them.
５はｐ＋＋散層で接地されている。そして、７は寄生サ
イリスタ効果を防止するために上記ウェル２とｐ＋＋散
層との間に設けたｎ＋＋散層で、接地され℃いる。5 is grounded with a p++ scattering layer. 7 is an n++ diffused layer provided between the well 2 and the p++ diffused layer to prevent a parasitic thyristor effect, and is grounded.
このｎ＋＋散５層を設けかつこれを接地することにより
、接合ダイオードに順方向バイアスが加わってウェル２
内のｎ＋＋散層３からウェル２ヘキヤリアが注入され、
その一部がウェル２と半導体基体１で構成される接合゛
を越えて基板１に収集される場合に・おいても、ｎ＋＋
散層７によりｐ＋＋散層に流れんとするキャリアを吸収
するので、ｐ＋型型数散層６１ ｎｍ半導体基板１．
ｐ型ウェル２により構成されるｐｎｐ型寄生トランジ
スタがターンオンするのを防止することができる。した
がって、接合ダイオードが順バイアスされてもサイリス
タ効果は生じない。本発明はこのような構造をさらに変
形したもので、具体的実施例を第３図および第４図を参
照に説明する。By providing this n++ 5 layer and grounding it, a forward bias is applied to the junction diode and the well 2
Well 2 well 2 carrier is injected from n++ diffused layer 3 in
Even if a part of it is collected in the substrate 1 beyond the junction 2 formed by the well 2 and the semiconductor body 1, the n++
Since the scattered layer 7 absorbs carriers flowing into the p++ scattered layer, the p+ type scattered layer 61 nm semiconductor substrate 1.
It is possible to prevent the pnp type parasitic transistor formed by the p type well 2 from turning on. Therefore, no thyristor effect occurs even if the junction diode is forward biased. The present invention is a further modification of such a structure, and a specific embodiment will be described with reference to FIGS. 3 and 4.
この実施例はサイリスタ紡出用のｎ＋＋散層７をｐ型半
導体領域２ａ （ウェル２と同時に形成することができ
る。）内に形成し、このｐＷ半導体領域２ａを電源電圧
端子（−■ＤＤ ）に接続してなるものである。こうす
ることによりｎ＋拡散層７自体を接地ラインへの配線と
して利用することができ、他の配線８ｂと支障なくクロ
スさせることが可能となろう従って、配線パターンの設
計自由度を損うことな（本発明を実施することができる
。In this embodiment, an n++ dispersed layer 7 for spinning a thyristor is formed in a p-type semiconductor region 2a (which can be formed at the same time as the well 2), and this pW semiconductor region 2a is connected to a power supply voltage terminal (-DD). It is connected to. By doing this, the n+ diffusion layer 7 itself can be used as a wiring to the ground line, and it will be possible to cross it with other wiring 8b without any problem.Therefore, the degree of freedom in designing the wiring pattern will not be impaired. (The present invention can be implemented.
以−←説明したように、本発明によればスイッチング素
子として動作するダイオードを相補型ＭＩＳ半導体集積
回路に支障な（構成することができるので、本発明を例
えば電子式腕時計に適用した一場合、昇任回路を集積回
路内に形成でき一電源一チツブの論理回路が得られる。As explained below, according to the present invention, a diode that operates as a switching element can be configured in a complementary MIS semiconductor integrated circuit, so that when the present invention is applied to, for example, an electronic wristwatch, The promotion circuit can be formed in an integrated circuit, and a logic circuit with one power supply and one chip can be obtained.
したがって、装置の小型化を図ることかでき、実装スペ
ース、およびコストの面で極めて大きな効果が１得られ
る。Therefore, it is possible to downsize the device, and extremely large effects can be obtained in terms of mounting space and cost.
なお、本発明はバイアスの極性をすべて逆にすればｐ型
半導体を基板とする相補１１Ｍｌ５半導体集積回路にも
適用することができることはいうまでもない。It goes without saying that the present invention can also be applied to a complementary 11M15 semiconductor integrated circuit using a p-type semiconductor as a substrate by reversing the polarities of all biases.
また、本発明は相補ｇＭＩ８半導体集積回路にスイッチ
ングダイオードを構成する場合にすべて適用し得るもの
で、電子式腕時計に適用範囲が限定されることはない。Further, the present invention can be applied to any case where a switching diode is configured in a complementary gMI8 semiconductor integrated circuit, and the scope of application is not limited to electronic wristwatches.
第１図、第２図は本発明者が検討した半導体集積回路装
置の構造を示し、第１図は断面図、第２図は部分断面斜
使図である。第３図、第４図は本発明の実施例を示すも
ので、第３図は断面図（Ａ−Ａ視）、第４図は配線、半
導体領域の平面的位置を示す平面図である。
１・・・ｎ型半導体基板、２，２ａ・・・ｐｍ半導体ウ
ェル、３・・・ダイオード形成用ｎ 拡散層、４・・・
コンタクト用ｐ＋型拡散層、５・・・接地ｐ＋拡散層、
６・・・絶縁膜、７・・・サイリスタ効果発生防止用ｎ
＋拡散層、８ａ・・・接地ライン配５ｔｓｂ・・・クロ
スオーバー配線膜、８Ｃ・・・電源端子接続用配線膜。1 and 2 show the structure of a semiconductor integrated circuit device studied by the present inventor, with FIG. 1 being a sectional view and FIG. 2 being a partially sectional perspective view. 3 and 4 show an embodiment of the present invention. FIG. 3 is a cross-sectional view (viewed along line A-A), and FIG. 4 is a plan view showing the planar positions of wiring and semiconductor regions. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2, 2a... PM semiconductor well, 3... N-diffusion layer for diode formation, 4...
p+ type diffusion layer for contact, 5... ground p+ diffusion layer,
6... Insulating film, 7... Thyristor effect prevention n
+ Diffusion layer, 8a... Ground line wiring 5tsb... Crossover wiring film, 8C... Wiring film for power terminal connection.
Claims (1)
される可能性のある接合ダイオ゛−ドと、前記ウェル領
域から離間して前記半導体基板に形成され、前記ウェル
領域と同一導電型でかつ接地される第１の半導体領域と
を有し、接合ダイオードが形成された前記ウェル領域と
前記第１の半導体領域との間に前記ウェル領域と同一導
電型の第２の半導体領域を形成し、かつ該第２の半導体
領域内に前記ウェル領域と逆導電型の第３の半導体領域
を形成して成り、これによって、サイリスタ効果を防止
して成ることを特徴とする相補型ＭＩＳ半導体集積回路
装置。1. A junction diode that is formed in a well region of a semiconductor substrate and can be forward biased, and a junction diode that is formed in the semiconductor substrate apart from the well region and has the same conductivity type as the well region. forming a second semiconductor region having the same conductivity type as the well region between the well region in which a junction diode is formed and the first semiconductor region; A complementary MIS semiconductor integrated circuit device comprising: a third semiconductor region having a conductivity type opposite to that of the well region; and a third semiconductor region having a conductivity type opposite to that of the well region is formed in the second semiconductor region, thereby preventing a thyristor effect. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067300A JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067300A JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50048666A Division JPS51124385A (en) | 1975-04-23 | 1975-04-23 | Complementary type mis semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5844763A true JPS5844763A (en) | 1983-03-15 |
| JPH0221660B2 JPH0221660B2 (en) | 1990-05-15 |
Family
ID=13341006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57067300A Granted JPS5844763A (en) | 1982-04-23 | 1982-04-23 | Complementary mis semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844763A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51124385A (en) * | 1975-04-23 | 1976-10-29 | Hitachi Ltd | Complementary type mis semiconductor integrated circuit |
-
1982
- 1982-04-23 JP JP57067300A patent/JPS5844763A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51124385A (en) * | 1975-04-23 | 1976-10-29 | Hitachi Ltd | Complementary type mis semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0221660B2 (en) | 1990-05-15 |
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