JPS61207584A - Production of circuit board - Google Patents
Production of circuit boardInfo
- Publication number
- JPS61207584A JPS61207584A JP4764785A JP4764785A JPS61207584A JP S61207584 A JPS61207584 A JP S61207584A JP 4764785 A JP4764785 A JP 4764785A JP 4764785 A JP4764785 A JP 4764785A JP S61207584 A JPS61207584 A JP S61207584A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- sulfuric acid
- substrate
- circuit board
- bubbles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/18—Acidic compositions for etching copper or alloys thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- ing And Chemical Polishing (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は回路基板の製造方法１：関し、とくに回路基板
上Ｃ二銅回路を形成する回路基板の製造方法の改良Ｃ：
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method 1 for manufacturing a circuit board, and particularly to an improvement C of a method for manufacturing a circuit board that forms a C dicopper circuit on the circuit board:
It is related to
従来、回路□基板上に銅回路を形成する回路基板の製造
方法としＣは、基板材料、たとえばセラミック基板上Ｃ
二銅を接着し、その後エツチングレジストを所′望のパ
ターンに印刷し、・ついでエッテンダ□液に浸漬し゛Ｃ
ｆＬツテングを行い回路パターンを形成する方法が行わ
れ°Ｃいる。この場合、エツチング工程において、エツ
チング液としでは塩化第２銅または塩化第２鉄などが主
（二値用される。また硫酸、過硫酸アンモニクム、硝酸
□などによりエツチングを行うことも可能である。 □
〔発明が解決しようとする問題点〕
従来゛のエツチング液とし゛〔塩化第２銅または塩化第
２鉄を使用する場合、有害の□塩酸ガスが発生する。′
また過硫酸アンモニワムを用いると、中和沈澱除去がで
きず、廃液が発生し、廃液処理が極め°Ｃ困難である。Conventionally, in a circuit board manufacturing method in which a copper circuit is formed on a circuit board, C is a substrate material such as C on a ceramic substrate.
After adhering the di-copper, print the etching resist in the desired pattern, and then immerse it in the ettender solution.
A method of forming a circuit pattern by fL drawing is performed. In this case, in the etching step, cupric chloride or ferric chloride is mainly used as the etching solution (binary is used. Etching can also be carried out using sulfuric acid, ammonium persulfate, nitric acid, etc.). □
[Problems to be Solved by the Invention] When cupric chloride or ferric chloride is used as the conventional etching solution, harmful hydrochloric acid gas is generated. ′
Furthermore, when ammonium persulfate is used, it is impossible to neutralize and remove the precipitate, resulting in waste liquid, which is extremely difficult to dispose of at °C.
また硝酸を使用すると、有害のＮ０２ガスが発生する。Also, when nitric acid is used, harmful N02 gas is generated.
硫ｒＲ溶液でエツチングを行う場合は、有害ガスの発生
や、廃液の処理の問題はないが、エツチング速竣が遅い
という問題がある。さら（二上記したエツチング液を使
用した場合、作製した回路基板上（二塩素イオンなどを
残留する場合も起り、これらのイオンは基板の配線パタ
ーンや基板４二実装するｒｃ’ｙツブの配線パターンを
腐蝕させるという問題がある。とくにアルミナの基板上
には、外波樹脂で保護されＣいない裸のＩＣテップを実
装する場合が多く、基板上の残留イオンの問題は重要で
ある。When etching is performed using a sulfur rR solution, there is no problem of generation of harmful gas or disposal of waste liquid, but there is a problem that the speed of etching completion is slow. Furthermore, when using the above-mentioned etching solution, dichloride ions may remain on the fabricated circuit board, and these ions may interfere with the wiring pattern of the board or the wiring pattern of the rc'y block to be mounted on the board. In particular, on alumina substrates, bare IC chips that are not protected by external wave resin are often mounted, and the problem of residual ions on the substrate is important.
〔問題点を解決するための手段］
本発明は従来の問題点を解決するため、エツチング工程
におい′Ｃ１エツチングレジストパターン印刷を行った
基板を、硫酸溶液に酸素ガスを混入し、酸素ガスζ：よ
り硫酸バブルを発生させ、硫酸バブルによりエツチング
を行う方法によることを特徴とするものである。[Means for Solving the Problems] In order to solve the problems of the conventional art, the present invention is performed in the etching process by mixing oxygen gas into a sulfuric acid solution for a substrate on which a 'C1 etching resist pattern has been printed, and treating the substrate with oxygen gas ζ: This method is characterized by a method in which sulfuric acid bubbles are generated and etching is performed using the sulfuric acid bubbles.
本発明は有害ガスの発生や廃液の処理問題のない硫酸溶
液をエツチング液に用い、硫酸溶液；二酸素ガスを混入
し’（ＭＭバブルを発生させ、硫酸バブルによりエツチ
ングを行うことから、硫酸溶液の場合（二比しエツチン
グ速度の迅速化をはかることができる。以下実施例につ
い゛Ｃ説明する。The present invention uses a sulfuric acid solution as an etching solution, which does not generate harmful gases or have problems with waste liquid treatment. In the case of (2), the etching speed can be increased in comparison.An example will be explained below.
第１図は本発明のエツチング工程の一実施例を説明する
図で、硫ｒＩ！３の溶液５二酸素ガス（０２）を注入し
、酸素ガス（二よつ′Ｃ硫酸バブル２を発生させ、硫酸
バブル２によりエツチングレジストパターンの印刷した
基板１をエツチングする方法である。FIG. 1 is a diagram illustrating an embodiment of the etching process of the present invention. In this method, dioxygen gas (02) is injected into solution 5 of step 3 to generate sulfuric acid bubbles 2, and the substrate 1 on which the etching resist pattern is printed is etched by the sulfuric acid bubbles 2.
第２図は本発明のエツチング工程の他の実施例を説明す
る図で、硫酸３に酸素ガス（０２）を吹きつけながら噴
出させ、硫酸６を硫酸の噴流４とし、硫酸の噴流４をエ
ツチングレジストパターンを印刷した基板１Ｃ二噴射し
゛Ｃエツチングを行う方法である。以下（二具体例を示
す。FIG. 2 is a diagram illustrating another embodiment of the etching process of the present invention, in which sulfuric acid 3 is jetted while blowing oxygen gas (02), sulfuric acid 6 is used as sulfuric acid jet 4, and sulfuric acid jet 4 is etched. This is a method of etching a substrate 1C on which a resist pattern has been printed by jetting it twice. Below (two specific examples are shown).
第１図鴫二よる方法の例：
５０Ｘ５０ｘ１ｍのアルミナ基板上に０．５μｍの無電
解Ｎｉめつきを施し、さらに５μｍのＣｕめつきを施し
た。この上ζニフォトレジストのパターンを形成し゛Ｃ
本発明の浸漬する方法ｆ二よりエツチングを行った。エ
ツチング液は硫＃１２０％、液温４０℃とし、１ｔのビ
ーカー中でＯｘ ２００ ｃｃ／分をガラスフィルタを
通し°Ｃ気泡とした。エツチング時間１５分で、単なる
硫酸中でのエツチング（＝比し、１１５の時間であった
。Figure 1: Example of the method by Shiji: 0.5 μm electroless Ni plating was applied to a 50×50×1 m alumina substrate, and further 5 μm Cu plating was applied. On top of this, a pattern of ζ photoresist is formed.
Etching was performed using the immersion method f2 of the present invention. The etching solution was sulfur #120%, the temperature of the solution was 40°C, and 200 cc/min of Ox was passed through a glass filter to create °C bubbles in a 1 ton beaker. Etching time was 15 minutes, compared to etching in simple sulfuric acid (=115 minutes).
第２図Ｃ二よる方法の例：
５Ｄｘ５Ｄｍのポリイミドフィルムを基板とし１８μｍ
の銅箔を貼付し、エツチングレジストを印刷した後、本
発明の吹付ける方法によりエツチングを行った。エツチ
ング液は硫酸３０％、液温８０ Ｃとし、ｍ ｔ ２０
０ ｃｃ／分、Ｃｈ 流！ ５００ ｃｃ／分テ噴”ａ
シｆ、＝。Example of method according to Fig. 2C2: 5D x 5Dm polyimide film is used as a substrate and 18μm
After applying a copper foil and printing an etching resist, etching was performed using the spraying method of the present invention. The etching solution was 30% sulfuric acid, the temperature was 80 C, and m t 20
0 cc/min, Ch style! 500 cc/min injection
Sif,=.
霧滴平均粒径１００μｍとなった。エツチング時間１０
分で、同一の溶液を単（二流しかけた場合（二比し、’
Ａｏとなった。The average particle size of the mist droplets was 100 μm. Etching time 10
If the same solution is applied in 2 minutes,
It became Ao.
以上述べたようじ、本発明によれは硫酸を用いることに
より有害ガスの発生はなく、残留イオンの配線パターン
や基板に実装するＩＣチップの配線パターンに与える影
響が、他のエツチング液、たとえば塩素ガスを発生する
ものに比し小さい。As stated above, according to the present invention, no harmful gas is generated by using sulfuric acid, and the influence of residual ions on the wiring pattern and the wiring pattern of IC chips mounted on the board is reduced by using other etching liquids, such as chlorine gas. It is small compared to that which occurs.
また廃液処理も容易である。さら−二硫酸のみではエツ
チング速度は遅いが、酸素”ガス−二より硫酸・をバブ
ル化しパＣエツチングを行うことにより、エツチング速
度の迅速化がはかれる。Also, waste liquid treatment is easy. In addition, the etching speed is slow when using only disulfuric acid, but the etching speed can be increased by bubble-forming sulfuric acid from oxygen gas and performing PA etching.
第１図および第２図は本発明のエツチング工程の二つの
実施例を説明する図である。
１・・・基板、
２・・・バブル、
３・・・硫酸、
４・・・噴流FIGS. 1 and 2 are diagrams illustrating two embodiments of the etching process of the present invention. 1...Substrate, 2...Bubble, 3...Sulfuric acid, 4...Jet stream
Claims (1)
の工程と、前記銅の層上にエッチングレジストを所望の
パターンに形成する第２の工程と、前記エッチングレジ
ストパターンを形成した基板をエッチング液によりエッ
チングを行う第３の工程からなる回路基板の製造方法に
おいて、 前記第３の工程は、硫酸液に酸素ガスを混入し、前記酸
素ガスにより硫酸バブルを形成し、前記硫酸バブルによ
りエッチングを行うことを特徴とする回路基板の製造方
法。[Claims] A first method of forming a copper layer on a substrate by plating or adhering.
a second step of forming an etching resist in a desired pattern on the copper layer; and a third step of etching the substrate on which the etching resist pattern is formed with an etching solution. The method for manufacturing a circuit board, wherein the third step includes mixing oxygen gas into a sulfuric acid solution, forming sulfuric acid bubbles with the oxygen gas, and performing etching using the sulfuric acid bubbles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4764785A JPS61207584A (en) | 1985-03-11 | 1985-03-11 | Production of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4764785A JPS61207584A (en) | 1985-03-11 | 1985-03-11 | Production of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207584A true JPS61207584A (en) | 1986-09-13 |
Family
ID=12781040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4764785A Pending JPS61207584A (en) | 1985-03-11 | 1985-03-11 | Production of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207584A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000015015A1 (en) * | 1998-09-03 | 2000-03-16 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for manufacturing the same |
| WO2000053824A1 (en) * | 1999-03-08 | 2000-09-14 | Commissariat A L'energie Atomique | Method for eliminating copper from microelectronic components |
| JP2010222654A (en) * | 2009-03-24 | 2010-10-07 | Nippon Steel Engineering Co Ltd | Method of pickling copper-based stock |
| CN102803562A (en) * | 2009-06-25 | 2012-11-28 | 3M创新有限公司 | Methods of wet etching a self-assembled monolayer patterned substrate and metal patterned articles |
-
1985
- 1985-03-11 JP JP4764785A patent/JPS61207584A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000015015A1 (en) * | 1998-09-03 | 2000-03-16 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for manufacturing the same |
| US7415761B2 (en) | 1998-09-03 | 2008-08-26 | Ibiden Co., Ltd. | Method of manufacturing multilayered circuit board |
| US7832098B2 (en) | 1998-09-03 | 2010-11-16 | Ibiden Co., Ltd. | Method of manufacturing a multilayered printed circuit board |
| US8148643B2 (en) | 1998-09-03 | 2012-04-03 | Ibiden Co., Ltd. | Multilayered printed circuit board and manufacturing method thereof |
| WO2000053824A1 (en) * | 1999-03-08 | 2000-09-14 | Commissariat A L'energie Atomique | Method for eliminating copper from microelectronic components |
| FR2790768A1 (en) * | 1999-03-08 | 2000-09-15 | Commissariat Energie Atomique | COPPER CHEMICAL ATTACK PROCESS FOR MICROELECTRONIC COMPONENTS |
| JP2010222654A (en) * | 2009-03-24 | 2010-10-07 | Nippon Steel Engineering Co Ltd | Method of pickling copper-based stock |
| CN102803562A (en) * | 2009-06-25 | 2012-11-28 | 3M创新有限公司 | Methods of wet etching a self-assembled monolayer patterned substrate and metal patterned articles |
| JP2012531518A (en) * | 2009-06-25 | 2012-12-10 | スリーエム イノベイティブ プロパティズ カンパニー | Wet etching method for self-assembled monolayer patterned substrate and metal patterned article |
| JP2017166070A (en) * | 2009-06-25 | 2017-09-21 | スリーエム イノベイティブ プロパティズ カンパニー | Methods of wet-etching self-assembled monolayer patterned substrate and metal patterned articles |
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