JPS61203674A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61203674A JPS61203674A JP4530885A JP4530885A JPS61203674A JP S61203674 A JPS61203674 A JP S61203674A JP 4530885 A JP4530885 A JP 4530885A JP 4530885 A JP4530885 A JP 4530885A JP S61203674 A JPS61203674 A JP S61203674A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- oxide film
- junction
- guard ring
- schottky
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005304 joining Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000239290 Araneae Species 0.000 description 1
- 206010011878 Deafness Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ショットキダイオード単体およびショットキ
ダイオードを含む集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a single Schottky diode and an integrated circuit including a Schottky diode.
ショットキダイオードは単体として、あるいは素子とし
て集積回路に含まれている。本発明は両者を対象とする
ものだが、以下では説明の便宜上、ショットキダイオー
ドについて述べる。Schottky diodes are included in integrated circuits either singly or as elements. Although the present invention is directed to both types, Schottky diodes will be described below for convenience of explanation.
従来、ショットキダイオードの高耐圧化・低順電圧化の
ために、第２図（ＩＬ）に示すように１Ｎ型半導体層２
の主面上のショットキ接合４０周辺をかこんで、Ｐ型領
域（以下ガードリング部という）６を設ける方法が知ら
れている。ガードリング部６は何ら外部的に電気接続さ
れることなく、フローティング状態にしておくもので、
その作用につき同図（ｂ） （ｅ）で説明する。Conventionally, in order to increase the breakdown voltage and lower the forward voltage of Schottky diodes, a 1N type semiconductor layer 2 was used as shown in FIG. 2 (IL).
A known method is to provide a P-type region (hereinafter referred to as a guard ring portion) 6 surrounding the Schottky junction 40 on the main surface of the semiconductor device. The guard ring part 6 is left in a floating state without any external electrical connection.
The effect will be explained with reference to FIGS. 5(b) and (e).
いまショットキ電極４（１）に逆方向電圧ｖＲＩｋ：印
加すると空乏層８が拡がるが、同図（ｂ）は丁度ガード
リング部６に空乏層８が到達したところで、さらに電圧
を高くした状態が同図（ｃ）である０同図（ｂ） Ｋな
るときの逆方向電圧＆Ｖｒｔとすると、同図（ｅ）の場
合にガードリング部６に印加される電圧Ｖ。Ｒは
ｖＧＲ＝ｖＲ−ｖｒｔ
となり、ｖｒｔだけ低くなる。ショットキダイオ−ドと
しては、ガードリング部６をショットキ電極４（１）と
電気接続する型のものがあるが、その型ではｖＧＲはｖ
Ｒそのものである。本発明のショットキダイオードでは
、ｖｒｔだけ低くなり耐圧が高く力る。また所要の耐圧
を得るために１空乏層８の拡がるＮ型半導体層２の厚み
７は薄くして良く、順方向電圧低減にも効果がある。Now, when a reverse voltage vRIk is applied to the Schottky electrode 4(1), the depletion layer 8 expands, and in FIG. If the reverse voltage &Vrt is 0 when the figure (c) is 0 and the figure (b) is K, then the voltage V applied to the guard ring portion 6 in the case of the figure (e). R becomes vGR=vR-vrt, and becomes lower by vrt. As a Schottky diode, there is a type in which the guard ring part 6 is electrically connected to the Schottky electrode 4 (1), but in that type, vGR is v
It is R itself. In the Schottky diode of the present invention, vrt is lowered and the withstand voltage is increased. Further, in order to obtain the required breakdown voltage, the thickness 7 of the N-type semiconductor layer 2 in which one depletion layer 8 extends may be made thinner, which is also effective in reducing the forward voltage.
さて、この種のショットキダイオードの製造方法を、各
工程ごとに図示した第３図で説明する。（ａｌ 二Ｎ”
型半導体基板１の上に成長させた所定の不純物濃度のＮ
型半導体層２を散化し、（ｂ）：酸化膜３に開孔９を設
けてｐ聾ガードリング部６を拡散により形成し、（ｃｌ
：ｐ型ガードリング部６をさらに高温拡散させ所定の深
さにするとともに酸化Ｊ［１０で開孔９をおおった後ホ
トレジストパターン１１を形成し、（ｄ） ： ｆｆ化
膜３に接合開孔部１２をあけ、その部分にショットキ接
合４を形成するために＆ ｅ Ｐｔ ｅ Ｃｒなどの金
属層４（２）をスパッタ法、Ｅガン蒸着法々どで蒸着し
、その上にホトレジストパターン１３を形成し、（ｅ）
：金属層４（２）の不要部分なのぞきショットキ電極
４（１）を形成する。ショットキ電極４（１）からリー
ド線を取りだすためには、さらにその上にＡｇ、ＡＱな
どの金属を形成する。Now, a method for manufacturing this type of Schottky diode will be explained with reference to FIG. 3, which illustrates each step. (al 2N”
type semiconductor substrate 1 with a predetermined impurity concentration.
(b): An opening 9 is provided in the oxide film 3 and a p-deaf guard ring portion 6 is formed by diffusion.
: The p-type guard ring part 6 is further diffused at a high temperature to a predetermined depth, and the opening 9 is covered with oxide J[10, after which a photoresist pattern 11 is formed. (d) : A bonding opening is formed in the FF film 3. A portion 12 is opened, and in order to form a Schottky junction 4 in that portion, a metal layer 4 (2) such as & e Pt e Cr is deposited by sputtering, E-gun vapor deposition, etc., and a photoresist pattern 13 is formed thereon. form, (e)
: A Schottky electrode 4(1) is formed in an unnecessary portion of the metal layer 4(2). In order to take out a lead wire from the Schottky electrode 4(1), a metal such as Ag or AQ is further formed thereon.
上記の製造方法では、第３図（ｂｌ 、 （（り 、
（ｄ）にみられるように、ガードリング部６の開孔９と
７ヨツトキ接合４の接合開孔部１２との孔明けが別々に
行なわれる。そのため第４図のように１ショットキ接合
４とガードリング部６との距離が一様忙ならないことが
多い。この場合、ガードリング部６に空乏層８が到達す
る電圧Ｖｒｔは距離の短いａ側できまり、距離が等しい
ａ ＝ ｂの場合より小さくなる。設計上、当然ａ ＝
ｂのようにしであるが、実際の製造工程では、ｉスフ
目金わせの関係から上記のように不均等になり、装置と
してのＶｒｔが低下する。このため■。８が高くなり、
低い逆方向電圧ｖＲで逆方向降伏が生ずるととＫなる。In the above manufacturing method, as shown in FIG.
As shown in (d), the opening 9 of the guard ring portion 6 and the joining opening 12 of the 7-way joint 4 are drilled separately. Therefore, as shown in FIG. 4, the distance between the Schottky joint 4 and the guard ring portion 6 is often not uniform. In this case, the voltage Vrt that the depletion layer 8 reaches the guard ring portion 6 is determined by the short distance a side, and is smaller than when the distances are equal, a = b. By design, of course a =
However, in the actual manufacturing process, due to the relationship between the i-splash and metal fittings, as described above, the unevenness occurs, and the Vrt of the device decreases. For this reason ■. 8 becomes higher,
If reverse breakdown occurs at a low reverse voltage vR, then K.
このように、接合開孔部１２の位置ずれＫよる耐圧低下
は従来の工程では避けられなかった＠本発明の目的は、
上記の事情に鑑み、接合開孔部認の位置ずれをなくシ、
所定の耐圧をうろことのできる製造方法を提供すること
にある。In this way, the reduction in breakdown voltage due to the positional deviation K of the joining hole 12 was unavoidable in the conventional process.@The purpose of the present invention is to
In view of the above circumstances, we will eliminate the positional deviation of the joint opening.
It is an object of the present invention to provide a manufacturing method that can measure a predetermined withstand pressure.
本発明のショットキダイオードは、フロティング状態の
ガードリング部を有するものであるが、その製造工程に
おいて、前記ガードリング部の形成工程として酸化膜開
孔の際に、以降の工程で形成されるショットキ接合の予
定領域上の酸化膜を、同時に開孔しておくようにしたも
のである。The Schottky diode of the present invention has a guard ring part in a floating state, and in the manufacturing process, when the oxide film is opened as the step of forming the guard ring part, the Schottky diode formed in the subsequent process is At the same time, holes are opened in the oxide film on the area where bonding is planned.
ガードリング部と、ショットキ接合の予定領域とのため
の酸化膜の開孔を同時に行なっているから、目合わせマ
スクを共通に使用することができる。したがって後の工
程でショットキ接合を形成する場合に、前記酸化膜の開
孔である接合開孔部を基準としてなされるから、ガード
リング部と、ショットキ接合との距離は、目合わせマス
ク精度で、均等にすることができる。Since the holes in the oxide film for the guard ring portion and the area where the Schottky junction is to be formed are formed at the same time, the alignment mask can be used in common. Therefore, when forming a Schottky junction in a later step, it is done based on the junction opening, which is the opening in the oxide film, so the distance between the guard ring part and the Schottky junction is determined by the accuracy of the alignment mask. It can be made even.
これ罠よってショットキダイオードの耐圧を設計値の範
囲内におさめることができる〇〔実施例〕
以下、図面を参照して本発明の一実施例の説明を行なう
。第１図に実施例を工程順に図示しである。同図（ａ）
はシリコン！型半導体基板１上に成長させた所定の不純
物濃度のＮ型半導体層２を酸化し、両面に酸化膜３が形
成された状態である。次に同図（ｂ） Ｋ示すように、
酸化膜３に写真蝕刻法により、ガードリング部６を形成
するための開孔９をあけるが、このときガラスマスクに
は将来ショットキ接合を形成すべき予定部分くもパター
ンを設けて同時に接合開孔部臣な形成する◎
次に、同図（ｅ） Ｋ示すように、熱酸化法により開孔
９．接合開孔部ｎ上に酸化膜１０ｉｋ形成するが、この
厚さは、ガードリング部９の形成を行なう（同図（ｄ）
）ときに１接合開孔部１２に拡散されないようにマスク
となる充分な厚さとする。By this means, the breakdown voltage of the Schottky diode can be kept within the range of the designed value. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in the order of steps. Figure (a)
is silicon! An N-type semiconductor layer 2 with a predetermined impurity concentration grown on a type semiconductor substrate 1 is oxidized, and oxide films 3 are formed on both surfaces. Next, as shown in Figure (b) K,
An opening 9 for forming the guard ring part 6 is made in the oxide film 3 by photolithography. At this time, a spider pattern is provided on the glass mask in the area where the Schottky junction is to be formed in the future, and at the same time, the opening 9 for forming the guard ring part 6 is formed in the glass mask. ◎ Next, as shown in Figure (e) K, apertures 9. An oxide film 10ik is formed on the junction opening n, the thickness of which is the same as the formation of the guard ring part 9 (FIG. 1(d)).
) The thickness is sufficient to act as a mask to prevent diffusion into the one-junction opening 12.
ソｔ、テホトレジストパターン１４を接合開孔部１２の
酸化［１０上に形成する。Then, a photoresist pattern 14 is formed over the oxidation layer 10 of the junction opening 12.
次に、同図（ｄ）に示すように、開孔９上の酸化膜１０
をエツチングするが、エツチングは前記酸化膜１０が除
去されたら直ちに停止し、ホトレジストで保護されてい
ない酸化膜３がエッチされすぎないようにする。エツチ
ング後、ホトレジストパターン１４す除去し、拡散を行
ない、ガードリング部６を形成する。Next, as shown in FIG. 3D, the oxide film 10 on the opening 9
However, the etching is stopped immediately after the oxide film 10 is removed, so that the oxide film 3 not protected by the photoresist is not etched too much. After etching, the photoresist pattern 14 is removed and diffused to form the guard ring portion 6.
次に、同図（ｅ）に示すようにガードリング部６上に表
面保護のため再度酸化膜１５を形成した後、ホトレジス
トパターン１６を利用して、同図（ｆ）に示すように、
接合開孔部１２に形成された酸化膜１σを除去し、接合
開孔部化を再び露呈する。同図（ｆ）はホトレジストパ
ターン１６除去後の状態を示す・
以下の工程は、従来例の第３図（ｄｌ 、 （ｅ）と同
様に行ない、Ｎ型半導体層稔との境界にショットキ接合
４な形成するようにショットキ電極４（１）をつくる。Next, as shown in FIG. 5(e), an oxide film 15 is again formed on the guard ring portion 6 for surface protection, and then, using a photoresist pattern 16, as shown in FIG.
The oxide film 1σ formed on the junction opening 12 is removed to expose the junction opening again. FIG. 3(f) shows the state after the photoresist pattern 16 has been removed. The following steps are performed in the same manner as in FIGS. The Schottky electrode 4(1) is made so as to have a uniform shape.
なお、前記一連の工程で、開孔９と、接合開孔部１２は
、同図（ｂ）で一度形成後、それ以降の工程でその部分
に酸化膜１０ 、１０’ 、 １ゲを形成し、またエツ
チングするので、最初に設ける酸化膜３は上記工程を考
慮して充分な厚さにとる。In addition, in the series of steps described above, after the opening 9 and the joining opening 12 are formed once as shown in FIG. Also, since etching is performed, the oxide film 3 to be formed first should have a sufficient thickness in consideration of the above steps.
以上、詳しく説明したように、ガードリング部の酸化膜
の開孔とショットキ接合に予定される接合開孔部とが同
一工程で形成され、最終的にショットキ接合とガードリ
ング部との距離がショットキ接合周辺にわたって一様に
なる。このためショットキダイオードに逆方向電圧を加
えたときの、空乏層が拡がりガードリング部に到達する
電圧Ｖｒ ｔが設計どおりとなり、耐圧電圧を高くとる
ことができる。また順方向電圧の低下も期待できる。な
お、集積回路に組込んだ場合にも、本発明が適用できる
ことはいうまでもない。As explained in detail above, the opening in the oxide film of the guard ring part and the junction opening part planned for the Schottky junction are formed in the same process, and the distance between the Schottky junction and the guard ring part is finally the same as that of the Schottky junction. uniform around the joint. Therefore, when a reverse voltage is applied to the Schottky diode, the depletion layer expands and the voltage Vrt that reaches the guard ring portion is as designed, and a high withstand voltage can be achieved. Further, a reduction in forward voltage can be expected. It goes without saying that the present invention is also applicable when incorporated into an integrated circuit.
第１図は、本発明の一実施例を示す製造方法を工程順に
示した図、第２図はガードリング部の効果を説明するた
めの図、第３図は従来例の製造工程図、第４図は従来例
で生ずるショットキ接合領域の位置ずれを示す図である
。
１・・・！型半導体基板、
２・・・Ｎ型半導体層、
３・・・酸化膜、 ４・・・ショットキ接合、４
（１）・・・ショットキ電極、４（２１・・・金属層、
６・・・ガードリング部、９・・・開孔、１０ 、１０
’ 、 １０’、 １５・・・酸化膜、１１ 、１３
、１４ 、１６・・・ホトレジストパターン、１２・・
・接合開孔部。FIG. 1 is a diagram showing a manufacturing method according to an embodiment of the present invention in order of process, FIG. 2 is a diagram for explaining the effect of the guard ring part, and FIG. 3 is a manufacturing process diagram of a conventional example. FIG. 4 is a diagram showing the positional deviation of the Schottky junction region that occurs in the conventional example. 1...! type semiconductor substrate, 2... N type semiconductor layer, 3... Oxide film, 4... Schottky junction, 4
(1)... Schottky electrode, 4 (21... metal layer,
6... Guard ring part, 9... Opening hole, 10, 10
', 10', 15...Oxide film, 11, 13
, 14, 16... photoresist pattern, 12...
・Joint opening.
Claims (1)
合の周辺に設けられ、前記伝導型と異なる伝導型の電気
的接続のないガードリング部とを有する半導体装置の製
造工程において、前記ガードリング部の形成工程として
、酸化膜開孔の際に、以降の工程で形成される前記ショ
ットキ接合の予定領域上の酸化膜を同時に開孔しておく
ことを特徴とする半導体装置の製造方法。In the manufacturing process of a semiconductor device having a Schottky junction on a main surface of a semiconductor of a certain conductivity type, and a guard ring portion provided around the junction and having no electrical connection of a conductivity type different from the conductivity type, the guard 1. A method for manufacturing a semiconductor device, wherein in the step of forming a ring portion, when opening a hole in the oxide film, a hole is simultaneously opened in the oxide film on a region where the Schottky junction to be formed in a subsequent step is to be formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4530885A JPS61203674A (en) | 1985-03-07 | 1985-03-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4530885A JPS61203674A (en) | 1985-03-07 | 1985-03-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61203674A true JPS61203674A (en) | 1986-09-09 |
Family
ID=12715683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4530885A Pending JPS61203674A (en) | 1985-03-07 | 1985-03-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61203674A (en) |
-
1985
- 1985-03-07 JP JP4530885A patent/JPS61203674A/en active Pending
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| JPS6341075A (en) | Manufacture of semiconductor device | |
| JPS61236162A (en) | Manufacture of semiconductor device |