JPS61172361A - Manufacture of tape carrier - Google Patents
Manufacture of tape carrierInfo
- Publication number
- JPS61172361A JPS61172361A JP60013833A JP1383385A JPS61172361A JP S61172361 A JPS61172361 A JP S61172361A JP 60013833 A JP60013833 A JP 60013833A JP 1383385 A JP1383385 A JP 1383385A JP S61172361 A JPS61172361 A JP S61172361A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- tape carrier
- chip
- gold
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 239000011888 foil Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 14
- 239000011889 copper foil Substances 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000003795 chemical substances by application Substances 0.000 description 8
- 229910000831 Steel Inorganic materials 0.000 description 6
- 239000010959 steel Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
長生立国
本発明は、デバイス孔を形成した絶縁フィルム基板の表
面上に金属箔を設け、この金属箔上にフォトレジストを
コーティングした後、金属箔をエツチングすることによ
って、デバイス孔の周囲にＩＣ，ＬＳＩ等のチップのボ
ンディング用フィンガを有する配線部を形成するテープ
キャリアの製造方法に関する。[Detailed description of the invention] The present invention provides a metal foil on the surface of an insulating film substrate in which device holes are formed, coats a photoresist on the metal foil, and then etches the metal foil. The present invention relates to a method for manufacturing a tape carrier in which a wiring portion having fingers for bonding chips such as ICs and LSIs is formed around device holes.
！末鼓豊
従来のこの種の製造方法において、フィンガの先端部に
バンプを設けるには、第１２図ないし第１４図に示すよ
うに、デバイス孔（１）を形成した絶縁フィルム基板（
２）上の銅箔を両面同時エツチングして、フィンガ（３
）を有する配線部（４）を形成するとともに、フィンガ
（３）に凹部（５）を設けることによりその先端部にバ
ンプ（６）を一体に形成し、この後、フィンガ（３）を
含む配線部（４）の表面全域に薄い金メッキ（７）を施
こしていた。! In this type of conventional manufacturing method, as shown in FIGS. 12 to 14, in order to provide a bump at the tip of the finger, an insulating film substrate (
2) Etch the upper copper foil on both sides at the same time to make the fingers (3
), and by providing a recess (5) in the finger (3), a bump (6) is integrally formed at the tip thereof, and then the wiring including the finger (3) is formed. A thin gold plating (7) was applied to the entire surface of the part (4).
しかし、これによると、バンプ高さくａ）は２０〜３０
μｍ必要であり、凹部（５）部分の残部肉厚（ｂ）も強
度上３０μｍ程度なければならないから、総厚（１）が
厚くなり、エツチング時間が長くなるとともに、銅の溶
解量が多く液の疲労も早いから、経済的好ましくない欠
点があった。また、エツチングを深くしなければならな
いので、フィンガ間隔の狭いものには不向きであり、バ
ンプ巾（ｄ）を小さくできない欠点もあった。さらに、
バンプに金メッキを施こすものの、その厚さは薄くしか
もバンプ自体は銅製であるため、ボンディングの信頼性
が低いという問題点があった。However, according to this, the bump height a) is 20 to 30
The thickness (b) of the remaining part of the recess (5) must also be about 30 μm for strength reasons, so the total thickness (1) becomes thicker, the etching time becomes longer, and the amount of dissolved copper increases. It also had the disadvantage of being economically undesirable because it fatigued quickly. Furthermore, since the etching must be deep, it is not suitable for devices with narrow finger spacing, and also has the disadvantage that the bump width (d) cannot be made small. moreover,
Although the bumps are plated with gold, the thickness is thin and the bumps themselves are made of copper, so there is a problem in that the reliability of bonding is low.
目 的
本発明の目的は、このような問題点を解消できるテープ
キャリアの製造方法を提供することにある。Purpose An object of the present invention is to provide a method for manufacturing a tape carrier that can solve these problems.
構 成
本発明においては、デバイス孔を形成した絶縁フィルム
基板の表面上に金属箔を設けた後、この金属箔の表面に
表側フォトレジスト、デバイス孔内に露呈している同金
属箔の裏面に裏側フォトレジストをコーティングする。Structure In the present invention, after a metal foil is provided on the surface of an insulating film substrate in which a device hole is formed, a front side photoresist is applied to the surface of this metal foil, and a back side photoresist is applied to the back side of the same metal foil exposed inside the device hole. Coat photoresist.
この後、表裏面フォトレジストを露光し１表側フォトレ
ジストの配線パターン形成部分以外の部分を除去すると
ともに、裏側フォトレジストにバンプ形成用欠除部を形
成する。次に、このバンプ形成用欠除部において金属箔
に金等のメッキを施こしてバンプを突設した後、金属箔
をエツチングし、最後に表裏面フォトレジストを剥離す
る。Thereafter, the front and back photoresists are exposed to light to remove the portions of the front side photoresist other than the wiring pattern formation portion, and at the same time, a bump formation cutout is formed in the back side photoresist. Next, the metal foil is plated with gold or the like in this bump-forming cutout to form a protruding bump, and then the metal foil is etched, and finally the photoresist on the front and back surfaces is peeled off.
夫−１−五 以下に本発明の実施例を図面に基づいて詳述する。Husband-1-5 Embodiments of the present invention will be described in detail below based on the drawings.
まず、第１図に示すように、絶縁フィルム基板（１１）
の表面上に鋼箔（１２）を設ける。絶縁フィルム基板（
１１）には、方形のデバイス孔（１３）が予め等間隔に
形成されている。First, as shown in Figure 1, an insulating film substrate (11)
A steel foil (12) is provided on the surface of. Insulating film substrate (
11), rectangular device holes (13) are formed in advance at equal intervals.
次に、第２図に示すように鋼箔（１２）の表面に表側フ
ォトレジスト（１４）、デバイス孔（１３）内において
鋼箔（１２）の裏面に裏側フォトレジスト（１５）をコ
ーティングした後、これら両フォトレジスト（１４）・
（１５）を同時に露光し、第３図に示すように表側フォ
トレジスト（１４）の配線パターン形成部分以外の部分
（１４ａ）を除去するとともに、裏側フォトレジスト（
１５）にバンプ形成用欠除部（１５ａ）を形成する。Next, as shown in Fig. 2, the front side photoresist (14) is coated on the surface of the steel foil (12), and the back side photoresist (15) is coated on the back side of the steel foil (12) in the device hole (13). , these both photoresists (14)・
(15) is exposed at the same time to remove the portion (14a) of the front side photoresist (14) other than the wiring pattern forming area as shown in FIG.
15) Form a bump-forming cutout (15a).
その後、このバンプ形成用欠除部（１５ａ）において鋼
！（１２）の裏面に、第４図に示すように金メッキを施
こすことによってバンプ（１６）を盛り上げ形成する。Thereafter, in this bump-forming cutout (15a), steel! As shown in FIG. 4, bumps (16) are formed on the back surface of (12) by applying gold plating.
次いで、第５図に示すように裏側フォトレジスト（１５
）上に、その剥離剤で溶解するラッカー等の裏止め剤（
１７）をコーティングした後、第６図に示すように銅箔
（１２）を従来公知のごとくエツチングする。ここで、
裏止め剤（１７）をコーティングするのは、エツチング
後の裏側フォトレジスト（１５）が破れて銅箔（１２）
が腐蝕することがないようにするためである。また、こ
のコーティングによってバンプ（１６）を裏止め剤（１
７）に埋設し、同時にバンプ（１６）の腐蝕も防止する
ことができる。Next, as shown in FIG.
) on top of a backing agent such as lacquer that dissolves with the release agent (
After coating 17), the copper foil 12 is etched as is known in the art, as shown in FIG. here,
The backing agent (17) is coated on the copper foil (12) after the backside photoresist (15) is torn after etching.
This is to prevent corrosion from occurring. This coating also allows the bumps (16) to be bonded to the backing agent (1).
7), and at the same time can prevent corrosion of the bump (16).
このように裏止め剤（１７）で保護して銅箔（１２）を
エツチングした後１表裏両フォトレジスト（１４）・（
１５）を剥離剤で剥離するとともに、これと同時に裏止
め剤（１７）を除去すれば、第７図に示すような製品、
つまりデバイス孔（１３）の周囲に銅箔（１２）による
配線部（１８）を形成し、この配線部（１８）のフィン
ガ（１９）の先端部の裏面に金メッキによるバンプ（１
６）を突設した目的とするテープキャリアが得られる。After protecting the copper foil (12) with a backing agent (17) and etching it, photoresists (14) on both the front and back sides are applied.
If 15) is removed with a release agent and the backing agent (17) is removed at the same time, a product as shown in Figure 7 is obtained.
That is, a wiring part (18) made of copper foil (12) is formed around the device hole (13), and a gold-plated bump (1
6) The desired tape carrier with protruding parts is obtained.
、 このテープキャリアにＩＣ，ＬＳＩ等のチップを実
装するには、第８図に示すようにチップ（２ｏ）上の接
続端子１例えばアルミパッド（２１）をバンプ（１６）
にボンディングする。バンプ（１６）は、全体が金製で
しかもボンディングの際につぶれてアルミパッド（２１
）の面上をすベリ、表面のアルミ酸化膜を部分的に破る
から、金とアルミニウムとが固着され、ボンディングの
信頼性が高い。, To mount a chip such as an IC or LSI on this tape carrier, as shown in Fig. 8, connect the connecting terminal 1 such as an aluminum pad (21) on the chip (2o) with a bump (16).
Bond to. The bump (16) is entirely made of gold and is crushed during bonding, resulting in an aluminum pad (21).
), and partially breaks the aluminum oxide film on the surface, so the gold and aluminum are firmly bonded and the bonding reliability is high.
なお、本発明は、鋼箔を絶縁フィルム基板の表面上に接
着剤を介することなく設けた、いわゆる二層テープはも
ちろん、接着剤を介して固着した三層テープにも適用で
きる。The present invention can be applied not only to a so-called two-layer tape in which a steel foil is provided on the surface of an insulating film substrate without using an adhesive, but also to a three-layer tape in which the steel foil is fixed via an adhesive.
また、第９図に示すとおり各フィンガ（２２）にそれぞ
れインナバンプ（２３）とアウタバンプ（２４）との２
つを設け、第１０図に示す如くインナバンプ（２３）・
・・・・・を１個のチップ（２５）上の接続端子（２６
）・・団・にそれぞれ固着し、その後フィンガ（２２）
部分を切り゛離し、たとえば第１１図に示す如くアウタ
バンプ（２４）を基板（２７）のリード部（２７ａ）に
接続するようにしてもよい。In addition, as shown in FIG. 9, each finger (22) has two inner bumps (23) and an outer bump (24).
and an inner bump (23) as shown in Fig. 10.
...... to the connection terminal (26) on one chip (25).
)... each sticks to the group, and then the finger (22)
The parts may be separated and the outer bumps (24) may be connected to the lead portions (27a) of the substrate (27), for example, as shown in FIG.
勿−ｍ＝１ 以上述べた通り本発明によれば次のような効果がある。Of course - m = 1 As described above, the present invention has the following effects.
■ エツチング時間を短縮し、作業時間を短かくするこ
とができる。■ Etching time can be shortened and working time can be shortened.
■ バンプ巾を小さくできるとともに、フィンガ間が狭
い場合にも問題なくバンプを形成することができる。- The bump width can be reduced, and bumps can be formed without problems even when the distance between fingers is narrow.
■ フィンガに対してバンプがメッキにより接合され、
しかもバンプ全体がフィンガとは別に金等で盛り上げ構
成されるため、ボンディングの信頼性が高い。■ The bump is joined to the finger by plating,
Moreover, since the entire bump is made of gold or the like, separate from the fingers, the bonding reliability is high.
■ 得られるテープキャリアは汎用のＩＣ等にそのまま
使用できる。■ The resulting tape carrier can be used as is for general-purpose ICs, etc.
第１図ないし第７図は本発明の方法を工程順に従って示
す断面図、第８図はそれによって得られたテープキャリ
アにチップを実装する使用例を示す断面図、第９図は本
発明の方法によって得られた他あテープキャリアの断面
図、第１０図および第１１図はそれぞれそのテープキャ
リアにチップを実装する使用例を示す断面図、第１２図
ないし第１４図は従来の方法を示す断面図である。
（１１）・・・・・・・・・絶縁フィルム基板（１２）
・・・・・・・・・銅箔
（１３）・・・・・・・・・デバイス孔（１４）・・・
・・・・・・表側フォトレジスト（１５）・・・・・・
・・・裏側フォトレジスト（１４ａ）・・・・・・・・
・表側フォトレジストの除去部分（１５ａ）・・・・・
・・・・バンプ形成用欠除部（１６）・・・・・・・・
・バンプ
（１７）・・・・・・・・・裏止め剤
（１８）・・・・・・・・・配線部
（１９）・・・・・・・・・フィンガ
（２０）・・・・・・・・・チップ
（２１）・・・・・・・・・アルミパッド第１図
第２図
第３図
第４図
第５図
第６図
第８図
第９図
第１０図
第１２図
第１３図
第１４図1 to 7 are cross-sectional views showing the method of the present invention according to the process order, FIG. 8 is a cross-sectional view showing an example of mounting a chip on a tape carrier obtained by the method, and FIG. 9 is a cross-sectional view showing the method of the present invention according to the process order. FIGS. 10 and 11 are cross-sectional views showing an example of how a chip is mounted on the tape carrier, respectively, and FIGS. 12 to 14 show the conventional method. FIG. (11) Insulating film substrate (12)
......Copper foil (13)...Device hole (14)...
...Front side photoresist (15)...
...Back side photoresist (14a)...
・Removed portion of front photoresist (15a)...
...Bump forming cutout (16)...
・Bump (17)...Backing agent (18)...Wiring section (19)...Finger (20)... ...... Chip (21) ...... Aluminum pad Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 8 Fig. 9 Fig. 10 Fig. 12 Figure 13 Figure 14
Claims (1)
属箔を設ける工程と、この金属箔の表面に表側フォトレ
ジスト、前記デバイス孔内に露呈している裏面に裏側フ
ォトレジストをコーティングする工程と、前記表側及び
裏側のフォトレジストを露光し、表側フォトレジストの
配線パターン形成部分以外の部分を除去するとともに、
裏側フォトレジストにバンプ形成用欠除部を形成する工
程と、前記バンプ形成用欠除部において前記金属箔に金
等のメッキを施こしてバンプを突設する工程と、前記金
属箔をエッチングする工程と、前記表側及び裏側のフォ
トレジストを剥離する工程とからなるテープキャリアの
製造方法。a step of providing a metal foil on the surface of the insulating film substrate in which the device hole is formed; a step of coating the surface of the metal foil with a front side photoresist; and a step of coating the back side exposed in the device hole with a back side photoresist; Expose the photoresist on the front side and the back side, remove the parts of the front side photoresist other than the wiring pattern forming part, and
forming a bump-forming cutout in the back side photoresist; plating the metal foil with gold or the like in the bump-forming cutout to provide a protruding bump; and etching the metal foil. A method for manufacturing a tape carrier, comprising: a step of peeling off the photoresist on the front side and the back side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60013833A JPS61172361A (en) | 1985-01-28 | 1985-01-28 | Manufacture of tape carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60013833A JPS61172361A (en) | 1985-01-28 | 1985-01-28 | Manufacture of tape carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61172361A true JPS61172361A (en) | 1986-08-04 |
Family
ID=11844269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60013833A Pending JPS61172361A (en) | 1985-01-28 | 1985-01-28 | Manufacture of tape carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61172361A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6358938A (en) * | 1986-08-29 | 1988-03-14 | Mitsubishi Electric Corp | Manufacture of film carrier with bump |
| WO1998033212A1 (en) * | 1997-01-23 | 1998-07-30 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment |
| WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
-
1985
- 1985-01-28 JP JP60013833A patent/JPS61172361A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6358938A (en) * | 1986-08-29 | 1988-03-14 | Mitsubishi Electric Corp | Manufacture of film carrier with bump |
| WO1998033212A1 (en) * | 1997-01-23 | 1998-07-30 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment |
| US6175151B1 (en) | 1997-01-23 | 2001-01-16 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| US6414382B1 (en) | 1997-01-23 | 2002-07-02 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument |
| US6646338B2 (en) | 1997-01-23 | 2003-11-11 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
| FR2808920A1 (en) * | 2000-05-10 | 2001-11-16 | Gemplus Card Int | Method for protecting chips arranged on a wafer comprises cutting wafer to loosen chips, depositing electrically insulating layer on active surface and flanks of at least one chip, and clearing at least one opening in the insulating layer |
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