JPH0350734A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH0350734A JPH0350734A JP1185356A JP18535689A JPH0350734A JP H0350734 A JPH0350734 A JP H0350734A JP 1185356 A JP1185356 A JP 1185356A JP 18535689 A JP18535689 A JP 18535689A JP H0350734 A JPH0350734 A JP H0350734A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bump
- metal film
- electrode
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 239000002313 adhesive film Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は集積回路の製造方法に関し、特に外部接続端子
である電極用金バンプを有する集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an integrated circuit, and more particularly to an integrated circuit having gold bumps for electrodes serving as external connection terminals.
〔従来の技術Ｊ
従来、集積回路の電極用金バンプの製造方法に関しては
数多くの提案がなされ、改良が加えられている。第２図
は、従来の電極用金バンプの製造工程を断面図により示
したものである。[Prior Art J] Conventionally, many proposals have been made and improvements have been made regarding methods of manufacturing gold bumps for electrodes of integrated circuits. FIG. 2 is a sectional view showing the manufacturing process of a conventional gold bump for electrodes.
従来は第２図に示すように、集積回路全面に前記第１金
属膜、第２金属膜、第３金属膜を順次形成し、その上に
、フォトレジスト膜を塗布する。Conventionally, as shown in FIG. 2, the first metal film, second metal film, and third metal film are sequentially formed on the entire surface of an integrated circuit, and a photoresist film is applied thereon.
このフォトレジスト膜の開口部は、パッシベーション開
口部全体を含む０次に、前記フォトレジスト膜をマスク
として電解メッキによりバンプ型電極を形成した後、前
記フォトレジスト膜を剥離除去する。レジスト膜除去後
、ウェットエツチングにより前記第３金属膜を除去し、
ドライエツチングによりバンプ型電極をマスク材として
前記第２金属膜を除去する。最後に、ウェットエツチン
グにより前記第２金属膜をマスク材として前記第３金属
膜を除去する。The opening of this photoresist film includes the entire passivation opening, and after forming a bump type electrode by electrolytic plating using the photoresist film as a mask, the photoresist film is peeled off. After removing the resist film, removing the third metal film by wet etching,
The second metal film is removed by dry etching using the bump type electrode as a mask material. Finally, the third metal film is removed by wet etching using the second metal film as a mask material.
この様に形成された集積回路では、以下に示す欠点があ
った。The integrated circuit formed in this manner has the following drawbacks.
まず、ウェットエツチングを用いる製造方法であるため
、過剰エツチングや電池反応によりサイドエッチが生じ
、バンプ型電極の密着強度不良が発生する。First, since the manufacturing method uses wet etching, side etching occurs due to excessive etching and battery reaction, resulting in poor adhesion of the bump type electrode.
また、フォトレジストを塗布し開口部を形成する工程に
おいて、フォトレジスト膜の開口部がパッシベーション
開口部全体を含んで形成されるため、前記フォトレジス
ト膜をマスクとして形成されるバンプ型電極は、アルミ
パッド上のパッシベーションを一部含んだ部分を下地と
して形成される。この構造では、外部引出電極との接合
の際、大きな熱的１機械的ダメージを受けると、パッシ
ベーションにクラックが入ってしまったり、アルミパッ
ド下の酸化膜やシリコン基板にクラックが生じ、基板か
らバンプ型電極が剥離してしまう問題があった。In addition, in the process of applying photoresist and forming an opening, the opening of the photoresist film is formed to include the entire passivation opening, so the bump-type electrode formed using the photoresist film as a mask is made of aluminum. It is formed using a portion of the pad that includes part of the passivation as a base. If this structure is subjected to large thermal or mechanical damage when bonding with the external lead electrode, cracks may appear in the passivation, cracks may occur in the oxide film under the aluminum pad or the silicon substrate, and bumps may be removed from the substrate. There was a problem that the mold electrode would peel off.
〔発明が解決しようとする課題１
本発明は、前記従来技術の欠点を解消しようとするもの
であり、密着強度が高く、高い実装安定性を有するバン
プ型電極を、簡便な工程で形成できる集積回路の製造方
法を提供する事にある。[Problem to be Solved by the Invention 1] The present invention aims to solve the drawbacks of the prior art described above, and is an integrated method that can form bump-type electrodes with high adhesion strength and high mounting stability through a simple process. The purpose is to provide a method for manufacturing circuits.
［課題を解決するための手段］
集積回路の電極パッド上にバンプ型電極を形成する方法
において、
（ａ）集積回路全面に、密着層としての第１金属膜、相
互拡散バリア膜としての第２金属膜および電解メッキの
下地電極としての第３金属膜とを順次形成する第１の工
程と。[Means for Solving the Problems] In a method for forming bump-type electrodes on electrode pads of an integrated circuit, (a) a first metal film as an adhesion layer and a second metal film as an interdiffusion barrier film are formed on the entire surface of the integrated circuit; a first step of sequentially forming a metal film and a third metal film as a base electrode for electrolytic plating;
（ｂ）前記金属膜上に、フォトレジスト膜を形成する工
程において、その開口部がパッシベーション開口部の内
部に形成されるようにする第２の工程と。(b) a second step of forming a photoresist film on the metal film, the opening of which is formed inside a passivation opening;
（ｃ）前記フォトレジスト膜をマスクとし、前記第３金
属膜を電極として電解メッキを行い、キノコ状のバンプ
型電極の外周部がパッシベーション開口部の外側まで形
成されるようにする第３の工程と、
（ｄ）前記フォトレジスト膜を剥離除去する第４の工程
と、
（ｅ）前記バンプ型電極をエツチングのマスク材として
、前記第１金属膜、第２基金属膜、第３金属膜を自己整
合的に乾式エツチング除去する第５の工程
から成ることを特徴とする、集積回路の製造方法。(c) A third step of performing electrolytic plating using the photoresist film as a mask and the third metal film as an electrode so that the outer periphery of the mushroom-shaped bump-type electrode is formed to the outside of the passivation opening. (d) a fourth step of peeling and removing the photoresist film; (e) using the bump type electrode as an etching mask material, removing the first metal film, second base metal film, and third metal film; A method for manufacturing an integrated circuit, comprising a fifth step of dry etching removal in a self-aligned manner.
〔実 施 例１
以下、本発明の実施例について、図面を参り、召して説
明する。[Embodiment 1] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の詳細な説明するための
工程順に示した断面図である。FIGS. 1(a) to 1(e) are sectional views showing the steps of the present invention in detail for explaining the present invention.
第１図（ａ）に示すように、拡散、配線、絶縁膜工程の
終了した集積回路表面のパッシベーション膜１１および
電極パッド１２の上に密着層として、Ｏ，ｌｕｍ 〜０
．２ｕｍのＴｉ膜１３と相互拡散バリア膜として、０．
１μｍ〜０．２μｍのｐｔ膜１４と、メッキ下地層とし
て、Ｏ，ｌｕｍ〜０．３μｍのＡｕ膜１５を順次、スパ
ッタ法により形成する。As shown in FIG. 1(a), a layer of O, lum ~ 0 is applied as an adhesion layer on the passivation film 11 and electrode pad 12 on the surface of the integrated circuit after the diffusion, wiring, and insulating film processes have been completed.
．． A 2 um thick Ti film 13 and a 0.0 um thick Ti film 13 are used as a mutual diffusion barrier film.
A PT film 14 with a thickness of 1 μm to 0.2 μm and an Au film 15 with a thickness of 1 μm to 0.3 μm as a plating base layer are sequentially formed by sputtering.
次に、第１図（ｂ）に示すように、前記金属謹上にフォ
トレジスト被膜１６を塗布し、そのバンプ型電極形成用
の開口部を、パッシベーション開口部の内部に形成する
。Next, as shown in FIG. 1(b), a photoresist film 16 is applied on the metal substrate, and an opening for forming a bump type electrode is formed inside the passivation opening.
次に、第１図（ｃ）に示すように、フォトレジスト開口
部１７に電解Ａｕメッキにより１５〜３０μｍ厚のＡｕ
バンプ１８を形成する。Next, as shown in FIG. 1(c), the photoresist opening 17 is plated with Au to a thickness of 15 to 30 μm.
Bumps 18 are formed.
次に、第１図（ｄ）に示すように、フォトレジスト１６
を剥離液により除去する。Next, as shown in FIG. 1(d), the photoresist 16
is removed using a stripping solution.
次に、第１図（ｅ）に示すように、イオンミーノング、
スパッタエツチング等の乾式エツチングにより、前記Ａ
ｕバンプ１８をマスクとして、前記Ｔｉ膜１３、Ｐｔ１
ｌｉ１４、Ａｕ１１！１５をエツチング除去する。Next, as shown in FIG. 1(e), ion meenong,
By dry etching such as sputter etching, the above A
Using the u bump 18 as a mask, the Ti film 13 and Pt1
Li14 and Au11!15 are removed by etching.
以上の工程により、金バンプ電極が集積回路上に形成さ
れる。Through the above steps, gold bump electrodes are formed on the integrated circuit.
このようにして形成された金バンプ電極は、密着強度が
高く、実装時の熱的、機械的応力がアルミパッドで吸収
される構造になっているため、高い実装安定性を有する
。The gold bump electrode formed in this manner has high adhesion strength and has a structure in which thermal and mechanical stress during mounting is absorbed by the aluminum pad, so it has high mounting stability.
［発明の効果］
以上説明したように、本発明によれば、密着強度に優れ
、高い実装安定性を有するバンプ型電極を容易に製造す
ることができる。[Effects of the Invention] As described above, according to the present invention, a bump-type electrode having excellent adhesion strength and high mounting stability can be easily manufactured.
第１図（ａ）〜（ｅ）は、本発明の詳細な説明するため
の工程順に示した断面図である。
第２図（ａ）〜（ｆ）は、従来技術を説明するための工
程順に示した断面図である。
１０ ・
１１ ・
ｌ ２ ・
ｌ ３ ・
１４ ・
ｌ ５ ・
ｌ ６ ・
１７ ・
１８ ・
２０ ・
２ ｌ ・
２２ ・
２３ ・
２４ ・
２５ ・
２６ ・
・集積回路基板
・パッシベーション膜
・電極パッド
・Ｔｉ１ｌ＠
・ｐｔ膜
・Ａｕ膜
・フォトレジスト膜
・開口部
・Ａｕバンプ
・集積回路基板
・パッシベーション用莫
・電極パッド
・Ｔｉ膜
・ｐｔ膿
・Ａｕ膜
・フォトレジスト膜
２７ ・
・Ａｕバンプ
以
上FIGS. 1(a) to 1(e) are cross-sectional views shown in order of steps for explaining the present invention in detail. FIGS. 2(a) to 2(f) are cross-sectional views shown in the order of steps for explaining the prior art. 10 ・ 11 ・ l 2 ・ l 3 ・ 14 ・ l 5 ・ l 6 ・ 17 ・ 18 ・ 20 ・ 2 l ・ 22 ・ 23 ・ 24 ・ 25 ・ 26 ・ ・Integrated circuit board・Passivation film・Electrode pad・Ti1l@ - PT film, Au film, photoresist film, opening, Au bump, integrated circuit board, passivation film, electrode pad, Ti film, PT pus, Au film, photoresist film 27 ・ ・More than Au bump
Claims (1)
において、 （ａ）集積回路全面に、密着膜としての第１金属膜、相
互拡散バリア膜としての第２金属膜および電解メッキの
下地電極としての第３金属膜とを順次形成する第１の工
程と、 （ｂ）前記金属膜上に、フォトレジスト膜を形成する工
程において、その開口部がパッシベーション開口部の内
部に形成されるようにする第２の工程と、 （ｃ）前記フォトレジスト膜をマスクとし、前記第３金
属膜を電極として電解メッキを行い、キノコ状のバンプ
型電極の外周部がパッシベーション開口部の外側まで形
成されるようにする第３の工程と、 （ｄ）前記フォトレジスト膜を剥離除去する第４の工程
と、 （ｅ）前記バンプ型電極をエッチングのマスク材として
、前記第１金属膜、第２金属膜、第３金属膜を自己整合
的に乾式エッチング除去する第５の工程 から成ることを特徴とする集積回路の製造方法。[Claims] A method for forming a bump-type electrode on an electrode pad of an integrated circuit, comprising: (a) a first metal film as an adhesive film, a second metal film as an interdiffusion barrier film, and a second metal film as an interdiffusion barrier film; a first step of sequentially forming a third metal film as a base electrode for electrolytic plating, and (b) a step of forming a photoresist film on the metal film, so that the opening is inside the passivation opening. (c) electroplating is performed using the photoresist film as a mask and the third metal film as an electrode, so that the outer periphery of the mushroom-shaped bump-shaped electrode is in the passivation opening. (d) a fourth step of peeling and removing the photoresist film; (e) using the bump-type electrode as an etching mask material to remove the first metal film; , a fifth step of removing the second metal film and the third metal film by dry etching in a self-aligned manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185356A JPH0350734A (en) | 1989-07-18 | 1989-07-18 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185356A JPH0350734A (en) | 1989-07-18 | 1989-07-18 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350734A true JPH0350734A (en) | 1991-03-05 |
Family
ID=16169356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1185356A Pending JPH0350734A (en) | 1989-07-18 | 1989-07-18 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350734A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2707797A1 (en) * | 1993-07-15 | 1995-01-20 | Samsung Electronics Co Ltd | Method of manufacturing bumps for chips. |
| JP2002170840A (en) * | 2000-09-25 | 2002-06-14 | Ibiden Co Ltd | Manufacturing method of semiconductor device and multi-layer printed circuit board including the same |
| US7842887B2 (en) | 2000-02-25 | 2010-11-30 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| US7852634B2 (en) | 2000-09-25 | 2010-12-14 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
-
1989
- 1989-07-18 JP JP1185356A patent/JPH0350734A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2707797A1 (en) * | 1993-07-15 | 1995-01-20 | Samsung Electronics Co Ltd | Method of manufacturing bumps for chips. |
| US7842887B2 (en) | 2000-02-25 | 2010-11-30 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| US8079142B2 (en) | 2000-02-25 | 2011-12-20 | Ibiden Co., Ltd. | Printed circuit board manufacturing method |
| US8186045B2 (en) | 2000-02-25 | 2012-05-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
| US8438727B2 (en) | 2000-02-25 | 2013-05-14 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
| JP2002170840A (en) * | 2000-09-25 | 2002-06-14 | Ibiden Co Ltd | Manufacturing method of semiconductor device and multi-layer printed circuit board including the same |
| US7852634B2 (en) | 2000-09-25 | 2010-12-14 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7855342B2 (en) | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7893360B2 (en) | 2000-09-25 | 2011-02-22 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7908745B2 (en) | 2000-09-25 | 2011-03-22 | Ibiden Co., Ltd. | Method of manufacturing multi-layer printed circuit board |
| US7999387B2 (en) | 2000-09-25 | 2011-08-16 | Ibiden Co., Ltd. | Semiconductor element connected to printed circuit board |
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