JPS6117144B2 - - Google Patents
Info
- Publication number
- JPS6117144B2 JPS6117144B2 JP55104476A JP10447680A JPS6117144B2 JP S6117144 B2 JPS6117144 B2 JP S6117144B2 JP 55104476 A JP55104476 A JP 55104476A JP 10447680 A JP10447680 A JP 10447680A JP S6117144 B2 JPS6117144 B2 JP S6117144B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon
- stepped portion
- etching
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910021426 porous silicon Inorganic materials 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000007743 anodising Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 20
- 238000002955 isolation Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は素子分離技術を改善した半導体装置の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device with improved element isolation technology.
近年、半導体装置は素子寸法縮少技術の発達に
伴ない高密度高集積化が進んで来た。例えばゲー
ト長縮少に伴なつて拡散不純物を拡散係数の大き
いリンから拡散係数の小さい砒素へ転換し、しか
もその導入方法が拡散法から制御が容易なイオン
法入法が採られるようになつて来た。一方、素子
分離技術は選択酸化法が主流を占め、窒化膜と酸
化膜の膜厚比を始め、酸化条件等の改良が加えら
れている。 In recent years, semiconductor devices have become more densely integrated with the development of element size reduction technology. For example, as gate lengths have been reduced, the diffusion impurity has been changed from phosphorus, which has a large diffusion coefficient, to arsenic, which has a small diffusion coefficient, and the introduction method has changed from the diffusion method to the easily controlled ion method. It's here. On the other hand, the mainstream of device isolation technology is selective oxidation, and improvements have been made in the thickness ratio of the nitride film and the oxide film, as well as in the oxidation conditions.
従来の素子分離法を用いてMOS型半導体を製
造する方法について第１図を参照して説明する。 A method of manufacturing a MOS type semiconductor using a conventional element isolation method will be explained with reference to FIG.
半導体基板１の上にシリコン酸化膜２を約1000
Å成長させ、更にその上に耐酸化性マスクとして
シリコン窒化膜（Si3N4）を約3000Å形成させる。
次に写真蝕刻技術（フオトエツチング）により、
シリコン窒化膜にパターン形成を行つて素子分離
領域に相当するシリコン窒化膜パターン３を形成
する（第１図Ａ図示）。次いでエツチング除去し
た部分から半導体基板１にイオン注入を行なつて
フイールド反転防止層４を形成する。 Approximately 1,000 silicon oxide films 2 are deposited on the semiconductor substrate 1.
A silicon nitride film (Si 3 N 4 ) of about 3000 Å is formed thereon as an oxidation-resistant mask.
Next, using photo-etching technology,
The silicon nitride film is patterned to form a silicon nitride film pattern 3 corresponding to an element isolation region (as shown in FIG. 1A). Next, ions are implanted into the semiconductor substrate 1 from the etched portion to form a field inversion prevention layer 4.
次に熱酸化を行なつて第１図Ｂに示すようにフ
イールド酸化膜５を形成する。このとき、形成さ
れるフイールド酸化膜５の周縁はシリコン窒化膜
パターン３の下側に喰い込んだ状態となる。この
喰いみ量は通常１〜２μｍであるがシリコン酸化
膜２が薄く、シリコン窒化膜パターン３が厚い
程、少なくなる傾向にある。 Next, thermal oxidation is performed to form a field oxide film 5 as shown in FIG. 1B. At this time, the peripheral edge of the field oxide film 5 to be formed digs into the underside of the silicon nitride film pattern 3. This amount of bite is normally 1 to 2 μm, but tends to decrease as the silicon oxide film 2 becomes thinner and the silicon nitride film pattern 3 becomes thicker.
次にシリコン窒化膜パターン３とシリコン酸化
膜２とを除去して、第１図Ｃに示すようにフイー
ルド酸化膜５からなる素子分離領域６と、これに
より分離された素子形成領域７とが形成される。 Next, the silicon nitride film pattern 3 and the silicon oxide film 2 are removed, and as shown in FIG. be done.
以下、通常の半導体素子技術に従つて、第１図
Ｄに示すような半導体素子を製造する。なお図に
おいて８はゲート酸化膜、９はこのゲート酸化膜
８の上に形成された多結晶シリコンからなるゲー
ト電極、１０１，１０２はソース・ドレイン領
域、１１は層間絶縁膜、１２はアルミニウム配
線、１３は保護膜である。 Thereafter, a semiconductor device as shown in FIG. 1D is manufactured according to ordinary semiconductor device technology. In the figure, 8 is a gate oxide film, 9 is a gate electrode made of polycrystalline silicon formed on this gate oxide film 8, 10 1 and 10 2 are source/drain regions, 11 is an interlayer insulating film, and 12 is aluminum. The wiring 13 is a protective film.
しかしながら、従来の方法では素子分離領域６
やソース・ドレイン領域１０１，１０２を小さく
形成して集積度を向上させる上で次のような問題
がある。 However, in the conventional method, the element isolation region 6
There are the following problems in improving the degree of integration by forming the source/drain regions 10 1 and 10 2 small.
第１に素子分離領域６となるフイールド酸化膜
５は、形成時において、必然的にシリコン窒化膜
パターン３への喰い込みがあるため、パターン変
換量が１〜２μｍとなり、これ以下の寸法に形成
することができず集積度向上の最大のネツクとな
つていた。 First, the field oxide film 5, which becomes the element isolation region 6, inevitably bites into the silicon nitride film pattern 3 during formation, so the pattern conversion amount is 1 to 2 μm, and the field oxide film 5 is formed to a size smaller than this. This has become the biggest obstacle to increasing the degree of integration.
第２に素子分離領域６の寸法を小さく形成する
と、これにより分離されていた両側のソース・ド
レイン領域１０１，１０２が素子分離領域６の下
部に広がつて短絡してしまう。 Secondly, if the dimensions of the element isolation region 6 are made small, the source/drain regions 10 1 and 10 2 on both sides, which were separated by this, spread to the lower part of the element isolation region 6 and become short-circuited.
更に第３に、ソース・ドレイン領域１０１，１
０２を狭くすると従来余り問題となつていなかつ
たイオン注入で形成されたフイールド反転防止層
４からの不純物の影響が無視できなくなるなどの
問題があつた。 Furthermore, thirdly, source/drain regions 10 1 , 1
When 02 is made narrower, problems arise, such as the influence of impurities from the field inversion prevention layer 4 formed by ion implantation, which has not been a problem in the past, cannot be ignored.
本発明は上記事情を考慮してなされたもので、
従来平面的に形成されていたフイールド酸化膜を
段差部の内側壁に垂直に形成し、素子分離領域の
平面的な寸法を零として、高密度高集積化を可能
にした半導体装置の製造方法を提供するものであ
る。 The present invention was made in consideration of the above circumstances, and
A method for manufacturing semiconductor devices that enables high-density and high-integration by forming a field oxide film, which has conventionally been formed in a planar manner, perpendicularly to the inner wall of the stepped portion and reducing the planar dimension of the element isolation region to zero. This is what we provide.
すなわち本発明はｐ型シリコンからなる半導体
基板上に、所定のパターンを有する耐エツチング
マスクを設ける工程と、前記基板をエツチングし
て段差部を形成する工程と、前記基板にプロトン
をイオン注入して段差部の内側壁以外にドナー層
を形成する工程と、基板シリコンを陽極化成して
段差部の内側壁に多孔質シリコンを選択的に形成
する工程と、前記多孔質シリコンを熱酸化してフ
イールド酸化膜とする工程とからなることを特徴
とするものである。 That is, the present invention includes the steps of providing an etching-resistant mask having a predetermined pattern on a semiconductor substrate made of p-type silicon, etching the substrate to form a stepped portion, and implanting proton ions into the substrate. A step of forming a donor layer on areas other than the inner wall of the stepped portion, a step of anodizing the substrate silicon to selectively form porous silicon on the inner wall of the stepped portion, and thermally oxidizing the porous silicon to form a field. This method is characterized by comprising a step of forming an oxide film.
以下本発明を図面に示す実施例を参照して詳細
に説明する。 The present invention will be described in detail below with reference to embodiments shown in the drawings.
第２図Ａ乃至同図１は、MOS型半導体装置の
製造に適用した場合の本発明の一実施例を順次工
程に従つて示すものである。 FIG. 2A to FIG. 1 show one embodiment of the present invention applied to the manufacture of a MOS type semiconductor device, step by step.
先ず第２図Ａに示すようにｐ型シリコンからな
る半導体基板１上に、厚さ約１μｍのシリコン酸
化膜２を形成する。次にこのシリコン酸化膜２の
表面にレジスト膜１４を塗布し、フオトエツチン
グにより所定のパターンを形成する。この後、プ
ラズマ弗酸（HF）ガスエツチング技術を用いて
レジスト膜１４の直下にあるシリコン酸化膜２を
除去する。このプラズマ弗酸（HF）ガスエツチ
ングはレジスト膜１４中に弗化水素を取り込み、
これがシリコン酸化膜２をエツチングし、仮想線
で示す状態から実線で示す状態にレジスト膜１４
が下降しながら、シリコン酸化膜２を垂直にエツ
チング除去するものである。 First, as shown in FIG. 2A, a silicon oxide film 2 having a thickness of about 1 μm is formed on a semiconductor substrate 1 made of p-type silicon. Next, a resist film 14 is applied to the surface of this silicon oxide film 2, and a predetermined pattern is formed by photo-etching. Thereafter, the silicon oxide film 2 directly under the resist film 14 is removed using plasma hydrofluoric acid (HF) gas etching technology. This plasma hydrofluoric acid (HF) gas etching incorporates hydrogen fluoride into the resist film 14,
This etches the silicon oxide film 2, changing the resist film 14 from the state shown by the virtual line to the state shown by the solid line.
The silicon oxide film 2 is vertically etched and removed while the wafer is lowered.
次にレジスト膜１４を除去した後、パターニン
グされたシリコン酸化膜２を耐エツチングマスク
としてリアクテイブイオンエツチング（RIE）を
用いて、エツチングを行ない同図Ｂに示すように
半導体基板１を溝状にエツチング除去して深さ約
１μｍの段差部１５を形成する。この場合のエツ
チングは方向性を持つているため、段差部１５の
内側壁１５ａは垂直に鋭く形成される。 Next, after removing the resist film 14, etching is performed using reactive ion etching (RIE) using the patterned silicon oxide film 2 as an etching-resistant mask to form a groove in the semiconductor substrate 1 as shown in FIG. Etching is performed to form a stepped portion 15 having a depth of about 1 μm. Since the etching in this case has directionality, the inner wall 15a of the stepped portion 15 is formed vertically and sharply.
次いで耐エツチングマスクとして用いたシリコ
ン酸化膜２を除去して基板表面を露出させた後、
プロトンを半導体基板１に対して垂直にイオン注
入し、半導体基板１の上面および、段差部１５の
底面にｎ型としてのドナー層１６を形成し、同図
Ｃの状態にする。このときイオン注入は方向性を
持つているので、段差部１５の内側壁１５ａには
イオンが注入されず、ｐ型シリコンのままに維持
される。 Next, after removing the silicon oxide film 2 used as an etching-resistant mask to expose the substrate surface,
Protons are ion-implanted perpendicularly to the semiconductor substrate 1 to form an n-type donor layer 16 on the top surface of the semiconductor substrate 1 and the bottom surface of the stepped portion 15, resulting in the state shown in FIG. At this time, since the ion implantation has directionality, no ions are implanted into the inner wall 15a of the stepped portion 15, and the p-type silicon remains as it is.
次に陽極化成を行なう。この時、半導体基板１
主面のドナー層１６には通電されず、陽極化成は
行なわれない。一方、ドナー層１６が形成され
ず、ｐ型のままである段差部１５のｐ型の内側壁
１５ａは選択的に通電されて陽極化成が行なわ
れ、同図Ｄに示すように多孔質シリコン層１７が
形成される。 Next, anodization is performed. At this time, semiconductor substrate 1
No current is applied to the donor layer 16 on the main surface, and anodization is not performed. On the other hand, the p-type inner wall 15a of the stepped portion 15, on which the donor layer 16 is not formed and remains p-type, is selectively energized and anodized, forming a porous silicon layer as shown in FIG. 17 is formed.
次いで、酸素と水蒸気雰囲気による1000℃のウ
エツト熱酸化を施した。この時段差部１５の内側
壁１５ａに形成した多孔質シリコン層１７が他の
露出する半導体基板１（ドナー層１６）より酸化
レートが速いために、該多孔質シリコン層１７に
は十分厚いシリコン酸化膜が、これ以外の露出す
る部分には薄いシリコン酸化膜が、成長された。
また、ドナーキラー効果を同時に受けてドナー層
１６はｐ型シリコンに戻る。つづいて、半導体基
板１を全面エツチングした。この時、段差部１５
の内側壁１５ａ以外の薄い酸化膜が除去されて、
該内側壁１５ａに厚い酸化膜が残りフイールド酸
化膜５で構成された素子分離領域６が形成される
と共に、半導体基板１の表面及び段差部１５の底
面に素子形成領域７ａ，７ｂ，７ｃが形成された
（同図Ｅ図示）。 Next, wet thermal oxidation was performed at 1000°C in an oxygen and water vapor atmosphere. At this time, since the porous silicon layer 17 formed on the inner wall 15a of the stepped portion 15 has a faster oxidation rate than the other exposed semiconductor substrate 1 (donor layer 16), the porous silicon layer 17 has a sufficiently thick silicon oxide layer. A thin silicon oxide layer was grown on the remaining exposed portions of the membrane.
Furthermore, the donor layer 16 returns to p-type silicon due to the donor killer effect. Subsequently, the entire surface of the semiconductor substrate 1 was etched. At this time, the stepped portion 15
The thin oxide film other than the inner wall 15a is removed,
A thick oxide film remains on the inner wall 15a, and an element isolation region 6 made of the field oxide film 5 is formed, and element formation regions 7a, 7b, and 7c are formed on the surface of the semiconductor substrate 1 and the bottom of the stepped portion 15. (as shown in Figure E).
以下、通常の半導体技術を用いて、素子形成領
域７ａ，７ｂ，７ｃの表面に、ゲート酸化膜８、
多結晶シリコンゲート電極９を形成し、フオトエ
ツチングによりパターニングして同図Ｆの状態と
する。次に同図Ｇの如く、砒素を注入してn+型
のソース・ドレイン領域１０１，１０２を形成す
る。次いで同図Ｈに示すように層間絶縁膜１１お
よびアルミニウム配線１２を行なつた後、更に全
面に保護膜１３を設けて、同図Ｉに示すように１
層ポリシリコンMOS半導体装置を製造する。 Thereafter, a gate oxide film 8, a gate oxide film 8, a
A polycrystalline silicon gate electrode 9 is formed and patterned by photoetching to obtain the state shown in FIG. Next, as shown in Figure G, arsenic is implanted to form n + type source/drain regions 10 1 and 10 2 . Next, after forming an interlayer insulating film 11 and aluminum wiring 12 as shown in FIG.
A layered polysilicon MOS semiconductor device is manufactured.
従つて上記方法によれば段差部１５の内側壁１
５ａに、素子分離領域６となるフイールド酸化膜
５を垂直方向に形成してあるので、従来の如く平
面的に形成したものに比べて素子分離領域６の平
面的な寸法を零にすることができる。また、フイ
ールド酸化膜５の大きさは、素子形成領域７ａ，
７ｂ，７ｃと独立して決めることができるので、
素子設計も容易である。更に、プロトンのイオン
注入により形成されたｎ型のドナー層１６は650
℃以上の熱処理工程（本実施例では1000℃の熱酸
化工程）で容易にｐ型に戻るため、その後の
MOSトランジスタの製造に際し、支障なくn+型
のソース・ドレイン領域１０１，１０２を形成で
きる。 Therefore, according to the above method, the inner wall 1 of the stepped portion 15
5a, the field oxide film 5, which becomes the element isolation region 6, is formed in the vertical direction, so that the planar dimension of the element isolation region 6 can be reduced to zero compared to the conventional case where the field oxide film 5 is formed planarly. can. Further, the size of the field oxide film 5 is determined by the size of the element formation region 7a,
7b and 7c can be determined independently, so
Element design is also easy. Furthermore, the n-type donor layer 16 formed by ion implantation of protons is 650
Because it easily reverts to p-type during a heat treatment process at temperatures above ℃ (1000℃ thermal oxidation process in this example), subsequent
When manufacturing a MOS transistor, n + type source/drain regions 10 1 and 10 2 can be formed without any problem.
なお、上記実施例では耐エツチング性マスクと
してシリコン酸化膜２を用いた場合について示し
たが、この他にレジスト膜、シリコン窒化膜を用
いても良く、またこれらを複合して多層に形成し
たものでも良い。 In addition, although the above embodiment shows the case where the silicon oxide film 2 is used as the etching-resistant mask, a resist film or a silicon nitride film may also be used, or a composite of these may be formed into a multilayer structure. But it's okay.
また多孔質シリコン層１７を熱酸化してフイー
ルド酸化膜５を形成する工程で、上記の如く、基
板全面を酸化する方法に限らず、必要な部分のみ
酸化しても良い。また熱酸化をドナー層１６がｐ
型シリコンに戻らない650℃より低い温度で行な
う場合、ドナー層１６をｐ型シリコンに戻す工程
は別個に行なつても良い。 Further, in the step of thermally oxidizing the porous silicon layer 17 to form the field oxide film 5, the method is not limited to oxidizing the entire surface of the substrate as described above, but only necessary portions may be oxidized. In addition, thermal oxidation is caused by the donor layer 16 p
When carried out at a temperature lower than 650° C. at which the donor layer 16 does not return to p-type silicon, the step of returning the donor layer 16 to p-type silicon may be performed separately.
更に上記実施例では１層ポリシリコンMOS型
半導体装置を製造する場合を例に挙げて説明した
が、本発明方法はフイールド酸化膜を素子分離に
用いる全ての素子形成方法に適用することができ
る。 Furthermore, although the above embodiments have been described with reference to the case of manufacturing a single-layer polysilicon MOS type semiconductor device, the method of the present invention can be applied to all device formation methods that use field oxide films for device isolation.
以上説明した如く、本発明に係わる半導体装置
の製造方法によればフイールド酸化膜を基板表面
に設けた段差部の内側壁に垂直に形成し、素子分
離領域の平面的な寸法を零として、素子の高密度
集積化を図ることができるものである。 As explained above, according to the method for manufacturing a semiconductor device according to the present invention, a field oxide film is formed perpendicularly to the inner wall of a stepped portion provided on a substrate surface, the planar dimension of the element isolation region is set to zero, and the element It is possible to achieve high-density integration.
第１図Ａ乃至同図Ｄは従来方法により製造する
工程を順次示す断面図、第２図Ａ乃至同図Ｉは本
発明をMOS型半導体装置に適用した場合の一実
施を順次工程に従つて示す断面図である。
１……半導体基板、２……シリコン酸化膜、３
……シリコン窒化膜、５……フイールド酸化膜、
６……素子分離領域、７，７ａ，７ｂ，７ｃ……
素子形成領域、１０１，１０２……n+型ソー
ス・ドレイン領域、１５……段差部、１６……ド
ナー層、１７……多孔質シリコン層。
1A to 1D are cross-sectional views sequentially showing the steps of manufacturing according to the conventional method, and FIGS. 2A to 2I are sectional views sequentially showing the steps of manufacturing the present invention when applied to a MOS type semiconductor device. FIG. 1...Semiconductor substrate, 2...Silicon oxide film, 3
...Silicon nitride film, 5...Field oxide film,
6... Element isolation region, 7, 7a, 7b, 7c...
Element formation region, 10 1 , 10 2 ... n + type source/drain region, 15 ... step portion, 16 ... donor layer, 17 ... porous silicon layer.
Claims (1)
のパターンを有する耐エツチングマスクを設ける
工程と、前記基板をエツチングして段差部を形成
する工程と、前記基板にプロトンをイオン注入し
て段差部の内側壁以外にドナー層を形成する工程
と、基板シリコンを陽極化成して段差部の内側壁
に多孔質シリコンを選択的に形成する工程と、前
記多孔質シリコン熱酸化してフイールド酸化膜と
する工程とからなることを特徴とする半導体装置
の製造方法。 ２ 熱酸化を650℃以上の温度で行ない、熱酸化
と同時にドナー層をｐ型シリコンに戻すことを特
徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。[Claims] 1. A step of providing an etching-resistant mask having a predetermined pattern on a semiconductor substrate made of p-type silicon, a step of etching the substrate to form a stepped portion, and a step of etching the substrate with proton ions. a step of implanting a donor layer on areas other than the inner wall of the stepped portion; a step of anodizing the substrate silicon to selectively form porous silicon on the inner wall of the stepped portion; and thermal oxidation of the porous silicon. A method for manufacturing a semiconductor device, comprising the step of forming a field oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, characterized in that thermal oxidation is performed at a temperature of 650° C. or higher, and the donor layer is returned to p-type silicon at the same time as the thermal oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10447680A JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10447680A JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5730342A JPS5730342A (en) | 1982-02-18 |
| JPS6117144B2 true JPS6117144B2 (en) | 1986-05-06 |
Family
ID=14381616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10447680A Granted JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5730342A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6386467A (en) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | Semiconductor device |
| JP2007294857A (en) * | 2006-03-28 | 2007-11-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
-
1980
- 1980-07-30 JP JP10447680A patent/JPS5730342A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5730342A (en) | 1982-02-18 |
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