JPS6115834U - flip-flop circuit - Google Patents
flip-flop circuitInfo
- Publication number
- JPS6115834U JPS6115834U JP10079184U JP10079184U JPS6115834U JP S6115834 U JPS6115834 U JP S6115834U JP 10079184 U JP10079184 U JP 10079184U JP 10079184 U JP10079184 U JP 10079184U JP S6115834 U JPS6115834 U JP S6115834U
- Authority
- JP
- Japan
- Prior art keywords
- flop circuit
- flip
- logic
- gate
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は共に従来例を示す回路図、第３図
および第４図は共に本考案実施例を示す回路図である。
Ｓ， Ｓ， Ｒ， Ｒ・・・入力端子、Ｑ， Ｑ・・・
出力端子、Ｇ１，Ｇ′１，Ｇ，Ｇ′２・・・論理ゲート
、Ｒ，Ｒ２・・・抵抗、Ｃ，Ｃ２・・・コンデンサ。FIG. 1 and FIG. 2 are both circuit diagrams showing a conventional example, and FIG. 3 and FIG. 4 are both circuit diagrams showing an embodiment of the present invention. S, S, R, R...input terminal, Q, Q...
Output terminal, G1, G'1, G, G'2...Logic gate, R, R2...Resistor, C, C2...Capacitor.
Claims (1)
入力端子がその出力端子に接続された第２の論理ゲート
とを含み、上記笹１の論理ゲートの出力端子が抵抗を介
して第２の論理ゲートの一方の入力端子に接続されると
共にこの一方の入力端子がコンデンサを介して接地され
るように構成したことを特徴とするラリツプフロツプ回
路。 ２ 上記第１および第２の論理ゲートが共に負論理ＯＲ
ゲートから成ることを特徴とする実用新案登録請求の範
囲第１項記載のフリツプフロツプ回路。 ３ 上記第１および第２の論理ゲートが共に正論理ＮＯ
Ｒゲートから成ることを特徴とする実用新案登録請求の
範囲第１項記載のフリップフロツプ回路。[Claims for Utility Model Registration] 1 The logic gate of Sasa 1 includes a first logic gate and a second logic gate in which one input terminal of the first logic gate is connected to its output terminal. 1. A rip-flop circuit characterized in that an output terminal is connected to one input terminal of a second logic gate via a resistor, and this one input terminal is grounded via a capacitor. 2 The first and second logic gates are both negative logic OR
A flip-flop circuit according to claim 1, characterized in that the flip-flop circuit comprises a gate. 3 The first and second logic gates are both positive logic NO.
The flip-flop circuit according to claim 1, characterized in that the flip-flop circuit comprises an R gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10079184U JPS6115834U (en) | 1984-07-04 | 1984-07-04 | flip-flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10079184U JPS6115834U (en) | 1984-07-04 | 1984-07-04 | flip-flop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115834U true JPS6115834U (en) | 1986-01-29 |
Family
ID=30660234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10079184U Pending JPS6115834U (en) | 1984-07-04 | 1984-07-04 | flip-flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115834U (en) |
-
1984
- 1984-07-04 JP JP10079184U patent/JPS6115834U/en active Pending
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