JPS5883838U - gate control circuit - Google Patents
gate control circuitInfo
- Publication number
- JPS5883838U JPS5883838U JP17847181U JP17847181U JPS5883838U JP S5883838 U JPS5883838 U JP S5883838U JP 17847181 U JP17847181 U JP 17847181U JP 17847181 U JP17847181 U JP 17847181U JP S5883838 U JPS5883838 U JP S5883838U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- gate control
- integrated circuit
- gate
- gate integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
−第1図は従来のゲート制御回路の一例を示す回−略図
、第2図は本考案によるゲート制御回路のm: 実施
例を示す回路図、第3図はゲート集積回路の巳 出力
段の一例を示す回路図である。
3 IC・・・・・・ゲート集積回路、Q□・曲
・トランジスタ、hc・・・・・・コンデンサ、■N□
〜IN4・・・・・・入力端、CIN・・・・・・制御
入力端、0UT1〜OUT、・・・・・・出力端。- Fig. 1 is a circuit diagram showing an example of a conventional gate control circuit, Fig. 2 is a circuit diagram showing an embodiment of the gate control circuit according to the present invention, and Fig. 3 is a circuit diagram showing an example of the gate integrated circuit. FIG. 2 is a circuit diagram showing an example. 3 IC......gate integrated circuit, Q□・curve・transistor, hc......capacitor, ■N□
~IN4...Input end, CIN...Control input end, 0UT1~OUT,...Output end.
Claims (1)
するゲート集積回路に於いて、前記ゲート集積回路の出
力段の共通アース端とアース間をzスイッチング素子を
設け、このスイッチング素〕をオフ制御することによっ
て前記ゲート集積回協の各出力を“H“状態に保持する
ことを特徴とするゲート制御回路。In a gate integrated circuit having a pull-up resistor at the output stage or an external output end, a z switching element is provided between a common ground terminal of the output stage of the gate integrated circuit and the ground, and this switching element is turned off. A gate control circuit characterized in that each output of the gate integrated circuit is held in an "H" state by the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17847181U JPS5883838U (en) | 1981-11-30 | 1981-11-30 | gate control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17847181U JPS5883838U (en) | 1981-11-30 | 1981-11-30 | gate control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5883838U true JPS5883838U (en) | 1983-06-07 |
Family
ID=29973295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17847181U Pending JPS5883838U (en) | 1981-11-30 | 1981-11-30 | gate control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5883838U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5487160A (en) * | 1977-12-23 | 1979-07-11 | Nec Corp | Logic circuit |
-
1981
- 1981-11-30 JP JP17847181U patent/JPS5883838U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5487160A (en) * | 1977-12-23 | 1979-07-11 | Nec Corp | Logic circuit |
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