JPS61111543A - Etching method - Google Patents
Etching methodInfo
- Publication number
- JPS61111543A JPS61111543A JP23389284A JP23389284A JPS61111543A JP S61111543 A JPS61111543 A JP S61111543A JP 23389284 A JP23389284 A JP 23389284A JP 23389284 A JP23389284 A JP 23389284A JP S61111543 A JPS61111543 A JP S61111543A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etching
- etched
- photo resist
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 238000007598 dipping method Methods 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、半導体ウェハに所定のデバイスを形成する
場合に必要なエツチング方法に係り、特に、ウェットタ
イプのエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an etching method necessary for forming a predetermined device on a semiconductor wafer, and particularly to a wet type etching method.
（ロ）従来技術
一般にこの種のエツチング方法は、例えば半導体ウェハ
の表面に形成させたシリコン酸化膜或いは電極等をパタ
ーンニングする場合に利用されている。ここでは、前記
シリコン酸化膜をパターンニングする場合を例として説
明する。(b) Prior Art Generally, this type of etching method is used for patterning, for example, a silicon oxide film or electrodes formed on the surface of a semiconductor wafer. Here, the case of patterning the silicon oxide film will be explained as an example.
まず前記半導体ウェハの表面にシリコン酸化膜を成長さ
せ、ホトレジストの塗布・露光・現像工程を経て前記シ
リコン酸化膜のエツチングすべき部分以外をホトレジス
トで被覆した後、前記半導体ウェハを例えば弗化水素等
のエツチング液中に所定時間浸漬させることにより前記
シリコン酸化膜をパターンニングしている。即ち、従来
では一度のエツチングでもって完了させている。このと
き、前記シリコン酸化膜とホトレジストとの界面にエツ
チング液が回り込み、この部分からエツチング深さと比
例してサイドエツチングしてしまうという問題がある。First, a silicon oxide film is grown on the surface of the semiconductor wafer, and after a photoresist application, exposure, and development process, the silicon oxide film is coated with photoresist except for the portion to be etched. The silicon oxide film is patterned by immersing it in an etching solution for a predetermined period of time. That is, conventionally, etching is completed in one go. At this time, there is a problem in that the etching solution flows around the interface between the silicon oxide film and the photoresist, and side etching occurs from this part in proportion to the etching depth.
即ち、上記方法においては微細なパターンニングを行う
のは非常に困難であり、 ′製品として歩留りの低減
を招くこととなる。In other words, it is very difficult to perform fine patterning using the above method, which results in a reduction in the yield of the product.
（ハ）目的
この発明は、サイドエツチング量を減少せしめて微細な
パターンニングを可能とし、かつ、製品の歩留りを向上
しうるエツチング方法を提供することを目的としている
。(C) Objective The object of the present invention is to provide an etching method that enables fine patterning by reducing the amount of side etching and improves the yield of products.
（ニ）構成
この発明に係るエツチング方法の特徴とする処は、半導
体ウェハの表面の被エツチング部以外を覆ったホトレジ
ストをマスクとして前記被エツチング部を所定の深さま
でエツチングする第１のエツチング工程と、該被エツチ
ング部とホトレジストとを再密着せしめるように該半導
体ウェハを加熱するベーキング工程と、前記ベーキング
されたホトレジストをマスクとして前記残余の被エツチ
ング部を再度エツチングする第２のエツチング工程とを
具備したことにある。(d) Structure The etching method according to the present invention is characterized by a first etching step in which the etching target area is etched to a predetermined depth using a photoresist covering the surface of the semiconductor wafer other than the etching target area as a mask. , a baking step of heating the semiconductor wafer so as to bring the etched portion and photoresist into close contact again; and a second etching step of etching the remaining etched portion again using the baked photoresist as a mask. It's what I did.
（ポ）実施例
第１図はこの発明に係るエツチング方法の一実施例を示
す説明図であり、被エツチング層とじて本実施例ではシ
リコン酸化膜とする。同図を参考として以下説明する。(P) Embodiment FIG. 1 is an explanatory view showing an embodiment of the etching method according to the present invention, and the layer to be etched is a silicon oxide film in this embodiment. This will be explained below with reference to the same figure.
■ 半導体ウェハ１０の表面１１にシリコン酸化膜２０
を成長させる。このシリコン酸化膜２０のエツチングす
べき部分以外に通常の露光・現像工程を経てホトレジス
ト３０を被着させる（第１図（ａｌ参照）。■ Silicon oxide film 20 on the surface 11 of the semiconductor wafer 10
grow. A photoresist 30 is deposited on the silicon oxide film 20 other than the portion to be etched through a normal exposure and development process (see FIG. 1 (al)).
■ 例えば弗化水素等のエツチング液中に前記ホトレジ
スＩ・３０をマスクとした半導体ウェハ１０を浸漬させ
ることにより、シリコン酸化膜２０の膜厚の約５０％を
エツチングする（第１図（ｂ）参照）（第１のエツチン
グ工程）。(2) Etching approximately 50% of the thickness of the silicon oxide film 20 by immersing the semiconductor wafer 10 using the photoresist I-30 as a mask in an etching solution such as hydrogen fluoride (see FIG. 1(b)). Reference) (first etching step).
■ 前記半導体ウェハ１０を大量の純水にて洗浄し、乾
燥させる。(2) The semiconductor wafer 10 is washed with a large amount of pure water and dried.
■ 前記洗浄した半導体ウェハ１０を例えばホットプレ
ートの上に装着し、前記被着したホトレジストの種類に
応じて加熱温度および時間を設定するが２２本実施例で
は１４０℃程度で５分間位行うことにより、ホトレジス
ト３０とシリコン酸化膜２０との密着性を再度高める（
ベーキング工程）。なお、前記■の工程にて所定厚エツ
チングしたシリコン酸化膜２０上端に発生したサイドエ
ツチング部２１には、その上部に位置するホトレジスト
３０が変形して前記シリコン酸化膜２０のサイドエツチ
ング部２１を覆うようになる（第１図（Ｃ１参照）。(2) The cleaned semiconductor wafer 10 is mounted on, for example, a hot plate, and the heating temperature and time are set depending on the type of photoresist deposited.22 In this embodiment, the heating is performed at about 140° C. for about 5 minutes. , the adhesion between the photoresist 30 and the silicon oxide film 20 is increased again (
baking process). Incidentally, in the side-etched part 21 generated at the upper end of the silicon oxide film 20 etched to a predetermined thickness in the step (2) above, the photoresist 30 located above is deformed and covers the side-etched part 21 of the silicon oxide film 20. (see Figure 1 (C1)).
■ 前記ベーキングした半導体ウェハ１０を再度弗化水
素等のエツチング液中に浸漬させることにより、前記残
余のシリコン酸化膜２０を完全にエツチングさせる（第
１図（ｄｌ参照）（第２のエツチング工程）。(2) By immersing the baked semiconductor wafer 10 again in an etching solution such as hydrogen fluoride, the remaining silicon oxide film 20 is completely etched (see FIG. 1 (dl) (second etching step). .
上記の如くパターンニングされた半導体ウェハ１０は、
順次拡散および成長工程へと進む。The semiconductor wafer 10 patterned as described above is
Proceed sequentially to diffusion and growth steps.
なお、この発明は被エツチング部として上記実施例のも
のに限定されず、例えばアルミニウム等の電極および窒
化膜などをパターンニングさせる場合にも有効であるこ
とは言うまでもない。It goes without saying that the present invention is not limited to the portions to be etched that are described in the above-mentioned embodiments, but is also effective in patterning electrodes such as aluminum, nitride films, and the like.
また、上記実施例ではエツチング工程を２分割した場合
を示したが、これに限定されるものでなく、分割数を３
以上にしそれぞれのエツチング工程の間にベーキング工
程を介在させればサイドエツチング量を更に少な（する
ことができる。Furthermore, although the above embodiment shows the case where the etching process is divided into two, the etching process is not limited to this, and the number of divisions may be three.
By interposing a baking process between each etching process, the amount of side etching can be further reduced.
（へ）効果
この発明は、上記詳説したように、工・ノチング工程を
複数回に分けると共にその途中に、サイドエツチング部
をホトレジストで覆いかつホトレジストの密着性を良好
にするベーキング工程を介在させたので、全体のサイド
エツチング量を大幅に減少させることができ、よって微
細なパターンニングが可能となる。(f) Effects As detailed above, this invention divides the etching/notching process into multiple steps, and interposes a baking process in the middle to cover the side etched portion with photoresist and improve the adhesion of the photoresist. Therefore, the total amount of side etching can be significantly reduced, and fine patterning becomes possible.
第１図はこの発明に係るエツチング方法の一実施例を示
す説明図である。
１０・・・半導体ウェハ、１１・・・表面、２０・・・
シリコン酸化膜、２１・・・サイドエ・ノチング部、３
０・・・ホトレジスト。FIG. 1 is an explanatory diagram showing an embodiment of the etching method according to the present invention. 10... Semiconductor wafer, 11... Surface, 20...
Silicon oxide film, 21... side etching part, 3
0...Photoresist.
Claims (1)
たホトレジストをマスクとして前記被エッチング部を所
定の深さまでエッチングする第１のエッチング工程と、 該被エッチング部とホトレジストとを再密着せしめるよ
うに該半導体ウェハを加熱するベーキング工程と、 前記ベーキングされたホトレジストをマスクとして前記
残余の被エッチング部を再度エッチングする第２のエッ
チング工程とを具備したことを特徴とするエッチング方
法。(1) A first etching step of etching the etched part to a predetermined depth using a photoresist covering the surface of the semiconductor wafer other than the etched part as a mask, and bringing the etched part and the photoresist into close contact again. An etching method comprising: a baking step of heating the semiconductor wafer; and a second etching step of etching the remaining etched portion again using the baked photoresist as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23389284A JPS61111543A (en) | 1984-11-05 | 1984-11-05 | Etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23389284A JPS61111543A (en) | 1984-11-05 | 1984-11-05 | Etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61111543A true JPS61111543A (en) | 1986-05-29 |
Family
ID=16962197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23389284A Pending JPS61111543A (en) | 1984-11-05 | 1984-11-05 | Etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61111543A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05148339A (en) * | 1991-02-27 | 1993-06-15 | Bayer Ag | Hydrophilic olefinically unsaturated polyurethane and use of same as reactive emulsifier |
-
1984
- 1984-11-05 JP JP23389284A patent/JPS61111543A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05148339A (en) * | 1991-02-27 | 1993-06-15 | Bayer Ag | Hydrophilic olefinically unsaturated polyurethane and use of same as reactive emulsifier |
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