JPH03250729A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH03250729A JPH03250729A JP4854890A JP4854890A JPH03250729A JP H03250729 A JPH03250729 A JP H03250729A JP 4854890 A JP4854890 A JP 4854890A JP 4854890 A JP4854890 A JP 4854890A JP H03250729 A JPH03250729 A JP H03250729A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- temperature
- semiconductor substrate
- impurity
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 45
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 238000011282 treatment Methods 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007373 indentation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000011866 long-term treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、半導体素子の製造方法、特に不純物拡散方
法に特徴を有する半導体素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device characterized by an impurity diffusion method.
（ロ）従来の技術
従来、半導体基板に基板の表裏両面から不純物拡散を行
い、アイソレーション層を得る場合には、不純物マスク
として酸化ｐ（ＳｉＯ□）を使用し、高温拡散を行う。(B) Prior Art Conventionally, when impurities are diffused into a semiconductor substrate from both the front and back surfaces of the substrate to obtain an isolation layer, p(SiO□) oxide is used as an impurity mask and high-temperature diffusion is performed.
その処理過程を第５図（ａｎ〜第５図（ｄ）により説明
すると、先ずシリコン（Ｓｉ）の半導体基板１の両面に
酸化膜２１．３を形成し〔第５図（ａ））、次にフォト
リゾ技術等を用い、拡散すべき領域４の酸化膜２．３を
除去しく第５図Ｑ）） ’ｊ、さらに酸化膜２．３及び
酸化膜除去部４の上面に、ボロン等の不純物５．６を塗
布し〔第５図（Ｃ）〕、Ｉ２７０℃の高温で長時間に亘
り、拡散領域７と下の拡散領域８が連通ずるまで、拡散
処理を行う。The processing process will be explained with reference to FIGS. 5(a) to 5(d). First, an oxide film 21.3 is formed on both sides of a silicon (Si) semiconductor substrate 1 [FIG. 5(a)], and then The oxide film 2.3 in the region 4 to be diffused is removed using photoresolution technology, etc. (Fig. 5Q) 5.6 [FIG. 5(C)], and a diffusion process is performed at a high temperature of I270° C. for a long time until the diffusion region 7 and the lower diffusion region 8 are communicated with each other.
通常酸化膜は５０００〜８０００人程度の厚さであるが
、ここでの高温処理、そして、長時間の処理なので１５
０００人〜２００００人程度に厚くし、拡散終了後に、
表面を全面エツチングして、つまり表面の酸化膜を一部
除去し、ボロンリッチ層を除去している。Normally the oxide film is about 5,000 to 8,000 thick, but since the high temperature treatment and long time treatment here
Increase the number to around 20,000 to 20,000 people, and after the spread is complete,
The entire surface is etched, that is, part of the oxide film on the surface is removed, and the boron-rich layer is removed.
（ハ）発明が解決しようとする課題
上記した従来の高温拡散では、高温で長時間に口る処理
か続＜１コめ 酸化膜か不純ｆｒ）＋ホロン）と反応し
、酸化ｌＩＩ：！乙こピンホールか多く発生しく第４図
参照） ごのピンホールにより酸化膜の絶縁耐圧が悪化
し、ショート等による歩留りを低下させるという問題が
あった。(c) Problems to be Solved by the Invention In the conventional high-temperature diffusion described above, the long-term treatment at high temperatures causes a reaction with the oxide film or impurity fr) + holon), causing oxidation lII:! (See Figure 4 (see Figure 4)) There was a problem in that the dielectric strength of the oxide film deteriorated due to the pinholes, and the yield decreased due to short circuits and the like.
この発明は、上記問題点に着目してなされたものであっ
て、高温拡散における酸化膜と不純物との反応を防止し
、ピンホールの発生を軽減し、歩留りの良い半導体素子
の製造方法を提供することを目的としている。The present invention has been made in view of the above-mentioned problems, and provides a method for manufacturing semiconductor devices that prevents the reaction between an oxide film and impurities during high-temperature diffusion, reduces the occurrence of pinholes, and has a high yield. It is intended to.
（ニ）課題を解決するための手段及び作用この発明の半
導体素子の製造方法は、半導体基板上に酸化膜を形成し
、次に拡散すべき領域の酸化膜を除去し、その後、前記
半導体基板の酸化膜及び酸化膜除去部上面に不純物を塗
布し、１０００“０〜１３００℃の温度で数十分加熱し
て第１の不純物拡散を行い、次に酸化膜上の不純物層の
除去処理を行い、続いて１０００℃〜１３００ ’Ｃの
温度で］、 Ｏ０時間〜２００時間の加熱による第２の
不純物拡散を行い、半導体基板内Ｃコ拡散領域を形成す
るようにしている。(d) Means and Effects for Solving the Problems The method for manufacturing a semiconductor element of the present invention includes forming an oxide film on a semiconductor substrate, removing the oxide film in a region to be diffused, and then removing the oxide film from the semiconductor substrate. An impurity is applied to the top surface of the oxide film and the part from which the oxide film has been removed, and heated at a temperature of 1000°C to 1300°C for several minutes to perform the first impurity diffusion.Then, the impurity layer on the oxide film is removed. Then, a second impurity diffusion is performed by heating at a temperature of 1000° C. to 1300° C. for a period of 0 hours to 200 hours to form a C co-diffused region in the semiconductor substrate.
この半導体素子の製造力弓ハは、処理時間が数十分と比
較的短い第１の不純物拡散の後で、酸化膜上の不純物層
の除去処理を行い、同温長時間の第２の不純物拡散に入
る前に酸化膜上の不純物かすでに除去されているので、
品温長時間の不純物拡散に入っても、酸化膜と不純物の
反応が少なくなり、酸化膜におけるピンホールの発生が
軽減される。The key to the production of semiconductor devices is that after the first impurity diffusion, which takes a relatively short processing time of several tens of minutes, the impurity layer on the oxide film is removed, and the second impurity diffusion process is performed at the same temperature for a long time. Since the impurities on the oxide film have already been removed before entering the diffusion,
Even if the impurity is diffused for a long time at the product temperature, the reaction between the oxide film and the impurity is reduced, and the occurrence of pinholes in the oxide film is reduced.
（ホ）実施例 以下、実施例により、この発明の詳細な説明する。(e) Examples Hereinafter, this invention will be explained in detail with reference to Examples.
第１図（ａ）乃至第１図げ）は、この発明の一実施例を
示し、半導体基板にＳＣＲ用のアイソし・−ジョン層を
形成するための拡散処理過程を示す半導体基板の断面図
である。FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor substrate showing an embodiment of the present invention and showing a diffusion process for forming an isolating layer for SCR on a semiconductor substrate. It is.
シリコン（Ｓ ｉ ）の半導体基板１の両面に酸化膜２
．３を形成すること〔第１図（ａ））、拡散すべき領域
４の酸化膜２．３を除去すること〔第１図（ｂ）Ｌ酸化
膜２．３及び酸化膜除去部４の上面に十〇ノ等の不純物
５．６を塗布することＣ第１図（ｂ））は、第５Ｖ（ａ
ｔ、第一）［ｋ（ｂ）、第、５図（Ｃｊ ４１示した従
来方法と同様である。ここで、ホロンソースとしては、
ＰＢＦ（ポリホロンフィルム）、ＢＮ′、Ｂｒ：ｐ、等
が使用される。An oxide film 2 is formed on both sides of a silicon (S i ) semiconductor substrate 1.
．． 3 [FIG. 1(a)), removing the oxide film 2.3 in the region 4 to be diffused [FIG. 1(b) the upper surface of the L oxide film 2.3 and the oxide film removed portion 4]. Applying impurities 5.6 such as 10 to
t, 1st) [k(b), Fig. 5 (Cj) Same as the conventional method shown in 41.Here, as a holon source,
PBF (polyphoron film), BN', Br:p, etc. are used.
このＴ協働の特徴は、いきなり、高温長時間の拡散処理
Ｑこ移らず、３０〜６０分程度の比較的短時間の不純物
拡散を行い、半導体基板１の酸化膜除去部４より、半導
体基板ウェハｊに拡散領域７．８の成長を開始させる〔
第１図（ｄ）〕。この処理における温度プロセスの一例
を示すと１、第２図（ａ）に示す通りである。半導体基
板ｌを加鯵炉に入れて、温度１２７０℃における加熱３
０〜６０分で半導体基板（ウェハ）１を加熱炉から出し
、次に今度は酸化膜除去部４をマスクして、酸化膜２．
３上をフォトリヅ方式でエツチングし、酸化膜２．３上
のポロンソースを除去する（第１図（ｅ）〕。このフォ
トリヅ・エツチングでは、逆に酸化膜除去部４がマスク
されるので、この部分におけるホロン層は工・ノチング
されず、ホロン層が減らないので、後のホロンの押込み
に有効である。次に、半導体基板１を再度加熱炉に入れ
、第２図の不純物拡散処理を行い、ホロンの押込みを行
う。この処理における温度プロヤスの一例を示すと第２
図（ｂｌに示す辿りであり、＋ ２７０ ’Ｃの高温で
１７０１＋ｒ〜１９０Ｈｒの長時間Ｑこ亘り加熱を行う
。これによりホロンの拡散領域としてｘ ＝ ｌ ００
（ｔ〜１２０μの押入れが可能となり、半導体基板１
の上面よりの拡散領域７と下面よりの拡散領域８か連結
され、アイソレーション層９か形成される。The feature of this T cooperation is that the impurity is diffused for a relatively short time of about 30 to 60 minutes without suddenly going through the high temperature and long time diffusion process Q, and the semiconductor substrate is Initiate growth of diffusion region 7.8 on wafer j [
Figure 1(d)]. An example of the temperature process in this treatment is shown in FIGS. 1 and 2 (a). Semiconductor substrate l is placed in a heating furnace and heated at a temperature of 1270°C 3
After 0 to 60 minutes, the semiconductor substrate (wafer) 1 is taken out of the heating furnace, and then the oxide film removal section 4 is masked and the oxide film 2.
3 is etched using a photolithography method to remove the poron source on the oxide film 2.3 (FIG. 1(e)).In this photolithography, the oxide film removed portion 4 is masked, so this The holon layer in the part is not etched or notched and the holon layer is not reduced, which is effective for later holon indentation.Next, the semiconductor substrate 1 is placed in the heating furnace again and the impurity diffusion treatment shown in FIG. 2 is performed. , indentation of holons is performed.An example of temperature propagation in this process is shown in the second example.
This is the trace shown in Figure (bl), and heating is performed for a long time Q from 1701+r to 190Hr at a high temperature of +270'C.As a result, x = l 00 as the holon diffusion region.
(It becomes possible to press the semiconductor substrate 1 to 120 μm.
The diffusion region 7 from the upper surface and the diffusion region 8 from the lower surface are connected to form an isolation layer 9.
なお、ｈ記実協働において、第１の不純物拡散、第２の
不純物拡散とも、１０００〜１３００’ｃ（７）加熱温
度で実用的である。また、第２の不純物拡散における時
間は、拡散幅により１００〜２００時間の範囲で選択す
ればよい。In addition, in the actual cooperation described in h, both the first impurity diffusion and the second impurity diffusion are practical at a heating temperature of 1000 to 1300'c (7). Further, the time for the second impurity diffusion may be selected in the range of 100 to 200 hours depending on the diffusion width.
以−」二のようにしてアイソレーション層９が形成され
る半導体基板１は、高温長時間の拡散時に酸化ＩＩ！
２．３上の不純物層、つまりボロンソースが除去されて
いるので酸化１１９２．３とホロンとの反応する度合か
少なく、したかって半導体基板１上に生じるピンホール
も少ない。概略的に、この実施例方法により得られた半
導体ウェハ（基板）１のピンホール１０は第３し１（ａ
）に示す状態であり、ホード位置とオリフラ部に若干発
生ずる程度であり、９０〜９５％の歩留りが得られた。The semiconductor substrate 1 on which the isolation layer 9 is formed as described above is oxidized to II! during high-temperature and long-term diffusion.
Since the impurity layer above 2.3, that is, the boron source, has been removed, the degree of reaction between oxidized 1192.3 and holon is reduced, and therefore fewer pinholes are generated on the semiconductor substrate 1. Generally speaking, the pinhole 10 of the semiconductor wafer (substrate) 1 obtained by the method of this embodiment is the third one (a).
), with only slight occurrence at the hoard position and orientation flat portion, and a yield of 90 to 95% was obtained.
従来方法による半導体ウェハ１のピンホールが第３図（
ｂ）に示すようにウェハ全体面にピンホール１０か生じ
、歩留りも４０〜７０％程度であると比較すると格段の
好結果を得ている。The pinholes in the semiconductor wafer 1 made by the conventional method are shown in Figure 3 (
As shown in b), 10 pinholes were formed on the entire surface of the wafer, and the yield was about 40 to 70%, which is a much better result.
また、第４図（ａ）に示すように、本発明をＳＣＲに実
施した場合の高温逆バイアス時のＱＡＴ （信頼性評価
時間）−１゜＊ｌＩ （ピークオフ電圧の漏れ電流）
の特性は、第４図（ｂ）に示す従来例による場合に比べ
、はるかに変動幅が小さい結果を得ている。Furthermore, as shown in FIG. 4(a), when the present invention is applied to an SCR, QAT (reliability evaluation time) -1°*lI (peak-off voltage leakage current) at high temperature reverse bias.
As for the characteristics, the fluctuation range is much smaller than that of the conventional example shown in FIG. 4(b).
また、上記実施例では、酸化膜上の不純物層を除去する
のに、フォトリゾ・エツチング方式を採用しているが、
これに代えてフッ酸ライト・エツチングにより酸化膜上
のボロンリッチ層を除去してもよい。Furthermore, in the above embodiment, a photolitho-etching method is used to remove the impurity layer on the oxide film.
Alternatively, the boron-rich layer on the oxide film may be removed by hydrofluoric acid light etching.
（へ）発明の効果
この発明によγ１．は、＋０００℃−１３００°（：の
温度で数十分加熱して第１の不純物拡散を行い、次に酸
化膜上の不純物層の除去処理を行い、続いて１０００℃
〜１３００℃０′）温度で１００時間〜２００時間の加
熱による第２の不純物拡散を行い、半導体基板内に拡散
領域を形成するようにしているので、長時間に亘る高温
拡散時は、不純物か酸化膜上から除去されており、し、
たかって酸化膜と不純物との反応も少なく、ピンホール
の発生も軽減される。そのため、酸化膜の膜質か向上し
、信頼性試験、バイアス試験等に強くなり、また耐圧不
良による歩留り低下も格段に改善される。(f) Effects of the invention With this invention, γ1. The first impurity diffusion is performed by heating at a temperature of +000°C - 1300° (:), then the impurity layer on the oxide film is removed, and then the impurity layer is heated at 1000°C.
The second impurity diffusion is performed by heating for 100 to 200 hours at a temperature of ~1300°C (0') to form a diffusion region within the semiconductor substrate. The oxide film is removed from above, and
Consequently, there is less reaction between the oxide film and impurities, and the occurrence of pinholes is also reduced. Therefore, the film quality of the oxide film is improved, making it resistant to reliability tests, bias tests, etc., and the reduction in yield due to poor breakdown voltage is also significantly improved.
第１図（ａ）、第１図（１））、第１図（Ｃ）、第１図
（ｄ、）、第１図（ｅ）及び第１図げ）は、この発明の
一実施例を示す拡散処理過程を説明する１こめの半導体
基板の断面図、第２図（ａ）は、同処理過程における第
１の不純物拡散の温度プロセス例を示すし１、第２図（
ｂ）は、同処理過程における第２の不純物拡散の温度プ
ロセス例をボ１図、第３図ｊａ）は、同実梅例により得
られ１こ半導体ウェハのピンホール分布を示す図、第、
３図（１））は、従来方法の実施で得られた半導体つ℃
ハのピンホール分布を示す図、第４図（ａｌは、−上記
実施例により製造したＳＣＲのＱ Ａ Ｔ Ｉ ＤＲ
Ｍ特性を示す図、第４図（ｂ）は、従来例により得られ
たＳＣＲのＱ Ａ Ｔ Ｉ ＤＡＭ特性を示すＭ、第
５図ａ）、第５図（ｂ）、第５１１Ｄ（Ｃ）及び第５図
（ｄ）は、従来の不純物拡散処理過程を説明するための
半導体基板の断面図である。
に半導体基板、 ２・３：酸化膜、４：酸化膜除去
部、 ５・６：ホロン層、７・８：拡散領域。FIG. 1(a), FIG. 1(1)), FIG. 1(C), FIG. 1(d,), FIG. 1(e) and FIG. 1) are examples of the present invention. FIG. 2(a) is a cross-sectional view of a semiconductor substrate for the first time to explain the diffusion treatment process, and FIG.
Figure b) shows an example of the temperature process of the second impurity diffusion in the same process; Figure 3a) shows the pinhole distribution of a semiconductor wafer obtained by the same example;
Figure 3 (1)) shows the semiconductor temperature obtained by implementing the conventional method.
FIG. 4 is a diagram showing the pinhole distribution of -
FIG. 4(b) is a diagram showing the M characteristic, FIG. 5(a), FIG. 5(b), and FIG. and FIG. 5(d) is a cross-sectional view of a semiconductor substrate for explaining a conventional impurity diffusion treatment process. 2 and 3: oxide film, 4: oxide film removed portion, 5 and 6: holon layer, and 7 and 8: diffusion region.
Claims (1)
領域の酸化膜を除去し、その後、前記半導体基板の酸化
膜及び酸化膜除去部上面に不純物を塗布し、１０００℃
〜１３００℃の温度で数十分加熱して第１の不純物拡散
を行い、次に酸化膜上の不純物層の除去処理を行い、続
いて１０００℃〜１３００℃の温度で１００時間〜２０
０時間の加熱による第２の不純物拡散を行い、半導体基
板内に拡散領域を形成するようにした半導体素子の製造
方法。(1) Form an oxide film on a semiconductor substrate, then remove the oxide film in the region to be diffused, then apply an impurity to the oxide film of the semiconductor substrate and the upper surface of the oxide film removed part, and heat at 1000°C.
The first impurity diffusion is performed by heating at a temperature of ~1300°C for several minutes, and then the impurity layer on the oxide film is removed, followed by heating at a temperature of 1000°C ~ 1300°C for 100 hours ~20
A method for manufacturing a semiconductor device, in which a second impurity diffusion is performed by heating for 0 hours to form a diffusion region in a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2048548A JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2048548A JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03250729A true JPH03250729A (en) | 1991-11-08 |
| JPH07101676B2 JPH07101676B2 (en) | 1995-11-01 |
Family
ID=12806429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2048548A Expired - Lifetime JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101676B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016189411A (en) * | 2015-03-30 | 2016-11-04 | 新電元工業株式会社 | Semiconductor device manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55143031A (en) * | 1979-04-25 | 1980-11-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58175845A (en) * | 1982-04-07 | 1983-10-15 | Mitsubishi Electric Corp | Structure of isolation diffusion region in semiconductor device |
| JPS63117419A (en) * | 1986-11-06 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1990
- 1990-02-28 JP JP2048548A patent/JPH07101676B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55143031A (en) * | 1979-04-25 | 1980-11-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58175845A (en) * | 1982-04-07 | 1983-10-15 | Mitsubishi Electric Corp | Structure of isolation diffusion region in semiconductor device |
| JPS63117419A (en) * | 1986-11-06 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016189411A (en) * | 2015-03-30 | 2016-11-04 | 新電元工業株式会社 | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07101676B2 (en) | 1995-11-01 |
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