JPS6093200U - Dynamic memory access circuit - Google Patents
Dynamic memory access circuitInfo
- Publication number
- JPS6093200U JPS6093200U JP18391683U JP18391683U JPS6093200U JP S6093200 U JPS6093200 U JP S6093200U JP 18391683 U JP18391683 U JP 18391683U JP 18391683 U JP18391683 U JP 18391683U JP S6093200 U JPS6093200 U JP S6093200U
- Authority
- JP
- Japan
- Prior art keywords
- dynamic memory
- memory access
- access circuit
- selection signal
- address selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はダイナミックメモリアクセス回路の従来例によ
る回路図、第２図は第１図の回路における信号のタイミ
ングチャート、第３図は本考案によるダイナミックメモ
リアクセス回路の一実施例の回路図、第４図は第３図の
回路における信号のタイミングチャートである。
１・・・・・・ダイナミックメモリ、２・・・・・・ア
ドレス切換回路、６・・・・・・ＣＰＵ、 １７・・・
・・・クロック信号、ＲＡＳ・・・・・・行アドレス選
択信号（又はその端子）、ＣＡＳ・・・・・・列アドレ
ス選択信号（又はその端子）、Ｓ・・・・・・アドレス
選択信号（又はその端子）。1 is a circuit diagram of a conventional example of a dynamic memory access circuit, FIG. 2 is a timing chart of signals in the circuit of FIG. 1, and FIG. 3 is a circuit diagram of an embodiment of a dynamic memory access circuit according to the present invention. FIG. 4 is a timing chart of signals in the circuit of FIG. 1...Dynamic memory, 2...Address switching circuit, 6...CPU, 17...
...Clock signal, RAS...Row address selection signal (or its terminal), CAS...Column address selection signal (or its terminal), S...Address selection signal (or its terminal).
Claims (1)
び列アドレス選択信号ならびにアドレス切替回路に供給
されるアドレス選択信号の各々のレベル転換時期を、Ｃ
ＰＵのクロック信号を用いて制御するように構成したこ
とを特徴とするダイナミックメモリアクセス回路。The level change timing of each of the row address selection signal and column address selection signal supplied to the dynamic memory and the address selection signal supplied to the address switching circuit is determined by C.
A dynamic memory access circuit characterized in that it is configured to be controlled using a clock signal of a PU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18391683U JPS6093200U (en) | 1983-11-28 | 1983-11-28 | Dynamic memory access circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18391683U JPS6093200U (en) | 1983-11-28 | 1983-11-28 | Dynamic memory access circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6093200U true JPS6093200U (en) | 1985-06-25 |
Family
ID=30397922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18391683U Pending JPS6093200U (en) | 1983-11-28 | 1983-11-28 | Dynamic memory access circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6093200U (en) |
-
1983
- 1983-11-28 JP JP18391683U patent/JPS6093200U/en active Pending
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