JPS6092828U - 電子部品の実装構造 - Google Patents

電子部品の実装構造

Info

Publication number
JPS6092828U
JPS6092828U JP18645183U JP18645183U JPS6092828U JP S6092828 U JPS6092828 U JP S6092828U JP 18645183 U JP18645183 U JP 18645183U JP 18645183 U JP18645183 U JP 18645183U JP S6092828 U JPS6092828 U JP S6092828U
Authority
JP
Japan
Prior art keywords
mounting structure
double
glass epoxy
circuit board
clad glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18645183U
Other languages
English (en)
Inventor
達彦 入江
茂成 高見
二郎 橋爪
敏行 山口
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP18645183U priority Critical patent/JPS6092828U/ja
Publication of JPS6092828U publication Critical patent/JPS6092828U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図及び第2図はこの考案の一実施例を示す図で、第
1図は斜視図、第2図は断面図である。

Claims (1)

    【実用新案登録請求の範囲】
  1. パワートランジスタ、集積回路等の、特に大電力用の半
    導体素子を実装する電子部品の実装構造において、両面
    銅張ガラスエポキシ回路基板1の1部に該基板とほぼ等
    厚の金属板3を埋め込み、該金属板3上に半導体素子4
    をグイボンドし、両面銅張ガラスエポキン回路基板1上
    に形成された銅箔からなる回路部5にワイヤボンドをし
    、回路部5と該両面銅張ガラスエポキシ回路基板1の表
    面の電極部8をスルホール9で接続して成る電子部品の
    実装構造。
JP18645183U 1983-11-30 1983-11-30 電子部品の実装構造 Pending JPS6092828U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18645183U JPS6092828U (ja) 1983-11-30 1983-11-30 電子部品の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18645183U JPS6092828U (ja) 1983-11-30 1983-11-30 電子部品の実装構造

Publications (1)

Publication Number Publication Date
JPS6092828U true JPS6092828U (ja) 1985-06-25

Family

ID=30402723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18645183U Pending JPS6092828U (ja) 1983-11-30 1983-11-30 電子部品の実装構造

Country Status (1)

Country Link
JP (1) JPS6092828U (ja)

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