JPH01245549A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01245549A JPH01245549A JP63072777A JP7277788A JPH01245549A JP H01245549 A JPH01245549 A JP H01245549A JP 63072777 A JP63072777 A JP 63072777A JP 7277788 A JP7277788 A JP 7277788A JP H01245549 A JPH01245549 A JP H01245549A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- cooling element
- electronic cooling
- element portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000001816 cooling Methods 0.000 claims abstract description 78
- 230000000694 effects Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000005679 Peltier effect Effects 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000001747 exhibiting effect Effects 0.000 claims 2
- 229920001721 polyimide Polymers 0.000 abstract description 15
- 239000009719 polyimide resin Substances 0.000 abstract description 14
- 238000010292 electrical insulation Methods 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 4
- 230000006698 induction Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置およびその製法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device and a method for manufacturing the same.
半導体装置は駆動に伴う発熱により温度が上昇する。温
度が上昇すると、半導体装置の特性は一般的に低下する
。そのため、強制的に冷却を行い、半導体装置の温度が
あまり上昇しないようにすることが行われている。The temperature of a semiconductor device increases due to heat generated during driving. As the temperature rises, the characteristics of semiconductor devices generally deteriorate. Therefore, forced cooling is performed to prevent the temperature of the semiconductor device from rising too much.
具体的な冷却方法としては、第４図にみるように、アル
ミ等からなる放熱フィン６１を半導体装置Ｔに外付けし
たり、第５図にみるように、小型モータ６２とファン６
３を備えた空冷式冷却器６４を外付けしたり、あるいは
、第６図にみるように、ノズルＮからの冷却水Ｗが半導
体装置Ｔに接触するように流される水冷式冷却器６５を
外付けするという方法がある。さらには、第７図にみる
ように、サーモモジュール６６と別置の電源装置６７、
あるいは、これに加えてフィン６８を組み合わせた電子
冷却装置を外付けするという方法もある。なお、サーモ
モジュール６６は、ペルチエ効果を利用しており、金属
板の間に、半導体片を挟むようにして設け、金属板の間
に電流を流すと、一方の金属板の側で冷却が、他方の金
属板の側で発熱がおこるというユニット体である。As a specific cooling method, as shown in FIG. 4, a heat radiation fin 61 made of aluminum or the like is externally attached to the semiconductor device T, or as shown in FIG. 5, a small motor 62 and a fan 6 are used.
3, or, as shown in FIG. There is a way to attach it. Furthermore, as shown in FIG. 7, a thermo module 66 and a separate power supply device 67,
Alternatively, there is also a method of externally attaching an electronic cooling device combining fins 68 in addition to this. The thermo module 66 utilizes the Peltier effect, and when a semiconductor piece is sandwiched between metal plates and a current is passed between the metal plates, cooling occurs on one side of the metal plate while cooling occurs on the side of the other metal plate. It is a unit body that generates heat.
しかしながら、上記の冷却方法は、冷却装置（冷却器）
がかなり大きく、どうしても、相当な組み付は面積が必
要となるため、半導体装置を高密度に実装することが困
難であったり、半導体装置の小型化が無意味なものとな
ってしまったりして、結局、電子機器の小型を図ること
ができないという問題がある。However, the above cooling method uses a cooling device (cooler)
is quite large, and a considerable amount of space is required for assembly, making it difficult to mount semiconductor devices in high density and making miniaturization of semiconductor devices pointless. However, there is a problem in that it is not possible to downsize the electronic device.
また、冷却装置は、半導体装置を機器に実装する際に個
々に取り付けられていることから、組み付はコストが高
くつくという問題もある。Furthermore, since the cooling devices are individually attached when semiconductor devices are mounted on equipment, there is also the problem that assembly costs are high.
この発明は、上記事情に鑑み、広い取り付は面積を必要
とせず、効果的に冷却され、しかも、組み付はコストも
少なくてすむ半導体装置およびその製法を提供すること
を課題とする。In view of the above circumstances, it is an object of the present invention to provide a semiconductor device that does not require a large installation area, is effectively cooled, and can be assembled at low cost, and a method for manufacturing the same.
前記課題を解決するため、請求頃１の発明は、所要の機
能を有する半導体素子部分を備え、ペルチエ効果による
冷却作用を発揮する電子冷却素子部分が前記半導体素子
部分と一体的に設けられている。In order to solve the above problem, the invention of claim 1 is provided with a semiconductor element portion having a required function, and an electronic cooling element portion that exhibits a cooling effect due to the Peltier effect is provided integrally with the semiconductor element portion. .
請求頃２の発明は、上に加えて、半導体素子と電子冷却
素子が、共通の駆動電源の導入用端子から電源供給を受
けるようになっており、かつ、前記電子冷却素子には電
流制限用のインピーダンス素子を介して電流が流れるよ
うになっている。In addition to the above, the invention of claim 2 is such that the semiconductor element and the electronic cooling element receive power supply from a common driving power supply introduction terminal, and the electronic cooling element has a current limiting function. Current flows through the impedance element.
請求頃３の発明は、前記半導体装置を得るにあたり、別
々に作成された前記半導体素子部分と前記電子冷却素子
部分を用いるとともに、両素子部分の各表面がそれぞれ
予め絶縁材料で平坦化されており、これらの平坦表面が
互いに密着するようにして一体化する。In the invention of claim 3, in obtaining the semiconductor device, the semiconductor element portion and the electronic cooling element portion are separately produced, and each surface of both the element portions is planarized with an insulating material in advance. , these flat surfaces are brought together in close contact with each other.
この発明では、半導体素子と電子冷却素子は一体化され
ていて、冷却が効果的になされるため、電子冷却素子を
ことさら大きなものとしなくてよい。しかも、半導体装
置を製造してから後、機器に実装する際に個々に冷却装
置を組み付けていた従来の場合と違って、装置の製造工
程のうちで電子冷却素子の組み付けがなされるので、組
み付けが効率的に行える。In this invention, since the semiconductor element and the electronic cooling element are integrated and cooling is performed effectively, the electronic cooling element does not need to be particularly large. Moreover, unlike the conventional case where cooling devices were assembled individually after semiconductor devices were manufactured and then mounted on equipment, the electronic cooling elements are assembled during the device manufacturing process. can be done efficiently.
請求頃２の発明では、半導体素子と電子冷却素子の駆動
電源の導入用端子が共用されているので、端子数が少な
くてすむ。電子冷却素子に流れる電流が制限されるため
、素子が過電流により破損することがない。In the invention of claim 2, since the terminal for introducing the drive power source for the semiconductor element and the electronic cooling element is shared, the number of terminals can be reduced. Since the current flowing through the electronic cooling element is limited, the element will not be damaged by overcurrent.
請求頃３の発明では、半導体素子部分と電子冷却素子部
分が別々に形成されているので、製造工程での干渉がな
く、半導体素子と電子冷却素子が正確に所望の機能を果
たせるようにすることができる。しかも、両素子部分は
、平坦表面を介してぴったりと密着していて、半導体素
子部分から電子冷却素子部分への熱伝達効率が良いため
に、半導体素子が十分に冷却される。In the invention of claim 3, since the semiconductor element part and the electronic cooling element part are formed separately, there is no interference in the manufacturing process, and the semiconductor element and the electronic cooling element can accurately perform the desired functions. Can be done. Moreover, since both the element parts are in close contact with each other through the flat surfaces, and the heat transfer efficiency from the semiconductor element part to the electronic cooling element part is good, the semiconductor element is sufficiently cooled.
以下、まず、請求頃１．２の発明にかかる半導体装置を
、その−例をあられす図面を参照しながら詳しく説明す
る。Hereinafter, first, an example of the semiconductor device according to the invention of claim 1.2 will be explained in detail with reference to the accompanying drawings.
第１図は請求頃１．２の発明の一例の半導体装置をあら
れす。半導体装置１は、所要の機能を有する半導体素子
部分２の上にペルチエ効果による冷却作用を発揮する電
子冷却素子部分３が一体的に設けられている。半導体素
子部分２は表面に平坦化用ポリイミド樹脂膜２１を備え
、電子冷却素子部分３は裏面に平坦化用ポリイミド樹脂
膜３１を備えていて、画部分２．３は、両ポリイミド樹
脂膜２１．３１をぴったりと合わせるようにして積ね合
わされて一体化され、電気的絶縁と同時に熱の伝導が良
好になされるようになっている。FIG. 1 shows a semiconductor device according to an example of the invention of claim 1.2. In the semiconductor device 1, an electronic cooling element portion 3 that exhibits a cooling effect due to the Peltier effect is integrally provided on a semiconductor element portion 2 having a required function. The semiconductor element portion 2 has a flattening polyimide resin film 21 on the front surface, the electronic cooling element portion 3 has a flattening polyimide resin film 31 on the back surface, and the image portion 2.3 has both polyimide resin films 21. 31 are laminated and integrated so as to fit closely together, thereby providing good electrical insulation and good heat conduction.
このように、この半導体装置１では、半導体素子部分２
と電子冷却素子部分３が一体的に設けられているため、
前述のごとき、電子冷却素子がことさら大きなものでな
くとも、’Ｊノ果的に冷却され、しかも、電子冷却素子
の組み付けが効率的に行える。In this way, in this semiconductor device 1, the semiconductor element portion 2
Since the and electronic cooling element portion 3 are integrally provided,
As mentioned above, even if the electronic cooling element is not particularly large, it can be effectively cooled and the electronic cooling element can be assembled efficiently.
半導体素子部分２は、静電誘導サイリスクが形成されて
おり、スイッチング機能を有している。The semiconductor element portion 2 has an electrostatic induction silicone formed thereon and has a switching function.
静電誘導サイリスクは、半導体基板２２の表側にカソー
ド領域（Ｎ”領域）２３およびゲート領域（Ｐ”領域）
２４を備え、かつ、裏側にアノード領域（Ｐ”領域）２
５を備えていて、カソード・アノードの間にＮ−高比抵
抗領域（不純物低濃度領域ないし真性半導体領域）２６
を備えている。The electrostatic induction silicon risk includes a cathode region (N" region) 23 and a gate region (P" region) on the front side of the semiconductor substrate 22.
24, and an anode region (P” region) 2 on the back side.
5, and an N- high resistivity region (low impurity concentration region or intrinsic semiconductor region) 26 between the cathode and anode.
It is equipped with
このサイリスクは、ゲート領域２４の電圧を制御するこ
とにより、カソード・アノード間電流をオン・オフする
。２３′はカソード電極、２４′はゲート電極、２５′
はアノード電極である。なお、２７は絶縁層である。This thyrisk turns on and off the cathode-anode current by controlling the voltage in the gate region 24. 23' is a cathode electrode, 24' is a gate electrode, 25'
is the anode electrode. Note that 27 is an insulating layer.
一方、電子冷却素子部分３に形成されている冷却素子は
、誘電体３２によって別々に絶縁分離された複−数のＮ
型半導体領域３３とＰ型半導体領域３４がオーミック接
触する金属領域３５を介して直列接続された構成となっ
ている。この電子冷却素子はペルチェ効果による冷却作
用を発揮する。On the other hand, the cooling element formed in the electronic cooling element portion 3 consists of a plurality of N
A type semiconductor region 33 and a P-type semiconductor region 34 are connected in series through a metal region 35 in ohmic contact. This electronic cooling element exhibits a cooling effect based on the Peltier effect.
すなわち、第１図の実線Ｉの向きに電流を流すと、各半
導体領域３３．３４と下側の金属領域（アルミニウムか
らなる領域）３５の接合個所では吸熱が起こり、各半導
体領域３３．３４と上側の金属領域３５の接合個所では
放熱が起こって、そのため、半導体素子部分２が冷却さ
れる。なお、３６は絶縁層（ＳｉＯ□膜）である。That is, when a current is passed in the direction of the solid line I in FIG. Heat dissipation occurs at the junction of the upper metal region 35, so that the semiconductor component part 2 is cooled. Note that 36 is an insulating layer (SiO□ film).
この半導体装置１では、駆動電源の導入用端子Ｖが設け
られており、半導体素子と電子冷却素子が、このひとつ
の導入用端子■から電源供給を受けるようになっている
。そのため、駆動電源の導入端子がひとつで済む。駆動
電源は直流であっても交流であってもよい。This semiconductor device 1 is provided with a driving power supply introduction terminal V, and the semiconductor element and the electronic cooling element receive power supply from this single introduction terminal V. Therefore, only one lead-in terminal for the drive power source is required. The driving power source may be direct current or alternating current.
直流の場合は、端子Ｖ側が共通（アース）端子Ｅ側に対
し十となるように電圧が印加される。そうすると、抵抗
Ｒ１ショットキーダイオードＤおよび、電子冷却素子の
直列回路に電流が流れ、冷却作用が発揮される。In the case of direct current, a voltage is applied such that the voltage on the terminal V side is ten times that of the common (earth) terminal E side. Then, a current flows through the series circuit of the resistor R1, the Schottky diode D, and the electronic cooling element, and a cooling effect is exerted.
交流の場合は、ダイオードＤがあるため、プラス側の半
波のみ、抵抗Ｒ、ショットキーダイオードＤおよび、電
子冷却素子の直列回路に電流が流れる。抵抗Ｒとダイオ
ードＤ（インピーダンス素子）は、電子冷却素子に流れ
る電流を制限し、電子冷却素子が過電流で破壊されるの
を阻止する。In the case of alternating current, since the diode D is present, current flows through the series circuit of the resistor R, the Schottky diode D, and the electronic cooling element only during the positive half wave. The resistor R and the diode D (impedance element) limit the current flowing to the electronic cooling element and prevent the electronic cooling element from being destroyed by overcurrent.
ショットキーダイオードＤは、電子冷却素子に逆向きの
電流が流れるのを阻止する。なお、コンデンサＣは、電
源ラインに重畳する雑音除去等の（つＪきをする。Schottky diode D prevents reverse current from flowing through the electronic cooling element. Note that the capacitor C serves to remove noise superimposed on the power supply line.
続いて、半導体装置の他の実施例を説明する。Next, other embodiments of the semiconductor device will be described.
第２図は、請求頃１．２の発明にかかる半導体装置の他
の実施例をあられす。FIG. 2 shows another embodiment of the semiconductor device according to the invention of claim 1.2.
第１図の半導体装置１は、電子冷却素子部分３が一層構
成であったが、第２図の半導体装置１′は、ふたつの電
子冷却素子部分３．３′が積まれており、それ以外の点
は、先の実施例と基本的には同じ構成である。ただ、電
子冷却素子部分３′は、その表側にも平坦化用のポリイ
ミド樹脂膜３１′が設けられている。電子冷却素子が積
層されているため、下の半導体素子の熱はより離れたと
ころに素早く移され、より効果的に冷却される。The semiconductor device 1 shown in FIG. 1 has a single-layered thermoelectric cooling element portion 3, whereas the semiconductor device 1' shown in FIG. This point is basically the same configuration as the previous embodiment. However, a polyimide resin film 31' for flattening is provided also on the front side of the electronic cooling element portion 3'. Because the electronic cooling elements are stacked, heat from the underlying semiconductor elements is quickly transferred to a further distance, resulting in more effective cooling.
つぎに、請求頃３の発明である半導体装置の製法を、そ
の−例の要部を説明する図面を参照しながら詳しく説明
する。Next, a method for manufacturing a semiconductor device according to the invention of claim 3 will be explained in detail with reference to drawings illustrating main parts of an example thereof.
電子冷却素子部分と半導体素子部分は、それぞれ別々に
作成される。The electronic cooling element portion and the semiconductor element portion are each manufactured separately.
電子冷却素子部分は、以下のようにして作られる。The electronic cooling element part is made as follows.
第３図（ａｌにみるように１．サファイア基板４１の上
にポリシリコンＮ４２積層し、さらに、その上にＳｉＯ
□膜４３全４３した構成のウェハ４０を作る。５ｉ（ｈ
膜４３に窓を明け、アルカリによる異方性エツチングを
施し、第３図（ｂｌにみるように、ポリシリコン層４２
を複数の分離島領域４２′・・・に分断する。表面に残
された５ｉｏ２１１９４３をエッヂング除去し、第３図
（Ｃ１にみるように、分離島領域４２′・・・を、ひと
つおきにＳｉＯ□膜４４で覆っておいて、５ｉｏｆｆｉ
ｌｌ臭４４で覆われていない分離島領域４２′・・・に
Ｐ型用不純物を拡散し、Ｐ型半導体領域３４を形成する
。続いて、第３図（ｄｌにみるように、ＳｉＯ２膜４４
全４４するとともにＰ型半導体領域３４の表面を５ｉ０
２膜４５で覆っておいて、５ｉＯｚ映４５で覆われてい
ない方の分離島領域４２′・・・にＮ型用不純物を拡散
し、Ｎ型半導体領域３３を形成する。As seen in Figure 3 (al) 1. Polysilicon N42 is laminated on the sapphire substrate 41, and SiO
□ A wafer 40 having a structure including all 43 films 43 is made. 5i(h
A window is opened in the film 43, anisotropic etching is performed using alkali, and the polysilicon layer 42 is etched as shown in FIG.
is divided into a plurality of isolated island regions 42'... The 5io211943 remaining on the surface is removed by etching, and as shown in FIG. 3 (C1), every other isolation island region 42'... is covered with a SiO
A P-type impurity is diffused into the isolation island regions 42' not covered with the ll odor 44 to form a P-type semiconductor region 34. Next, as shown in FIG. 3 (dl), the SiO2 film 44 is
44, and the surface of the P-type semiconductor region 34 is 5i0.
The N-type impurity is diffused into the isolation island region 42' which is not covered with the 5iOz film 45 to form the N-type semiconductor region 33.
Ｎ型、Ｐ型半導体領域３３．３４形成後、第３図＋ｅ＞
にみるように、ＳｉｎｇをＣＶＤ法等により蒸着して、
各半導体領域３３．３４の間を埋めるようにして５ｉＯ
ｚｌｌ臭４７を形成するとともに、間膜４７には、金属
領域とのコンタクトをとる所に窓４６を開ける。この窓
４６を利用して、第３図ｆｆｌにみるように、アルミニ
ウムを蒸着して、金属領域３５を半分形成し、その後、
その上から、第３図ｆｇ）にみるように、ＣＶＤ法等に
より５ｉｎｓ膜４８を積層形成する。After forming N-type and P-type semiconductor regions 33 and 34, Fig. 3+e>
As shown in , Sing is deposited by CVD method etc.
5iO so as to fill the space between each semiconductor region 33 and 34.
A window 46 is formed in the interlayer 47 at a location where contact is made with the metal region. Utilizing this window 46, as shown in FIG. 3 ffl, aluminum is deposited to form half of the metal region 35, and then
From above, as shown in FIG. 3fg), a 5-ins film 48 is laminated by CVD or the like.
この５ｉＯｚ膜４８の上に、第３図０））にみるように
、ポリイミド樹脂膜３１を積層形成して、５ｉＯｚ映４
８表面を平坦化する。その後、第３図（ｉｌにみるよう
に、サファイア基板４１を研暦除去し、その跡へＳｉＯ
□膜４９膜形９するとともに、第３図（Ｊｌにみるよう
に、間膜４９に、金属領域とのコンタクトをとる所に窓
５０を開ける。この窓５０を利用して、第３図（ｋ＋に
みるように、アルミニウムを蒸着して、金属領域３５の
残り半分を形成し、その上へ、第３図（１１にみるよう
に、ＣＶＤ法により、ＳｉＯ□膜３６を積層形成する。On this 5iOz film 48, a polyimide resin film 31 is laminated as shown in FIG.
8. Flatten the surface. After that, as shown in Figure 3 (il), the sapphire substrate 41 was removed and SiO
□ At the same time as the membrane 49 is shaped 9, a window 50 is opened in the interlayer 49 at a place where contact is made with the metal region, as shown in FIG. As shown in k+, aluminum is deposited to form the remaining half of the metal region 35, and a SiO□ film 36 is laminated thereon by the CVD method as shown in FIG. 3 (see 11).
もちろん、端にくる半導体領域３３．３４には、第３図
＋ｍｌにみるように、接続用の金属領域３５′をＳｉＯ
□膜（絶縁膜）３６から露出させる。なお、ＳｉＯ□膜
４７．４８．４９は、Ｐ型半導体領域とＮ型半導体領域
を絶縁分離する誘電体３２に相当する。Of course, in the semiconductor regions 33 and 34 at the ends, as shown in FIG.
□Exposed from the film (insulating film) 36. Note that the SiO□ films 47, 48, and 49 correspond to the dielectric 32 that insulates and isolates the P-type semiconductor region and the N-type semiconductor region.
上記の方法は、通常の半導体製造のマイクロ加工技術を
利用しており、ひとつのウェハに多数の電子冷却素子を
形成するという大量生産方式を採用することができるた
め、電子冷却素子部分の製造コストが低くなる。The above method uses micro-processing technology used in normal semiconductor manufacturing, and can be mass-produced by forming a large number of electronic cooling elements on one wafer, which reduces the manufacturing cost of the electronic cooling element part. becomes lower.
一方、半導体素子部分の方は、半導体基板を用いて通常
の半導体素子の作り方によって、例えば、第１図にみる
ような静電誘導サイリスタを作り、その表面をポリイミ
ド樹脂で平坦化するようにして作成する。On the other hand, for the semiconductor element part, for example, an electrostatic induction thyristor as shown in Figure 1 is made using a semiconductor substrate using the normal method of making semiconductor elements, and its surface is flattened with polyimide resin. create.
製造された電子冷却素子部分と半導体素子部分は、ポリ
イミド樹脂で平坦化された面が互いに密着するようにし
て一体化する。その際、両ポリイミド膜は、例えば、エ
ポキシ樹脂系等の接着剤を用いて接合したり、少なくと
も一方のポリイミド樹脂膜自体に接着性をもたせておい
て、重ね合わされた際に接着させるようにしてもよい。The manufactured electronic cooling element portion and semiconductor element portion are integrated so that their flattened surfaces made of polyimide resin are brought into close contact with each other. At that time, both polyimide films may be bonded together using an adhesive such as an epoxy resin, or at least one of the polyimide resin films itself may be made to have adhesive properties so that they will be bonded together when they are overlapped. Good too.
そして、電気配線を済ませてから、全体をエポキシ樹脂
等の熱硬化性樹脂でモールドすると、半導体装置が完成
する。Then, after completing the electrical wiring, the whole is molded with a thermosetting resin such as epoxy resin to complete the semiconductor device.
電子冷却素子部分と半導体素子部分は、別々に作られて
おり、その製造過程での干渉がない。例えば、半導体素
子部分を作ってから、その上に電子冷却素子部分を順次
積み重ねながら製造する場合には、後の冷却素子部分の
製造工程で、先に製造されている半導体素子の不純物の
拡散状態が乱されたりする等の干渉が起こり、好ましく
ないのである。The electronic cooling element part and the semiconductor element part are made separately, so there is no interference during the manufacturing process. For example, when manufacturing a semiconductor element part and then stacking an electronic cooling element part on top of it, in the later manufacturing process of the cooling element part, the impurity diffusion state of the previously manufactured semiconductor element is This is undesirable as it causes interference such as disturbance of the image.
この発明は上記実施例に限らない。例えば、両素子部分
には、ポリイミド樹脂膜を設けないようにしておいて、
両素子部分を所定の距離隔てた状態に保持しておいて、
その隙間に、例えば、ポリイミド樹脂を注入するように
して、画部分を接着一体化するようにしてもよい。This invention is not limited to the above embodiments. For example, by not providing a polyimide resin film on both element parts,
Keep both element parts separated by a predetermined distance,
For example, polyimide resin may be injected into the gap to bond and integrate the image portions.
ポリイミド樹脂の代わりに他の種類の樹脂を用いて平坦
化するようにしてもよい。半導体素子部分に形成される
素子も、静電誘導サイリスク以外に、例えば、ＭＯ５型
半導体素子、バイポーラトランジスタ等でもよい。誘電
体の材料や金属領域の材料が上記例示以外の材料であっ
てもよい。Other types of resin may be used instead of polyimide resin for flattening. Elements formed in the semiconductor element portion may also be, for example, MO5 type semiconductor elements, bipolar transistors, etc., in addition to electrostatic induction silices. The material of the dielectric and the material of the metal region may be other than those exemplified above.
請求頃１の発明は、半導体素子と電子冷却素子が一体化
されていて、電子冷却素子がことさら人きくなくとも、
冷却が効果的になされるので、冷却素子があっても広い
面積は必要ない。そのため、半導体装置の実装密度をあ
げることができる。The invention of claim 1 is such that the semiconductor element and the electronic cooling element are integrated, and even if the electronic cooling element is not particularly sensitive,
Since cooling is done effectively, even if a cooling element is provided, a large area is not required. Therefore, the packaging density of semiconductor devices can be increased.
しかも、装置の製造工程のうちで電子冷却素子の組み付
けがなされるので、組み付けが効率的に行え、コストが
安い。Moreover, since the electronic cooling element is assembled during the manufacturing process of the device, the assembly can be performed efficiently and the cost is low.
請求頃２の発明では、上に加えて、半導体素子と電子冷
却素子の駆動電源の導入用端子が共用されているので、
端子数が少なくてすみ、高密度化や、これを取りつける
側の基板の配線を簡略化できる。しかも、電子冷却素子
に過電流が流れるのが防止されており、故障せず信頼性
が高い。In the invention of claim 2, in addition to the above, since the introduction terminal for the driving power source of the semiconductor element and the electronic cooling element is shared,
The number of terminals required is small, allowing for higher density and simpler wiring on the board to which it is attached. Moreover, overcurrent is prevented from flowing into the electronic cooling element, so it is highly reliable without failure.
請求頃３の発明で得られた半導体装置は、請求頃１の発
明が有する効果に加えて、つぎのような効果を奏する。The semiconductor device obtained by the invention of claim 3 has the following effects in addition to the effects of the invention of claim 1.
すなわち、半導体素子部分と電子冷却素子部分が別々に
形成されているので、製造工程での干渉がなく、半導体
素子と電子冷却素子が正確に所望の機能が果たせるよう
になっており、しかも、両素子部分は、平坦表面を介し
てぴったりと密着していて、半導体素子部分から電子冷
却素子部分への熱伝達効率が良いために、半導体素子が
十分に冷却されるのである。In other words, since the semiconductor element part and the electronic cooling element part are formed separately, there is no interference in the manufacturing process, and the semiconductor element and the electronic cooling element can accurately perform the desired functions. The element portions are in close contact with each other through the flat surfaces, and the heat transfer efficiency from the semiconductor element portion to the thermoelectric cooling element portion is high, so that the semiconductor element is sufficiently cooled.
第１図は、この発明にかかる半導体装置の一実施例をあ
られす断面図、第２図は、この発明にかかる半導体装置
の他の実施例をあられす断面図、第３図（ａ）〜（ｍ）
は、この半導体装置の製法の一例における電子冷却素子
部分の作成の様子を順を追ってあられす説明図、第４〜
７図は、それぞれ、半導体装置に使われる従来の冷却装
置をあられず説明図である。
１１’・・・半導体装置 ２・・・半導体素子部分３
．３′・・・電子冷却素子部分 ２１．３１・・・ポリ
イミド樹脂膜（絶縁材料）
代理人 弁理士 松 本 武 彦
＄３図
１３図
第４図 第５図
第６図
■
第７図FIG. 1 is a cross-sectional view of one embodiment of the semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of another embodiment of the semiconductor device according to the present invention, and FIGS. (m)
Figures 4 to 4 are explanatory diagrams showing step-by-step the creation of the electronic cooling element part in an example of the manufacturing method of this semiconductor device.
FIG. 7 is an explanatory diagram of a conventional cooling device used for semiconductor devices. 11'...Semiconductor device 2...Semiconductor element portion 3
．． 3'...Electronic cooling element part 21.31...Polyimide resin film (insulating material) Agent Patent attorney Takehiko Matsumoto$3Figure 13Figure 4Figure 5Figure 6■ Figure 7
Claims (1)
エ効果による冷却作用を発揮する電子冷却素子部分が前
記半導体素子部分と一体的に設けられている半導体装置
。 ２ 半導体素子と電子冷却素子が、半導体装置に設けら
れた共通の駆動電源の導入用端子から電源供給を受ける
ようになっているとともに、前記電子冷却素子には電流
制限用のインピーダンス素子を介して電流が流れるよう
になっている請求頃１記載の半導体装置。 ３ 所要の機能を有する半導体素子部分を備え、ペルチ
エ効果による冷却作用を発揮する電子冷却素子部分が前
記半導体素子部分と一体的に設けられている半導体装置
を得るにあたり、前記半導体素子部分と前記電子冷却素
子部分とは別々に作成されていて、両素子部分の各表面
がそれぞれ予め絶縁材料で平坦化されており、これらの
平坦表面が互いに密着するようにして一体化することに
より前記半導体装置を得るようにすることを特徴とする
半導体装置の製法。[Scope of Claims] 1. A semiconductor device comprising a semiconductor element portion having a required function, and in which an electronic cooling element portion exhibiting a cooling effect due to the Peltier effect is provided integrally with the semiconductor element portion. 2. The semiconductor element and the electronic cooling element are configured to receive power supply from a common drive power introduction terminal provided on the semiconductor device, and the electronic cooling element is supplied with power through an impedance element for current limiting. The semiconductor device according to claim 1, wherein a current flows through the semiconductor device. 3. In obtaining a semiconductor device including a semiconductor element portion having a required function and in which an electronic cooling element portion exhibiting a cooling effect due to the Peltier effect is provided integrally with the semiconductor element portion, the semiconductor element portion and the electron The semiconductor device is manufactured separately from the cooling element portion, and each surface of both element portions is flattened in advance with an insulating material, and these flat surfaces are brought into close contact with each other and integrated. A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63072777A JPH01245549A (en) | 1988-03-26 | 1988-03-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63072777A JPH01245549A (en) | 1988-03-26 | 1988-03-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01245549A true JPH01245549A (en) | 1989-09-29 |
Family
ID=13499155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63072777A Pending JPH01245549A (en) | 1988-03-26 | 1988-03-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01245549A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895964A (en) * | 1993-06-30 | 1999-04-20 | Pioneer Electronic Corporation | Thermoelectric cooling system |
| DE10126565A1 (en) * | 2001-05-31 | 2002-12-19 | Infineon Technologies Ag | Device for heat dissipation in an integrated circuit having many levels is arranged in at least one of these levels |
| DE10132763A1 (en) * | 2001-07-10 | 2003-01-30 | Bosch Gmbh Robert | Integrated semiconductor circuit with substrate carrying microwave circuit region(s) |
| DE10238843A1 (en) * | 2002-08-20 | 2004-03-11 | Infineon Technologies Ag | Semiconductor component used in opto-electronic communications comprises a Peltier element for cooling a micro-structure and a thermal generator coupled together via a coupling unit |
| JP2006032453A (en) * | 2004-07-13 | 2006-02-02 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| DE102007051312B4 (en) * | 2006-12-29 | 2009-09-10 | Dongbu Hitek Co., Ltd. | Method of manufacturing a CMOS device with Peltier element and photodiode |
| DE102008049726A1 (en) * | 2008-09-30 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device having an on-chip active heat transfer system |
| FR2977984A1 (en) * | 2011-07-13 | 2013-01-18 | St Microelectronics Rousset | INTEGRATED THERMOELECTRIC GENERATOR, AND INTEGRATED CIRCUIT COMPRISING SUCH A GENERATOR |
| JP2013140992A (en) * | 2008-06-27 | 2013-07-18 | Qualcomm Inc | Active thermal control for stacked ic devices |
| US8995134B2 (en) | 2011-05-27 | 2015-03-31 | Lear Corporation | Electrically-cooled power module |
| JP2017525135A (en) * | 2014-06-02 | 2017-08-31 | ハット テクノロジ アノニム シルケット | Integrated circuit having a cooling array |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558022A (en) * | 1978-07-03 | 1980-01-21 | Oki Electric Ind Co Ltd | Integration circuit |
| JPS58137240A (en) * | 1982-02-10 | 1983-08-15 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS6084849A (en) * | 1983-10-15 | 1985-05-14 | Mitsubishi Electric Corp | Semiconductor device |
-
1988
- 1988-03-26 JP JP63072777A patent/JPH01245549A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558022A (en) * | 1978-07-03 | 1980-01-21 | Oki Electric Ind Co Ltd | Integration circuit |
| JPS58137240A (en) * | 1982-02-10 | 1983-08-15 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS6084849A (en) * | 1983-10-15 | 1985-05-14 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895964A (en) * | 1993-06-30 | 1999-04-20 | Pioneer Electronic Corporation | Thermoelectric cooling system |
| DE10126565A1 (en) * | 2001-05-31 | 2002-12-19 | Infineon Technologies Ag | Device for heat dissipation in an integrated circuit having many levels is arranged in at least one of these levels |
| DE10126565B4 (en) * | 2001-05-31 | 2006-12-21 | Infineon Technologies Ag | Device for dissipating heat from an integrated circuit |
| DE10132763A1 (en) * | 2001-07-10 | 2003-01-30 | Bosch Gmbh Robert | Integrated semiconductor circuit with substrate carrying microwave circuit region(s) |
| DE10132763B4 (en) * | 2001-07-10 | 2007-10-11 | Robert Bosch Gmbh | A semiconductor integrated circuit, a method of cooling a microwave circuit region, and a method of manufacturing a semiconductor integrated circuit |
| DE10238843A1 (en) * | 2002-08-20 | 2004-03-11 | Infineon Technologies Ag | Semiconductor component used in opto-electronic communications comprises a Peltier element for cooling a micro-structure and a thermal generator coupled together via a coupling unit |
| US6891278B2 (en) | 2002-08-20 | 2005-05-10 | Infineon Technologies Ag | Semiconductor component |
| DE10238843B4 (en) * | 2002-08-20 | 2007-08-02 | Infineon Technologies Ag | Semiconductor device |
| DE10238843B8 (en) * | 2002-08-20 | 2008-01-03 | Infineon Technologies Ag | Semiconductor component |
| JP4485865B2 (en) * | 2004-07-13 | 2010-06-23 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006032453A (en) * | 2004-07-13 | 2006-02-02 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| DE102007051312B4 (en) * | 2006-12-29 | 2009-09-10 | Dongbu Hitek Co., Ltd. | Method of manufacturing a CMOS device with Peltier element and photodiode |
| JP2013140992A (en) * | 2008-06-27 | 2013-07-18 | Qualcomm Inc | Active thermal control for stacked ic devices |
| US8987062B2 (en) | 2008-06-27 | 2015-03-24 | Qualcomm Incorporated | Active thermal control for stacked IC devices |
| DE102008049726A1 (en) * | 2008-09-30 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device having an on-chip active heat transfer system |
| US7924569B2 (en) | 2008-09-30 | 2011-04-12 | Advanced Micro Devices, Inc. | Semiconductor device comprising an in-chip active heat transfer system |
| DE102008049726B4 (en) * | 2008-09-30 | 2012-02-09 | Advanced Micro Devices, Inc. | Stacked chip configuration with current-fed heat transfer system and method for controlling the temperature in a semiconductor device |
| US8995134B2 (en) | 2011-05-27 | 2015-03-31 | Lear Corporation | Electrically-cooled power module |
| FR2977984A1 (en) * | 2011-07-13 | 2013-01-18 | St Microelectronics Rousset | INTEGRATED THERMOELECTRIC GENERATOR, AND INTEGRATED CIRCUIT COMPRISING SUCH A GENERATOR |
| US9177994B2 (en) | 2011-07-13 | 2015-11-03 | Stmicroelectronics (Rousset) Sas | Integrated thermoelectric generator |
| JP2017525135A (en) * | 2014-06-02 | 2017-08-31 | ハット テクノロジ アノニム シルケット | Integrated circuit having a cooling array |
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