JPS6068661U - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6068661U
JPS6068661U JP1983160736U JP16073683U JPS6068661U JP S6068661 U JPS6068661 U JP S6068661U JP 1983160736 U JP1983160736 U JP 1983160736U JP 16073683 U JP16073683 U JP 16073683U JP S6068661 U JPS6068661 U JP S6068661U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
substrates
container
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983160736U
Other languages
English (en)
Inventor
賢太郎 石田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1983160736U priority Critical patent/JPS6068661U/ja
Publication of JPS6068661U publication Critical patent/JPS6068661U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
１゛　　第１図は本考案による混成集積回路装置の断面
図である。 １・・・・・・混成集積回路の放熱板、２・・・・・・
容器の外部引出しリード、３は容器の側壁を構成するセ
ラミック、４・・・・・・容器の側壁の金属配線、５・
・・・・・第一のセラミック基板で主要な発熱素子が搭
載されている。６・・・・・・第二のセラミック基板、
７・・・・・・第一のセラミック基板５に搭載された半
導体ペレットの一部を示す。８・・間第−のセラミック
基板上の金属配線の一部を示す。９・・・・・・第二の
セラミック基板６に搭載された半導体ペレットの一部を
示す。１０・・・・・・第二のセラミック基板上の金属
配線の一部を示す。１１・・・・・・セラミック基板内
及びセラミック基板と容器を接続するボンディングワイ
ヤ゛−１１２・・・・・・容器を封止するフタ。

Claims (1)

  1. 【実用新案登録請求の範囲】 １　少なくとも２枚のセラミック基板の各々に一つ以上
    の半導体ペレットが搭載され、これらの基板は互いに各
    々のペレット搭載面に対してほぼ垂直方向に配置され、
    かつ容器の側壁面になされた配線により基板間の電気的
    接続がなされている事を特徴とする混成集積回路装置。 ２　前記第１項記載の混成集積回路装置において、容器
    とりつけ面に近い方の基板には動作時に発生する熱量が
    多い半導体ペレットが搭載されている事を特徴とする混
    成集積回路装置。
JP1983160736U 1983-10-18 1983-10-18 混成集積回路装置 Pending JPS6068661U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983160736U JPS6068661U (ja) 1983-10-18 1983-10-18 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983160736U JPS6068661U (ja) 1983-10-18 1983-10-18 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS6068661U true JPS6068661U (ja) 1985-05-15

Family

ID=30353452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983160736U Pending JPS6068661U (ja) 1983-10-18 1983-10-18 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6068661U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278401A (ja) * 2005-03-28 2006-10-12 Denso Corp 半導体装置
JP2014183126A (ja) * 2013-03-18 2014-09-29 Fujitsu Ltd 高周波モジュール
JP2018512724A (ja) * 2015-02-10 2018-05-17 コンティ テミック マイクロエレクトロニック ゲゼルシャフト ミット ベシュレンクテル ハフツングＣｏｎｔｉ Ｔｅｍｉｃ ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ＧｍｂＨ 電子コンポーネントおよびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278401A (ja) * 2005-03-28 2006-10-12 Denso Corp 半導体装置
JP4556732B2 (ja) * 2005-03-28 2010-10-06 株式会社デンソー 半導体装置及びその製造方法
JP2014183126A (ja) * 2013-03-18 2014-09-29 Fujitsu Ltd 高周波モジュール
JP2018512724A (ja) * 2015-02-10 2018-05-17 コンティ テミック マイクロエレクトロニック ゲゼルシャフト ミット ベシュレンクテル ハフツングＣｏｎｔｉ Ｔｅｍｉｃ ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ＧｍｂＨ 電子コンポーネントおよびその製造方法

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