JPS6065533A - Dry etching method - Google Patents
Dry etching methodInfo
- Publication number
- JPS6065533A JPS6065533A JP17298483A JP17298483A JPS6065533A JP S6065533 A JPS6065533 A JP S6065533A JP 17298483 A JP17298483 A JP 17298483A JP 17298483 A JP17298483 A JP 17298483A JP S6065533 A JPS6065533 A JP S6065533A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- gas
- dry etching
- residue
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はモリブデン、タングステンその他の遷移金属お
よびそれらの硅素化合物のドライエツチング方法に係り
、特にエツチング残渣の少ない、良好な高精度パターン
をエツチング形成するのに好適なエツチング方法に関す
る。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for dry etching molybdenum, tungsten and other transition metals, and their silicon compounds, and in particular to etching and forming a good, high-precision pattern with little etching residue. This invention relates to an etching method suitable for.
グロー放電プラズマを用いるドライエツチング方法は、
微細なパターンを高精度に加工できる方法としてよく知
られており、近年、半導体集積回路の製造方法として採
用されつつある。この方法は、１〜１００ Ｐａ程度の
低圧の反応性ガスを真空室に導入し、高周波電界を印加
してプラズマ化させ、ガス分子から解離生成する反応性
のイオンやラジカノ【べこよって試料をエツチングする
方法である。反応性ガスとしては、通常、Ｆ、Ｃｔなど
ハロゲンを含む化合物ガス、例えばＣＦ４、ＳＦ６、Ｃ
Ｃ１！２Ｆ２等が単独あるいは混合して用いられる。The dry etching method using glow discharge plasma is
It is well known as a method that can process fine patterns with high precision, and has recently been adopted as a method for manufacturing semiconductor integrated circuits. In this method, a low-pressure reactive gas of about 1 to 100 Pa is introduced into a vacuum chamber, and a high-frequency electric field is applied to turn it into plasma. This is an etching method. Reactive gases are usually compound gases containing halogens such as F and Ct, such as CF4, SF6, and Ct.
C1!2F2 and the like can be used alone or in combination.
モリフ゛デン（八１ｏ ）のエツチングを例にとると、
ＣＦ４あるいはＳＦ、から解離したＦラジカルがＭＯ表
面で次の反応を行い
ＭＯ＋６Ｆ −−→ＭｏＦ６
反応生成物ＭＯＦ６は蒸気圧が高く気化してＭｏ表面か
ら離脱し、エツチング反応が進行する。Taking etching of molyphdenum (81o) as an example,
The F radicals dissociated from CF4 or SF undergo the following reaction on the MO surface: MO+6F --→MoF6 The reaction product MOF6 has a high vapor pressure and is vaporized and detached from the Mo surface, and the etching reaction progresses.
モリブデン（Ｍｏ）、タングステン（Ｗ）、チタン（Ｔ
ｉ）、タンタル（Ｔａ ）およびこれらの硅素（Ｓｉ）
化合物は、ＭＯ８型トランジスタのゲート電極材料等と
して半導体集積回路を構成する材料であるが、これらは
いずれもＦを含むプラズマ中で上記の反応式と同様の反
応により容易にエツチングすることができる。通常、Ｍ
Ｏ８型トランジスタのゲート電極の下地には厚さ数十ｎ
ｍの薄い二酸化硅素（Ｓｉｎ２）のゲート酸化膜があり
、ゲート電極のエツチング加工中に、このゲート酸化膜
のエツチングを最小限に抑制するため、使用するガスプ
ラズマ中でのゲート電極材料のエツチング速度とＳｉｏ
２のエツチング速度の比（いわゆるエツチング選択比）
は十分大きな値でなければならない。一般にＣＦ４等炭
素を含むフッ素化合物のプラズマでは５ｉ０２のエツチ
ング速度が相当大きな値古なって、十分なエツチング選
択比が得られず、ゲート電極のエツチングにはＳＦ６、
ＮＦ３−ガスプラズマが用いられる。本発明者らが、反
応性スパッタエツチングあるいは反応性イオンエツチン
グと呼ばれる方式でＳＦ６ガスを用いてＭｏおよびＷを
エツチングした実験結果では、ＳｉＯ２に対するエツチ
ング選択比は、ガス圧力、高周波電力等のある条件のも
とでは、それぞれ３０および５０以上さ非常に高い値が
得られた。Molybdenum (Mo), tungsten (W), titanium (T)
i), tantalum (Ta) and these silicon (Si)
Compounds are materials constituting semiconductor integrated circuits, such as gate electrode materials of MO8 type transistors, and any of these can be easily etched in plasma containing F by a reaction similar to the above reaction formula. Usually, M
The base of the gate electrode of an O8 transistor has a thickness of several tens of nanometers.
There is a thin gate oxide film of silicon dioxide (Sin2) with a thickness of m, and in order to minimize the etching of this gate oxide film during the etching process of the gate electrode, the etching rate of the gate electrode material in the gas plasma used is and Sio
Etching speed ratio of 2 (so-called etching selection ratio)
must be a sufficiently large value. In general, in plasma of fluorine compounds containing carbon such as CF4, the etching rate of 5i02 becomes considerably high, and a sufficient etching selectivity cannot be obtained.
NF3-gas plasma is used. According to experimental results obtained by the present inventors in which Mo and W were etched using SF6 gas using a method called reactive sputter etching or reactive ion etching, the etching selectivity relative to SiO2 was determined under certain conditions such as gas pressure and high frequency power. Under these conditions, very high values of over 30 and 50 were obtained, respectively.
このように、ＳＦ６ガスは、Ｍｏ％Ｗに限らずＴｉＴａ
およびこれらのＳｉ化合物からなるゲート電極材料を下
地ゲーＩ・酸化膜５ｉ０２に対して高い選択比でドライ
エツチングするのに有効であるが、本発明者等の実験検
討の結果、次のような問題のあることが見出された。す
なわち、ＳＦ６ガスのグロー放電プラズマ中で、反応性
スパッタエツチング法により上記のゲート電極材料をエ
ツチングすると、第１図に示したように、下地表面に著
しいエツチング残渣１０が残り、長時間のオーバーエツ
チングを施しても容易に除去できなかった。さらに、レ
ジストマスク１１の端部に沿ってゲート電極１２が裾を
引いて形成され、長時間のオーバーエツチングを施して
も、裾を引いた形状が変化せず、結局、レジストマスク
寸法よりも大きな寸法のゲート電極が形成された。In this way, SF6 gas is not limited to Mo%W but also TiTa.
Although it is effective for dry etching gate electrode materials made of these Si compounds with a high selectivity with respect to the underlying gate I/oxide film 5i02, as a result of experimental studies conducted by the present inventors, the following problems were found. It was found that there is. That is, when the above gate electrode material is etched by the reactive sputter etching method in glow discharge plasma of SF6 gas, a significant etching residue 10 remains on the underlying surface as shown in FIG. It could not be easily removed even after applying. Furthermore, the gate electrode 12 is formed with a skirt along the edge of the resist mask 11, and even if over-etching is performed for a long time, the shape of the gate electrode 12 does not change, and the gate electrode 12 ends up being larger than the resist mask dimension. A gate electrode with dimensions was formed.
本発明の目的は、上記のように、Ｍｏ、Ｗ、Ｔｉ。 As mentioned above, the object of the present invention is to use Mo, W, and Ti.
Ｔａ、およびそれらのＳｉ化合物からなる材料をＳＦ６
プラズマでドライエツチングする時に生じるエツチング
残渣やパターン端部の裾引き現象を解消して、寸法精度
の高いエツチング方法を提供することにある。SF6 is a material consisting of Ta and their Si compounds.
It is an object of the present invention to provide an etching method with high dimensional accuracy by eliminating etching residues and skirting phenomena at pattern edges that occur when dry etching is performed using plasma.
本発明の基礎となった実験について以下に説明する。 The experiments that formed the basis of the present invention will be described below.
通常、ドライエツチングでは、被エツチング試料を真空
槽からなるエツチング室内の所定の場所に配置して、エ
ツチング室を十分排気したのち、ＳＦ６等のガスを所定
の流量で導入して同時に一定の排気速度でこれを排気す
ることにより、エツチング室内の圧力を１〜１００Ｐａ
程度の所定圧力に一定に制御して放電によりプラズマを
発生する。Normally, in dry etching, the sample to be etched is placed at a predetermined location in an etching chamber consisting of a vacuum chamber, and after the etching chamber is sufficiently evacuated, a gas such as SF6 is introduced at a predetermined flow rate, and at the same time the etching rate is maintained at a constant pumping speed. By exhausting this, the pressure inside the etching chamber is reduced to 1 to 100 Pa.
Plasma is generated by electric discharge under constant control at a predetermined pressure.
−この方法で、Ｍｏ、 Ｗ、 Ｔｉ、 Ｔａあるいはそ
れらのＳｉ化合物をＳＦ６プラズマでエツチングする際
に発生する前記したエツチング残渣およびパターン端部
の裾引き現象は、実験の結果、ＳＦ、ガスを導入する前
の到達真空度に依存し、到達真空度が高いはど残渣が生
じ易く、到達真空度が低い場合の方が残渣が少い傾向が
あるのが見出された。到達真空度が低い場合、エツチン
グ室内に吸着ガス等が多量に残渣しており、ＳＦ６プラ
ズマを発生させてエツチングしている際中に吸着ガスの
脱離等によってプラズマ中のガス組成が変化１７、エツ
チング性状が異ったと考えられる。本実際では、到達真
空度が低い場合のエツチング室内の主な残留ガスはＮ２
．０゜、Ｎ２０と考えて、これらをＳＦ６ガスに添加し
てエツチングする方法を試みた結果、Ｎ２を少量混合す
ることが、上記のエツチング残渣やパターン端部の裾引
きの発生しないエツチングを実現するのに有効であるこ
とが判明１．た。- As a result of experiments, the above-mentioned etching residue and tailing phenomenon at the edge of the pattern that occur when Mo, W, Ti, Ta, or their Si compounds are etched with SF6 plasma can be solved by introducing SF gas. It was found that it depends on the ultimate vacuum level before the process, and that residues are more likely to be formed when the ultimate vacuum level is high, and there is a tendency for there to be less residue when the ultimate vacuum level is low. When the ultimate vacuum level is low, there is a large amount of adsorbed gas remaining in the etching chamber, and during etching by generating SF6 plasma, the gas composition in the plasma changes due to desorption of the adsorbed gas, etc.17. It is thought that the etching properties were different. In this actual situation, the main residual gas in the etching chamber when the ultimate vacuum is low is N2.
．． 0° and N20, and tried a method of etching by adding these to SF6 gas, and found that mixing a small amount of N2 achieves etching without the above-mentioned etching residue or skirting at the edge of the pattern. It was found to be effective for 1. Ta.
本発明は、上記の実験結果に基づき、ＳＦ６に少量のＮ
２を混合したガスプラズマを用いて、 Ｍｏ 。Based on the above experimental results, the present invention provides a small amount of N to SF6.
Mo using a gas plasma mixed with 2.
Ｗ、Ｔｉ、Ｔａ、もしくはそれらのＳｉ化合物をエツチ
ングを行うことにより、エツチング残渣の生じない上記
物質のエツチングを行うことを特徴とする。A feature of this method is that by etching W, Ti, Ta, or their Si compounds, the above-mentioned substances can be etched without producing any etching residue.
本発明の効果のよって来る原因は明らかではないが、本
発明者等の推測では、レジストマスクあるいはエツチン
グ室内の残留ガスに起因する炭素あるいは酸素がガスプ
ラズマ中に混入し、Ｍｏ、Ｗ等のエツチング中にこれら
の炭化物もしくは酸化物が形成され、これらが難エツチ
ング性であるために残渣になり易いと考えられる。ＳＦ
６にＮ２を混合するとプラズマ中で生成するＮラジカル
が、炭化物もしくは酸化物のＣもしくはＯをＣＮ、ＯＮ
に転化させて除去されて残渣のないエツチングが可能に
なると考えられる。パターン端部に裾を引く現象が解消
できるのも同様な機構によると考えられる。Although the cause of the effects of the present invention is not clear, the inventors have speculated that carbon or oxygen from the resist mask or residual gas in the etching chamber is mixed into the gas plasma, causing etching of Mo, W, etc. It is thought that these carbides or oxides are formed in the film, and because these are difficult to etch, they tend to become residues. science fiction
When N2 is mixed with 6, N radicals generated in the plasma convert C or O of carbides or oxides into CN, ON.
It is believed that this process is converted into and removed, allowing for residue-free etching. It is thought that a similar mechanism is also responsible for eliminating the phenomenon of hems being drawn at the ends of the pattern.
ＳＦ６に混合するＮ２の混評は容量％で１０優を超える
と、Ｍｏ、 Ｗ％Ｔｉ、Ｔａ等のエツチング速度が著し
く低下するため、これらの材料の下地となるＳ ＋ ０
２ （’）エツチング速度との比が低下するため、実用
上不適格となる。このため、Ｎ２の混合率はＳＦ６に対
し、１０容量チ以下、更に望ましくは３〜７容量チがエ
ツチング選択比を１０〜２０倍以上の実用的な値に維持
したまま、上記の残渣除去の効果を実現する上で好まし
い。The mixed reputation of N2 mixed with SF6 is that if the volume % exceeds 10, the etching rate of Mo, W% Ti, Ta, etc. will decrease significantly, so the S + 0 that is the base of these materials will decrease.
2 (') The ratio to the etching rate decreases, making it unsuitable for practical use. For this reason, the mixing ratio of N2 to SF6 should be 10 volumes or less, more preferably 3 to 7 volumes, to maintain the etching selectivity at a practical value of 10 to 20 times or more while removing the above residue. Preferable for achieving the effect.
また、ＳＦ６に混合するガス吉してＡｒ、Ｈｅ１Ｈ２等
を用いた場合、このうちＡｒをＳＦ６に混合する場合に
ついて、上記のＳＦ６＋Ｎ２と同様にエツチング残渣な
く、パターンの裾引き現象も少ないエツチングが実現で
きるこ吉が実験の結果明らかになった。この場合、上記
の炭化物あるいは酸化物と考えられるエツチング残渣と
なり易い物質は、プラズマ中に生成するＡｒイオンによ
るスパッタ効果により除去されるものであろう。ＳＦ６
にＡｒを混合する場合は、Ａｒ混合量が５０容量チ程度
まで、エツチング速度の低下等の望ましくない副次効果
は生じず、５０容易チ以下で任意の混合比率を選択でき
るメリットがある。Furthermore, when Ar, He1H2, etc. are used as a gas to be mixed with SF6, when Ar is mixed with SF6, etching is achieved with no etching residue and less pattern tailing phenomenon, similar to the above-mentioned SF6+N2. Dekikokichi was revealed as a result of an experiment. In this case, the above-mentioned carbides or oxides, which tend to become etching residues, will be removed by the sputtering effect of Ar ions generated in the plasma. SF6
When Ar is mixed with Ar, no undesirable side effects such as a decrease in etching speed occur until the amount of Ar mixed is around 50 volumes, and there is an advantage that an arbitrary mixing ratio can be selected within 50 volumes or less.
以下、本発明を実施例を参照して詳しく説明する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
実施例１
エツチング室内の高周波電極上に被エツチング試料を載
置する方式の反応性スパッタエツチング装置を用いて、
Ｍｏ％Ｗ％Ｔｉ％Ｔａの薄膜が被着されたウェーハ状試
料のエツチングを行った。エツチング室内にＳＦ６のみ
を５０ｍ ｌ！／ｍ ｉ ｎの流量で導入し、一定の排
気速度で排気して、エツチング室内のＳＦ６圧力を２０
Ｐａに一定に保ったのち、高周波゛電極に１３．５６
ＭＴ−（ｚの高周波電力を電力密度０．３５Ｗ／ｃｍ２
で印加しプラズマを発生させて、エツチングを行った。Example 1 Using a reactive sputter etching apparatus in which a sample to be etched is placed on a high-frequency electrode in an etching chamber,
A wafer-shaped sample coated with a thin film of Mo%W%Ti%Ta was etched. 50ml of SF6 only in the etching chamber! SF6 pressure in the etching chamber was increased to 20% by introducing at a flow rate of /min and exhausting at a constant exhaust speed.
After keeping the Pa constant, the high frequency electrode was set at 13.56
MT-(z high frequency power at power density 0.35W/cm2
Etching was performed by generating plasma.
被エツチング試料がＷの場合、厚さ３００ｎｍのＷ膜は
約１分でエツチングが終了して、下地のＳｉＯ２膜が露
出したが、引き続き２分間のオーバーエツチングを施し
た。エツチングの試料表面を走査型電子顕微鏡で観察す
ると第１図に示すよう？こ大きさ５０ｎｍ程度の残渣１
０が試料表面に多数観察された。次に、同様な試料を、
ＳＦ６．５０ｍ／／ｍｉｎ、１”Ｊ２； ３ｍ／／ｍｉ
ｎを同時にエツチング室に導入して、上記と同様の手続
きに従ってエツチングすると、第２図に示したように残
渣がなく、かつ第１図のような裾引きのないレジストマ
スク寸法に忠実なパターンをエツチング形成することが
できた。このとき、厚さ３００ ｎｍのＷ膜のエツチン
グ時間は約１．５分であり、オーバーエツチングは１．
５分さした。When the sample to be etched was W, the etching of the 300 nm thick W film was completed in about 1 minute and the underlying SiO2 film was exposed, but over-etching was subsequently performed for 2 minutes. When the surface of an etched sample is observed with a scanning electron microscope, it looks as shown in Figure 1. Residue 1 with a size of about 50 nm
Many 0s were observed on the sample surface. Next, a similar sample is
SF6.50m//min, 1”J2; 3m//mi
When N is introduced into the etching chamber at the same time and etched according to the same procedure as above, a pattern that is faithful to the resist mask dimensions without residue as shown in Figure 2 and without skirting as shown in Figure 1 can be obtained. It was possible to form it by etching. At this time, the etching time for a W film with a thickness of 300 nm was about 1.5 minutes, and the overetching was 1.5 minutes.
It took 5 minutes.
以上の結果は、Ｍｏ、Ｔｉ、Ｔａの薄膜をエツチングす
る場合も同様であった。The above results were the same when etching thin films of Mo, Ti, and Ta.
実施例２
実施例１においてＳＦ６に混合するガスをＮ２の替りに
Ａｒとし、ＳＰ６５０ｍ／’／ｍｉｎに対してＡｒを２
０ｍＪ／ｍｉｎの割合で混合してエツチングした場合に
も実施例１と同様にエツチング残渣のないエツチングが
実現できた。ただし、この場合実施例１と異なり、Ａｒ
の混合によって５ｉｎ２のエツチング速度が、約５ ｎ
ｍ／ｍ ｉ ｎから１５ ｎｍ／ｍ ｉ ｎ程度に増
大した。Example 2 In Example 1, the gas mixed with SF6 was Ar instead of N2, and Ar was changed to 2 for SP650m/'/min.
Even when etching was performed by mixing at a rate of 0 mJ/min, etching without any etching residue could be achieved as in Example 1. However, in this case, unlike Example 1, Ar
The etching rate of 5in2 is increased by mixing approximately 5n
m/min increased to approximately 15 nm/min.
実施例３
実施例１及び２と同様な方法で、Ｍｏ 、 Ｗ、 Ｔｉ
。Example 3 In the same manner as in Examples 1 and 2, Mo, W, Ti
.
Ｔａのいずれかの８＋化合物をエツチングした場合も、
ＳＦ６にＮ２を５容量係もしくはＡｒを３０容量怖混合
した結果、残渣の少ないエツチングができた。When etching any 8+ compound of Ta,
As a result of mixing SF6 with 5 volumes of N2 or 30 volumes of Ar, etching with less residue was achieved.
以上、説明したように、本発明によれば、Ｍｏ、Ｗ、
Ｔｉ 、 Ｔａもしくはそれらの８ｉ化合物のエツチン
グを残渣を生じることなく、またパターン端部に裾を引
くことなく行うことができるので、パターン寸法精度が
高く、エツチング残渣によるパターン間短絡のない加工
ができる効果がある。As explained above, according to the present invention, Mo, W,
Etching of Ti, Ta, or their 8i compounds can be performed without creating a residue or drawing a hem at the edge of the pattern, resulting in high pattern dimensional accuracy and processing without short circuits between patterns due to etching residue. effective.
従って、本発明の方法は、上記の材料をＭＯ８型トラン
ジスタのゲート電極材料として用いる半導体集積回路の
装造方法として有効である。Therefore, the method of the present invention is effective as a method for fabricating a semiconductor integrated circuit using the above-mentioned material as a gate electrode material of an MO8 type transistor.
第１図はＳＦ６ガスのみのプラズマにより、レジストパ
ターンをマスクとして厚さ３００ｎｍのＷ膜をエツチン
グしたときの試料の断面図、第２図は、ＳＦ６にＮ２も
しくはＡｒを混合したガスのプラズマにより同様な試料
をエツチングした場合の試料の断面図である。
１０・・・・・・・・・エツチング残渣、１１・・・・
・・・・・レジストマスク、１２６１０１０．１．、ゲ
ート電極（Ｗ）、１３・・・・・・・・ゲート酸化膜、
１４・・・・・・・・・基板結晶０第 （図
禎 ２ 図Figure 1 is a cross-sectional view of a sample when a W film with a thickness of 300 nm was etched using a resist pattern as a mask using a plasma containing only SF6 gas. FIG. 3 is a cross-sectional view of a sample obtained by etching a sample. 10... Etching residue, 11...
...Resist mask, 1261010.1. , gate electrode (W), 13...gate oxide film,
14......Substrate crystal 0th (Figure 2)
Claims (1)
合したガスのグロー放電プラズマ中でモリブデン、タン
グステン、チタン、タンタルおよび／もしくはそれらの
硅素化合物をドライエツチングするこ吉を特徴とするド
ライエツチング方法。 ２、特許請求の範囲第１項記載のドライエツチング方法
において、六弗化イオウに混合する窒素の混合率が六弗
化イオウに対して１ｏ容量チ以下であることを特徴とす
るドライエツチング方法。 ３、特許請求の範囲第１項記載のドライエツチング方法
において、六弗化イオウに混合するアルゴンの混合率が
六弗化イオウに対して５ｏ容量チ以下であるこ吉を特徴
とするドライエツチング方法。[Claims] ■ A method for dry etching molybdenum, tungsten, titanium, tantalum and/or their silicon compounds in a glow discharge plasma of a gas containing sulfur hexafluoride and a little bit of nitrogen or argon. Characteristic dry etching method. 2. A dry etching method as claimed in claim 1, characterized in that the mixing ratio of nitrogen to sulfur hexafluoride is less than 10% by volume per sulfur hexafluoride. 3. A dry etching method according to claim 1, characterized in that the mixing ratio of argon to sulfur hexafluoride is less than 50% by volume per sulfur hexafluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17298483A JPS6065533A (en) | 1983-09-21 | 1983-09-21 | Dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17298483A JPS6065533A (en) | 1983-09-21 | 1983-09-21 | Dry etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6065533A true JPS6065533A (en) | 1985-04-15 |
Family
ID=15952010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17298483A Pending JPS6065533A (en) | 1983-09-21 | 1983-09-21 | Dry etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6065533A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133323A (en) * | 1987-11-19 | 1989-05-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0265132A (en) * | 1988-08-30 | 1990-03-05 | Sony Corp | Dry etching method |
| EP0418540A2 (en) * | 1989-08-11 | 1991-03-27 | Sanyo Electric Co., Ltd | Dry etching method |
| JPH0445528A (en) * | 1990-06-13 | 1992-02-14 | Nec Corp | Reactive dry etching |
| EP0514013A2 (en) * | 1991-04-22 | 1992-11-19 | Nec Corporation | Method for etching polysilicon film |
| JPH07147271A (en) * | 1993-11-26 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| US5521119A (en) * | 1994-07-13 | 1996-05-28 | Taiwan Semiconductor Manufacturing Co. | Post treatment of tungsten etching back |
| US5545290A (en) * | 1987-07-09 | 1996-08-13 | Texas Instruments Incorporated | Etching method |
| DE102015117448A1 (en) * | 2015-09-02 | 2017-03-02 | Von Ardenne Gmbh | Method and processing arrangement |
-
1983
- 1983-09-21 JP JP17298483A patent/JPS6065533A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545290A (en) * | 1987-07-09 | 1996-08-13 | Texas Instruments Incorporated | Etching method |
| JPH01133323A (en) * | 1987-11-19 | 1989-05-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0265132A (en) * | 1988-08-30 | 1990-03-05 | Sony Corp | Dry etching method |
| EP0418540A2 (en) * | 1989-08-11 | 1991-03-27 | Sanyo Electric Co., Ltd | Dry etching method |
| JPH0445528A (en) * | 1990-06-13 | 1992-02-14 | Nec Corp | Reactive dry etching |
| EP0514013A2 (en) * | 1991-04-22 | 1992-11-19 | Nec Corporation | Method for etching polysilicon film |
| JPH07147271A (en) * | 1993-11-26 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| US5521119A (en) * | 1994-07-13 | 1996-05-28 | Taiwan Semiconductor Manufacturing Co. | Post treatment of tungsten etching back |
| DE102015117448A1 (en) * | 2015-09-02 | 2017-03-02 | Von Ardenne Gmbh | Method and processing arrangement |
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