JPS6055160U - DC regeneration circuit - Google Patents

DC regeneration circuit

Info

Publication number
JPS6055160U
JPS6055160U JP14691483U JP14691483U JPS6055160U JP S6055160 U JPS6055160 U JP S6055160U JP 14691483 U JP14691483 U JP 14691483U JP 14691483 U JP14691483 U JP 14691483U JP S6055160 U JPS6055160 U JP S6055160U
Authority
JP
Japan
Prior art keywords
operational amplifier
differential operational
resistor
inverting input
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14691483U
Other languages
Japanese (ja)
Other versions
JPH0419880Y2 (en
Inventor
誠 今村
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP14691483U priority Critical patent/JPS6055160U/en
Publication of JPS6055160U publication Critical patent/JPS6055160U/en
Application granted granted Critical
Publication of JPH0419880Y2 publication Critical patent/JPH0419880Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例回路の構成図。第２図は従来例回路の構
成図。第３図は本考案第二実施例回路の構成図。第４図
はその動作説明用のタイムチャート。ａは入力信号の波
形を示し、ｂは出力信号の波形を示す。第５図は本考案
第二実施例回路の構成図。 ｌ　　Ｃｔ　　占 Ｒ２（ｂ） 一→曹−−−「→−ラ ＴＤ２　　“FIG. 1 is a configuration diagram of a conventional circuit. FIG. 2 is a configuration diagram of a conventional circuit. FIG. 3 is a configuration diagram of a circuit according to a second embodiment of the present invention. FIG. 4 is a time chart for explaining the operation. a indicates the waveform of the input signal, and b indicates the waveform of the output signal. FIG. 5 is a block diagram of a circuit according to a second embodiment of the present invention. l Ct Zhan R2 (b) 1 → Cao --- "→-La TD2 "

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）非反転入力が共通電位点に接続された差動演算増
幅器Ａ１と、 一端が信号入力に接続され他端が上記差動演算増幅器の
反転入力に接続された第一の抵抗器Ｒ３と、 一端が上記差動演算増幅器の反転入力に接続され他端が
信号出力に接続された第二の抵抗器Ｒ２と、 上記信号出力にアノードが接続され上記差動演算増幅器
の出力にカソードが接続された第一のダイオードＤ１と
、 上記差動演算増幅器の出力にアノードが接続された第二
のダイオードＤ２と、 この第二のダイオードのカソードと共通電位点との間に
接続されたコンデンサＣ１と、上記第二のダイオードの
カソードと上記差動演算増幅器の反転入力との間に接続
された第三の抵抗器Ｒ３と を備えた直流再生回路。(1) A differential operational amplifier A1 whose non-inverting input is connected to a common potential point; and a first resistor R3 whose one end is connected to the signal input and the other end is connected to the inverting input of the differential operational amplifier. , a second resistor R2 having one end connected to the inverting input of the differential operational amplifier and the other end connected to the signal output; an anode connected to the signal output and a cathode connected to the output of the differential operational amplifier; a second diode D2 whose anode is connected to the output of the differential operational amplifier; and a capacitor C1 connected between the cathode of the second diode and a common potential point. , a third resistor R3 connected between the cathode of the second diode and the inverting input of the differential operational amplifier. （２）コンデンサと第三の抵抗器との間にバッファ増幅
回路が挿入された実用新案登録請求の範囲第（１）項に
記載の直流再生回路。(2) The DC regeneration circuit according to claim (1), in which a buffer amplifier circuit is inserted between the capacitor and the third resistor.
JP14691483U 1983-09-21 1983-09-21 DC regeneration circuit Granted JPS6055160U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14691483U JPS6055160U (en) 1983-09-21 1983-09-21 DC regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14691483U JPS6055160U (en) 1983-09-21 1983-09-21 DC regeneration circuit

Publications (2)

Publication Number Publication Date
JPS6055160U true JPS6055160U (en) 1985-04-18
JPH0419880Y2 JPH0419880Y2 (en) 1992-05-07

Family

ID=30326863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14691483U Granted JPS6055160U (en) 1983-09-21 1983-09-21 DC regeneration circuit

Country Status (1)

Country Link
JP (1) JPS6055160U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114381A (en) * 1985-11-13 1987-05-26 Canon Inc Feedback clamping circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53140342U (en) * 1977-04-13 1978-11-06
JPS55150515U (en) * 1979-04-14 1980-10-30

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53140342U (en) * 1977-04-13 1978-11-06
JPS55150515U (en) * 1979-04-14 1980-10-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114381A (en) * 1985-11-13 1987-05-26 Canon Inc Feedback clamping circuit

Also Published As

Publication number Publication date
JPH0419880Y2 (en) 1992-05-07

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