JPS6041249A - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6041249A
JPS6041249A JP14989583A JP14989583A JPS6041249A JP S6041249 A JPS6041249 A JP S6041249A JP 14989583 A JP14989583 A JP 14989583A JP 14989583 A JP14989583 A JP 14989583A JP S6041249 A JPS6041249 A JP S6041249A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit
base ribbon
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14989583A
Other languages
English (en)
Inventor
Naoharu Senba
仙波　直治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14989583A priority Critical patent/JPS6041249A/ja
Publication of JPS6041249A publication Critical patent/JPS6041249A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は樹脂モールドした混成集積回路装置に関するも
のである。
混成集積回路装置（以下、ＩＣ）は多種少量生産であシ
、形状が千差万別で自動化、省力化が非常に難しい、一
般の汎用ＩＣの形状に統一可能であるならば、前述の問
題も解決する。しかしながら従来の汎用ＩＣは、第１図
に示すようにベースリボン１に半導体素子３を接着剤５
を用いて接着し、次に接続線２を用いてベースリボン１
に接続しモールド樹脂４を用いて封止している。本構造
では多数の半導体素子、抵抗及び容量と回路構成を組入
れることは不可能である。
本発明の目的は上記欠点を除き、多数の半導体素子、抵
抗及び容量と回路構成を組入れられ、更にトランスファ
ーモールド蜆形法等により、量産性、信頼度が高く、且
つ安価な混成集積回路を提供することである。
本発明の特徴は、ベースリボンに絶縁層を設け、更に回
路構成を設け、能動素子及び受動素子を接続し、これを
樹脂モールドした混成集積回路にある。
灰に本発明を図面によシ詳細に説明する。第２図は本発
明の一実施例の平面図及び断面図である。
ベースリボン１の一部に絶縁層７を設け、その上に導電
体の回路６を置く、更に回路６上に半導体素子３、抵抗
８、容量９等を塔載し、必要接続部に接続線２を用いて
接続する。このため本発明によれば量産化及び省力化等
が容易なベースリボン方式のものに於いても、混成集積
回路の製造が可能となる。
【図面の簡単な説明】
第１図は従来の汎用ＩＣの断面図及び平面図、第２図は
本発明の一実施例の断面図及び平面図である。 なお図において、１・・・・・・ベースリボン、２・・
・・・・接続線、３・・・・・・半導体素子、４・・・
・・・モールド樹脂、５・・・・・・接着剤、６・・・
・・・導電体回路、７・・・・−・絶縁層、８・・・・
・・抵抗体、９・・・・・・容景、である。 ゛、−一、・ ＝３＝ 鼎　／　図

Claims (1)

    【特許請求の範囲】
  1. ベースリボンに絶縁層が設けられ、更に回路構成要素が
    設けられ、能動素子及び受動素子が接続され、しかる後
    に樹脂モールドされたことを特徴とする混成集積回路装
    置。
JP14989583A 1983-08-17 1983-08-17 混成集積回路装置 Pending JPS6041249A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14989583A JPS6041249A (ja) 1983-08-17 1983-08-17 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14989583A JPS6041249A (ja) 1983-08-17 1983-08-17 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS6041249A true JPS6041249A (ja) 1985-03-04

Family

ID=15484962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14989583A Pending JPS6041249A (ja) 1983-08-17 1983-08-17 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6041249A (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62265733A (ja) * 1986-05-13 1987-11-18 Nec Corp 混成集積回路装置
JPS6315447A (ja) * 1986-07-07 1988-01-22 Nec Corp 混成集積回路装置
FR2632454A1 (fr) * 1988-06-02 1989-12-08 Burr Brown Corp Circuit integre hybride encapsule dans un boitier en matiere plastique
US4908933A (en) * 1988-05-12 1990-03-20 Ibiden Co., Ltd. Method of manufacturing a substrate for mounting electronic components
US4949225A (en) * 1987-11-10 1990-08-14 Ibiden Co., Ltd. Circuit board for mounting electronic components
US5022960A (en) * 1989-05-01 1991-06-11 Ibiden Co., Ltd. Method of manufacturing circuit board for mounting electronic components
US5093713A (en) * 1989-01-30 1992-03-03 Kabushiki Kaisha Toshiba Semiconductor device package
US5096852A (en) * 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
US5124783A (en) * 1989-01-30 1992-06-23 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
US5446309A (en) * 1992-06-22 1995-08-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a first chip having an active element and a second chip having a passive element
EP1396885A1 (en) * 2002-09-03 2004-03-10 Hitachi, Ltd. Resin moulded automotive electronic control unit

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62265733A (ja) * 1986-05-13 1987-11-18 Nec Corp 混成集積回路装置
JPS6315447A (ja) * 1986-07-07 1988-01-22 Nec Corp 混成集積回路装置
US4949225A (en) * 1987-11-10 1990-08-14 Ibiden Co., Ltd. Circuit board for mounting electronic components
US4908933A (en) * 1988-05-12 1990-03-20 Ibiden Co., Ltd. Method of manufacturing a substrate for mounting electronic components
US5096852A (en) * 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
FR2632454A1 (fr) * 1988-06-02 1989-12-08 Burr Brown Corp Circuit integre hybride encapsule dans un boitier en matiere plastique
US5124783A (en) * 1989-01-30 1992-06-23 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
US5093713A (en) * 1989-01-30 1992-03-03 Kabushiki Kaisha Toshiba Semiconductor device package
US5088008A (en) * 1989-05-01 1992-02-11 Ibiden Co., Ltd. Circuit board for mounting electronic components
US5022960A (en) * 1989-05-01 1991-06-11 Ibiden Co., Ltd. Method of manufacturing circuit board for mounting electronic components
US5446309A (en) * 1992-06-22 1995-08-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a first chip having an active element and a second chip having a passive element
EP1396885A1 (en) * 2002-09-03 2004-03-10 Hitachi, Ltd. Resin moulded automotive electronic control unit
US7439452B2 (en) 2002-09-03 2008-10-21 Hitachi, Ltd. Multi-chip module packaging with thermal expansion coefficiencies

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