JPS6038936A - Receiver - Google Patents

Receiver

Info

Publication number
JPS6038936A
JPS6038936A JP14651383A JP14651383A JPS6038936A JP S6038936 A JPS6038936 A JP S6038936A JP 14651383 A JP14651383 A JP 14651383A JP 14651383 A JP14651383 A JP 14651383A JP S6038936 A JPS6038936 A JP S6038936A
Authority
JP
Japan
Prior art keywords
frequency
circuit
signal
output
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14651383A
Other languages
Japanese (ja)
Inventor
Mikihiko Kawamoto
川本　幹彦
Tadashi Nakagawa
中川　紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP14651383A priority Critical patent/JPS6038936A/en
Publication of JPS6038936A publication Critical patent/JPS6038936A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To save a narrow band filter or the like being an externally mounted component in case of circuit integration by obtaining a sound signal and a so- called stop signal for conducting digital tuning from a synchronism detecting circuit. CONSTITUTION:In receiving a certain broadcast radio wave corresponding to a frequency dividing ratio M of a programmable divider 10, when the level of an intermediate frequency signal obtained from a frequency mixing circuit 3 of a PLL circuit comprising 7, 8, 9, 3, 16 and 17 is large and the signal is locked accurately to the output of a reference frequency oscillating circuit 5, its lock detecting signal indicates the automatic search of a broadcast station. On the other hand, accurate locking is impossible, a central processing unit 20 changes the frequency dividing ratio of the divider 10. Since the PLL circuits have a prescribed lock-in range or capture range and the synchronism detecting circuits 18, 18' detect the said relation of synchronism, no narrow band filter is required.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、ＡＭ受信機に関し、特にディジタルテー−ニ
ングを行うＡＭ受信機に用いて好適な回路技術に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an AM receiver, and particularly to a circuit technique suitable for use in an AM receiver that performs digital tuning.

〔背景技術〕[Background technology]

ＡＭ受信機におけるディジタルチューニングは、自動選
局を行うものである。自動選局を行うためには、放送電
波を受信したことを検出し、その検出信号により他の放
送電波を選局する動作を一時的に中止させなければなら
ない。このため、いわゆるストップ信号が必要になる。Digital tuning in AM receivers performs automatic channel selection. In order to perform automatic channel selection, it is necessary to detect that a broadcast radio wave has been received, and use the detection signal to temporarily stop the operation of selecting other broadcast radio waves. For this reason, a so-called stop signal is required.

本願発明に先立ち、本発明者等は前記ディジタルチュー
ニングシステムにつき、種々の技術的検討を行った＠そ
の結果、下記の如き欠陥を有していることが判明した。Prior to the invention of the present application, the present inventors conducted various technical studies on the digital tuning system, and as a result, it was found that the digital tuning system had the following defects.

すなわち、前記ストップ信号を得るために、通常の中間
周波回路の後段に、特に狭帯域特性のフィルタを設ける
。そ【２で、前記フィルタの後段に検波回路や波形整形
回路を設け、狭帯域フィルタの出力信号から、波形整形
されたストップ信号を得ている。しかるに、前記回路構
成では、狭帯域フィルタ等をストップ信号を得るために
たけ設けねばならず、これがコスト高の一因になってい
るいることが、本発明者等の検討により明らかにされた
。また、ＡＭラジオ受信機は、現状の回路技術では半導
体集積回路化されているが、前記狭帯域フィルタは外付
は部品にしなければならカい。That is, in order to obtain the stop signal, a filter with particularly narrow band characteristics is provided at the subsequent stage of the normal intermediate frequency circuit. Second, a detection circuit and a waveform shaping circuit are provided after the filter, and a waveform-shaped stop signal is obtained from the output signal of the narrowband filter. However, in the circuit configuration described above, it is necessary to provide a large number of narrowband filters and the like in order to obtain a stop signal, and studies by the present inventors have revealed that this is a cause of high cost. Furthermore, although AM radio receivers are made into semiconductor integrated circuits using current circuit technology, the narrowband filter must be externally mounted as a component.

このために、外部接続端子も必要になり、これが集積度
向上の障害になっていることが、本発明者等の検討によ
り明らかにされた。For this reason, external connection terminals are also required, and studies by the present inventors have revealed that this is an obstacle to increasing the degree of integration.

更に、音声信号用とストップ信号を得るための検波回路
とを個別に設けた場合、中間周波数である４　５０　Ｋ
Ｈ２の第２高周波等が発生し易いこと−も、本発明者の
検討により明らかにされた。Furthermore, if a detection circuit for audio signals and a detection circuit for obtaining a stop signal are provided separately, the intermediate frequency of 450K
The inventor's study also revealed that the second high frequency of H2 is likely to occur.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、狭帯域フィルタ等の外付は部品を用い
ることなく、自動選局動作を行うＡＭ受信機を提供する
ことにある・ 本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面から明らかになるでおろ
９゜ 〔発明の概要〕 本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりであるＯ すなわち、音声信号とディジタルチューニンクを行うた
めの、いわゆるストップ信号とを、同期検波回路から得
て、ＩＣ化に際し外付は部品となる狭帯域フィルタ等を
削減するという本発明の目的を達成するものである。An object of the present invention is to provide an AM receiver that performs automatic channel selection without using external parts such as a narrow band filter.The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.9 [Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows. The purpose of the present invention is to obtain a so-called stop signal for performing digital tuning with an audio signal from a synchronous detection circuit, and to reduce the need for external narrowband filters and the like when integrated into an IC. be.

実施例１ なお、第１図に示すＡＭ受信機は、その主要部は特に限
足されないが、半導体集積回路内に借成されている。Embodiment 1 Although the main parts of the AM receiver shown in FIG. 1 are not particularly limited, they are borrowed within a semiconductor integrated circuit.

受信アンテナｌで受信されたＡ１１１’ｌ［熱綜周波信
号は高周波増幅回路２により増幅された後、周波数混合
回路３に供給される。The A111'l[thermocombinant frequency signal received by the receiving antenna l is amplified by the high frequency amplifier circuit 2 and then supplied to the frequency mixing circuit 3.

水晶振動子４によりその発振周波数が安定化された基準
周波数発振回路５は基準周波数ｆＲＥＦの発振出力信号
を第１の周波数ディバイタロに供給する。第１の周波数
ディバイダ６は所定の分周比を有することにより、その
出力より安定化された９ＫＨ２の分局出力信号を発生す
る。位相比較回路７はこの９　Ｋ’ｆ（２０分周出力信
号の位相を電子ス・イッテＳＷの出力０の信号の位相と
の差を検出し、この位相差に比例した出力電圧を発生す
る。ローパスフィルタ８は位相比較回路７の低周波出力
成分を局部発振回路９に供給し、この局部発振回路９は
その発振周波数がローパスフィルタ８よりの電圧によっ
て制御される如く電圧制御発振器（いわゆるＶＣＯ）の
形式に栂成されている。この局部発振回路９の出力信号
は周波数混合回路３に供給されるとともに、その分周比
Ｍがコントロール手段としての中央処理装置２０により
制御されるプログラマブル・ディバイダ１０に供給され
る。The reference frequency oscillation circuit 5, whose oscillation frequency has been stabilized by the crystal oscillator 4, supplies an oscillation output signal of the reference frequency fREF to the first frequency divider. Since the first frequency divider 6 has a predetermined frequency division ratio, it generates a stabilized 9KH2 divided output signal from its output. The phase comparator circuit 7 detects the difference between the phase of this 9 K'f (20 frequency divided output signal) and the phase of the output 0 signal of the electronic switch SW, and generates an output voltage proportional to this phase difference. The low-pass filter 8 supplies the low-frequency output component of the phase comparison circuit 7 to the local oscillation circuit 9, and the local oscillation circuit 9 is a voltage-controlled oscillator (so-called VCO) whose oscillation frequency is controlled by the voltage from the low-pass filter 8. The output signal of the local oscillation circuit 9 is supplied to the frequency mixing circuit 3, and a programmable divider 10 whose frequency division ratio M is controlled by the central processing unit 20 as a control means. supplied to

中央処理装置２０により制御された電子スイフチＳＷの
出力０が端子ａｌｃ接続された場合・位相比較回路７は
プログラマブル−ディバイダ１０の出力信号の周波数と
位相とを第１の周波数ディバイダ６の出力信号の周波数
と位相とに合致せしめる・ 従って、回路ブロック７．８，９．１０は第１のＰＬＬ
（いわゆるＰｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ）回路
を榴成する。さらに、受信すべきＡＭ放送局の放送周波
数を’ＢＲとすると、局部発振回路９０局部発振周波数
ｆ。ｓｃ　をこの放送周波数ｆＢＲより一定の中間周波
数’ＩＦ（例えば４５０　ＫＨ２）だけ高い値に設定す
ると、この一定の周波数σ）ｔセ間周波信号が中間周波
増幅回路１１の入力立１Ｍ子に供給される。When the output 0 of the electronic switch SW controlled by the central processing unit 20 is connected to the terminal alc, the phase comparator circuit 7 converts the frequency and phase of the output signal of the programmable divider 10 to that of the output signal of the first frequency divider 6. Therefore, circuit blocks 7.8 and 9.10 are the first PLL.
(so-called Phase Locked Loop) circuit. Further, if the broadcast frequency of the AM broadcast station to be received is 'BR, then the local oscillation circuit 90 has a local oscillation frequency f. When sc is set to a value higher than this broadcasting frequency fBR by a constant intermediate frequency 'IF (for example, 450 KH2), this constant frequency σ)t interval frequency signal is supplied to the input terminal 1M of the intermediate frequency amplifier circuit 11. Ru.

放送周波数１″ＢＲを９５４　ＫＨ２とし、中間周波数
ｆＩＦを４５０　ＫＨ２とすると、局部発振回路９０局
部発振周波数ｆ。ＳＣは１４ｏ４１（Ｈ２となり、中央
処理装置２０により制御されたプログラマブル・ディバ
イダ１０の分周比Ｍを１５６とすれば、１４０４／１５
６＝９ＫＨ２０周波数の出力がプログラマブル・ディバ
イダ１ｏの出力から得られ、端子ａ。If the broadcast frequency 1"BR is 954 KH2 and the intermediate frequency fIF is 450 KH2, then the local oscillation circuit 90 local oscillation frequency f.SC becomes 14o41 (H2), and the frequency division of the programmable divider 10 controlled by the central processing unit 20 If the ratio M is 156, then 1404/15
An output of 6=9KH20 frequency is obtained from the output of programmable divider 1o, terminal a.

０を介して位相比較回路７の他方の入力に供給される。0 to the other input of the phase comparator circuit 7.

従ｚ”（、Ｑ”ｒ　１のＰＬＬ回路７，８，９．１０は
局部発振回路９の局部発振出力信号の周波数と位相とを
基準周波数発振回路５の周波数と位相とにロックせしめ
る。The PLL circuits 7, 8, 9, and 10 of the secondary z''(, Q''r 1) lock the frequency and phase of the local oscillation output signal of the local oscillation circuit 9 to the frequency and phase of the reference frequency oscillation circuit 5.

ｉ−カる第１７７）ＰＬＬ回路７＃　８１９．ＩＱの０
ツク動作が完了した後、中央処理装置２ｏは電子スイッ
チＳＷを端子ａから端子すに切換える。一方、周波数混
合回路３の出力Ａｌ１子より得られた４　５０　ＫＨ２
の中間周波信号はリミウタ増幅器１６によってＡＭ成分
が除去された後、分周比５０の第２の周波数ディバイダ
１７に供給さすｌ、る。従って、４５０　ＫＨ，７，／
　５０二９ＫＩ−Ｉ２の第２の周波数ディバイダ１７の
出力信号は電子スイッチＳ　Ｗの端子す、ｏを介して位
相比較回路７の他方の入力に供給される。i-Cal No. 177) PLL circuit 7# 819. IQ of 0
After the checking operation is completed, the central processing unit 2o switches the electronic switch SW from terminal a to terminal S. On the other hand, 4 50 KH2 obtained from the output Al1 of the frequency mixing circuit 3
After the AM component is removed by the limiter amplifier 16, the intermediate frequency signal is supplied to a second frequency divider 17 with a division ratio of 50. Therefore, 450 KH,7,/
The output signal of the second frequency divider 17 of the 5029KI-I2 is supplied to the other input of the phase comparison circuit 7 via the terminals s, o of the electronic switch SW.

従って、回路プロ１．り７，８，９，３，１６゜１７は
第２のＰ　Ｌ　Ｔ、回路を構成し、この第２のＰＬＬ回
路は周波数混合回路３よりイコられる中間周波信号の周
波数と位相とを基準周波数発振回路５０周波数と位相と
に口・ンクせしめる。Therefore, Circuit Pro 1. 7, 8, 9, 3, 16° 17 constitute a second PLL circuit, and this second PLL circuit uses the frequency and phase of the intermediate frequency signal equalized by the frequency mixing circuit 3 as a reference frequency. Set the oscillation circuit 50 frequency and phase.

二重平衡差動回路に接続されたトランジスタＱ１〜Ｑ、
、Ｉにより構成された回路１８は、当業者間で良く知ら
れているように同期検波回路を構成する。transistors Q1-Q connected to a double-balanced differential circuit;
, I constitute a synchronous detection circuit, as is well known to those skilled in the art.

すなわち、トランジスタＱ、のベースに印加された入力
信号がトランジスタＱ、のペースに印加された同期信号
によってスイッチされ、負荷抵抗へに同期検波出力が得
られる。That is, the input signal applied to the base of transistor Q is switched by the synchronous signal applied to the pace of transistor Q, and a synchronous detection output is obtained to the load resistor.

本実施例においては同期検波回路１８は第２の周波数デ
ィバイダ１７の信号を第１の周波数ディバイダ６の信号
によって同期検波する。In this embodiment, the synchronous detection circuit 18 synchronously detects the signal from the second frequency divider 17 using the signal from the first frequency divider 6.

受信アンテナ１により受信された９　５４　ＫＨ２の周
波数’ＢＲの受信電界強度が十分大きな場合は周波数混
合回路３より得られる中間周波信号の振幅レベルも大と
なるため、最終的に同期検波回路１８より得られる同期
検波出力の振幅も大となる。コンデンサＣＩ　＋　Ｃ２
ｍ抵抗Ｒ１によって平滑された同期検波出力はレベル弁
別器１９に供給される。If the received electric field strength of the frequency 'BR of 954 KH2 received by the receiving antenna 1 is sufficiently large, the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 will also be large, so that the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 will be finally increased by the synchronous detection circuit 18. The amplitude of the obtained synchronous detection output also becomes large. Capacitor CI + C2
The synchronous detection output smoothed by m resistor R1 is supplied to level discriminator 19.

平滑された同期検波出力が所定の基準レベルより高い場
合、レベル弁別器１９の出力は高レベルとなり中央処理
装置２０はプログラマブル・ディバイダ１０の分周比Ｍ
を１５６のまま保持するとともに電子スイッチＳＷを端
子すから端子ａに再び切換える。When the smoothed synchronous detection output is higher than a predetermined reference level, the output of the level discriminator 19 becomes high level, and the central processing unit 20 sets the frequency division ratio M of the programmable divider 10.
is held at 156, and the electronic switch SW is switched from terminal A to terminal a again.

従って中間周波増幅回路１１の出力信号はＡＭ検波回路
１２により音声信号に彷調され、電力増幅器１３．出力
結合コンデンサ１４を介してスピーカ１５に供給され、
９５４　ＫＨ２の放送周波数ｆ　のＡＭ放送のオートサ
ーチが完了するとともＲ にこのＡＭ放送の再生動作が開始される。Therefore, the output signal of the intermediate frequency amplification circuit 11 is converted into an audio signal by the AM detection circuit 12, and the output signal is converted into an audio signal by the power amplifier 13. is supplied to the speaker 15 via the output coupling capacitor 14,
As soon as the automatic search for the AM broadcast of the broadcast frequency f of 954 KH2 is completed, the reproduction operation of this AM broadcast is started at R2.

これに対して、受信アンテナ１により受信された９　５
４　ＫＨ２の周波数’ＢＲの受信電界強度が極めて低い
場合は、最終的にレベル弁別器１９の出力は低レベルと
なり中央処理袋ｆｔ２０はプログラマブル・ディバイダ
１０の分周比Ｍを１５６から１５７に変換するとともに
電子スイッチＦ３Ｗを端子すから端子ａに切換え、９５
４　Ｉ（ＩＩ２の放送周波ｉｆＢ、のＡＭ放送の受信を
放棄する。In contrast, 9 5 received by receiving antenna 1
4 If the received electric field strength of the frequency 'BR of KH2 is extremely low, the output of the level discriminator 19 will eventually become a low level, and the central processing bag ft20 will convert the frequency division ratio M of the programmable divider 10 from 156 to 157. At the same time, switch the electronic switch F3W from terminal to terminal a, 95
4 Abandon reception of AM broadcasts on broadcast frequency ifB of I (II2).

このようにプログラマブル・デイノ（イタ１０σ）分周
比Ｍが１５７に変換されると、局部発振回路９０局部発
振周波数は９　ＫＨｚｘ　１５７−１４１３Ｋｎ２とな
る。従って、１４１３ＫＨ２−４５０ＫＨ２＝　９６３
　ＫＨ２！Ｄ放送周波数のＡＭ放送の受信を開始する。When the programmable Deino (Ita 10σ) frequency division ratio M is converted to 157 in this way, the local oscillation frequency of the local oscillation circuit 90 becomes 9 KHz x 157-1413Kn2. Therefore, 1413KH2-450KH2=963
KH2! Start receiving AM broadcasts on the D broadcast frequency.

この時、１４１３　ＫＩ（２の局部発振出力を発振する
局部発振回路９の周波数と位相とは第１のＰＬＬ回路７
，８，９．１０によって基準周波数発振回路５０周波数
と位相とにロックされる。At this time, the frequency and phase of the local oscillation circuit 9 that oscillates the local oscillation output of 1413 KI (2) are the same as those of the first PLL circuit 7.
, 8, 9.10, the reference frequency oscillation circuit 50 is locked to the frequency and phase.

かかる第１のＰＬＬ回路７，８，９．１０のロックｖ１
作が完了した後に中央処理装置ＩＨ’ｚ電子スイッチＳ
Ｗを端子ａから端子１）几切換え、第２のＰＬＬ回路７
，８，９，３，１６．１７は周波数混合回路３より得ら
れる中間周波信号の周波数と位相とを基皐周波数発振回
路の周波数と位オ目とにロックせしめる。Lock v1 of such first PLL circuit 7, 8, 9.10
After the operation is completed, the central processing unit IH'z electronic switch S
Switching W from terminal a to terminal 1), second PLL circuit 7
, 8, 9, 3, 16, and 17 lock the frequency and phase of the intermediate frequency signal obtained from the frequency mixing circuit 3 to the frequency and position of the base frequency oscillation circuit.

受信アンテナ１により受信された９　６３　ＫＨ２の周
波数ｆＢＲの受信電界強度が十分大きな場合は・ｖベル
弁別’５１９の出力は高レベルとなり中央処理装置２０
はプログラマブル・デイノ（イタｌＯσ）分周比Ｍを１
５７のまま保持するとともに電子スイッチＳＷを端子す
から端子ａに切換え、９６３ＫＨ２グ敬送周波数ｆＩＩ
ＲのＡＭ放送のオートサーチが完了するとともにこのＡ
Ｍ放送の再生動作が開始される。If the received electric field strength of the frequency fBR of 963 KH2 received by the receiving antenna 1 is sufficiently large, the output of the v bell discrimination '519 becomes a high level and the central processing unit 20
is the programmable Deino (Italoσ) dividing ratio M of 1
Keep it at 57 and switch the electronic switch SW from terminal to terminal a, and set the frequency fII to 963KH2.
When the automatic search for AM broadcasts in R is completed, this A
The reproduction operation of the M broadcast is started.

これに対して、受信アンテナ１により受信さり。On the other hand, the signal is received by receiving antenna 1.

た９　６３　ＫＨｚの周波数ｒＢＲの受信電界強度が極
めて低い場合、中央処理袋は２０はプロゲラマフ゛、Ｉ
＋／・ディμ・ｆダニ０の分周比Ｍを１５７から１５８
に変換するとともに電子スイッチＳＷを端子すから端子
ａＫ切換え、９５３　ＫＨ２の放送周波数ｆＢＲのＡＭ
放送の受信を放棄する。If the received field strength of the frequency rBR of 963 KHz is extremely low, the central processing bag 20
+/・di μ・f tick 0 frequency division ratio M from 157 to 158
At the same time, the electronic switch SW is switched from the terminal to the terminal aK, and the broadcasting frequency fBR of 953 KH2 is AM.
Abandon broadcast reception.

さらに、上述の同様な動作は十分大きな受信電界強度の
ＡＭ放送が検出されるまで紗りかえされ・オートサーチ
が達成される。Furthermore, the same operation as described above is repeated until an AM broadcast with a sufficiently large received field strength is detected, and an auto search is achieved.

ＡＧＣ回路１６はＡＭ検波回路１２に接続されることに
よりＡＧＯ電圧を発生し、高周波増幅回路３の利得と中
間周波増幅回路１１の利得とを制御する。The AGC circuit 16 is connected to the AM detection circuit 12 to generate an AGO voltage, and controls the gain of the high frequency amplifier circuit 3 and the gain of the intermediate frequency amplifier circuit 11.

実施例２ 第２図は、本発明の第２の実施例によるＡ　）Ａ受信機
のブロック・ダイアグラムを示し、第１図中と同等のプ
ロ、ツクには同一の参照番号を付してその説明を省略し
、特に異なる点について以下に説明する。Embodiment 2 FIG. 2 shows a block diagram of an A)A receiver according to a second embodiment of the present invention, in which the same components as in FIG. 1 are given the same reference numerals. A detailed explanation will be omitted, and particularly different points will be explained below.

特に第１図中のＡＭ検波回路１２と同期検波回路１８と
は、第２図においては共通の同期検波回路１８′によっ
て置換され、この同期検波回路１８′においてトランジ
スタＱ、のベースは中間周波増幅回路１１の出力信号に
よって駆動され、トランジスタＱｓ　、Ｑ、のペースは
第１の周波数ディパイダ６の中間ステージから４５０　
ＫＨ２０周波数ｆゆ、′の信号により駆動される。In particular, the AM detection circuit 12 and the synchronous detection circuit 18 in FIG. 1 are replaced by a common synchronous detection circuit 18' in FIG. Driven by the output signal of the circuit 11, the pace of the transistors Qs, Q, is 450 from the intermediate stage of the first frequency divider 6.
It is driven by a signal of KH20 frequency f,'.

まず、中央処理装置２０は電子スイッチＳＷの端子ａと
端子Ｏとを接続するとともに、プログラマブル・ディバ
イダｌＯの分周比Ｍを１５６に設定する。First, the central processing unit 20 connects the terminal a and the terminal O of the electronic switch SW, and sets the frequency division ratio M of the programmable divider IO to 156.

従って、位相比較回路７の一方の入力に、は第１の周波
数ディパイダ６より９　ＫＨ２０周波数ｆＲゆの信号が
印加されているため、局部発振回路９０局部発振周波数
’ｏｓｃは９　ＫＨｚｘ　１５６−１４０４ＫＨ２に設
定するとともに、第１のＰＬＬ回路７゜８．９．１０は
局部発振回路９の局部発振出力信号の周波数と位相とを
基準周波数発振回路５０周波数と位相とにロックする・ かかる第１のＰＬＬ回路７，８，９．１０のロック動作
が完了した後、中央処理装置２０は電子スイッチＳＷを
端子ａから端子すに切換える。一方、周波数混合回路３
の出力端子より得られた４　５０　ＫＨ２の中間周波信
号はり壮、２増幅器１６によってＡＭ成分が除去された
後、分局比５０の第２の周波敬ディパイダ１７に供給さ
れる。従って、４５０　ＫＨ２／　５０＝　９　Ｉ（Ｈ
，の第２の周波数ディバイダ１７の出力信号は電子スイ
ッチＳＷの端子す、Ｏを介して位相比較回路７の他方の
入力に供給される。Therefore, since a signal with a frequency fR of 9 KH20 is applied from the first frequency divider 6 to one input of the phase comparison circuit 7, the local oscillation frequency 'osc of the local oscillation circuit 90 becomes 9 KHz x 156-1404 KH2. At the same time, the first PLL circuit 7°8.9.10 locks the frequency and phase of the local oscillation output signal of the local oscillation circuit 9 to the frequency and phase of the reference frequency oscillation circuit 50. After the locking operations of the circuits 7, 8, 9, and 10 are completed, the central processing unit 20 switches the electronic switch SW from terminal a to terminal S. On the other hand, frequency mixing circuit 3
The intermediate frequency signal of 450 KH2 obtained from the output terminal of the intermediate frequency signal is supplied to a second frequency divider 17 with a division ratio of 50 after the AM component is removed by a second amplifier 16. Therefore, 450 KH2/50=9 I(H
, the output signal of the second frequency divider 17 is supplied to the other input of the phase comparison circuit 7 via the terminals S, O of the electronic switch SW.

従って、第２のＰＬＬ回路７，８，９，３゜１６．１７
は周波数混合回路３より得られる中間周波信号の周波数
と位相どを基準周波数発振回路５の周波数と位相とにロ
ックせしめる。Therefore, the second PLL circuit 7, 8, 9, 3°16.17
locks the frequency and phase of the intermediate frequency signal obtained from the frequency mixing circuit 3 to the frequency and phase of the reference frequency oscillation circuit 5.

受信アンテナ１より受信さハ、た９　５４　ＫＨｚの周
波数’ＢＲの受信電界強度が十分大きな場合は周波数混
合回路３より得られる中間周波信号の振幅レベルも大と
残るため、最終的に同期検波回路１８′より得られる同
期検波出力の振幅も犬となる。コンデンサＣ□　、Ｃ２
，抵抗Ｒ７によって平滑された同期検波出力はレベル弁
別器１９に供給される。If the received electric field strength of the frequency 'BR of 954 KHz received by the receiving antenna 1 is sufficiently large, the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 remains high, so that the signal is finally transmitted to the synchronous detection circuit. The amplitude of the synchronous detection output obtained from 18' also becomes a dog. Capacitor C□, C2
, the synchronous detection output smoothed by the resistor R7 is supplied to the level discriminator 19.

平滑された同期検波出力が所定の基準レベルよりも高い
場合、レベル弁別器１９の出力は高レベルとなり中央処
理装置２０はプログラマブル・ディバイダニ００分局比
Ｍを１５６の１ま保持するとともに電子スイッチＳＷを
端子すから端子ａに再び切換える。When the smoothed synchronous detection output is higher than a predetermined reference level, the output of the level discriminator 19 becomes a high level, and the central processing unit 20 maintains the programmable divider 00 division ratio M to 1 of 156 and turns on the electronic switch SW. Switch from terminal to terminal a again.

従って、中間周波信号回ｒ３１１の出力信号は同期検波
回路１８′により音声信号に復調され、入力結合コンデ
ンサＣ９ｅ電力増幅器］　３　、出力結合コンデンサ１
４を介してスピーカ１５に供給され、９５４ＫＨ２）放
送周波数’ＢＲのＡＭ放送のオートサーチが完了すると
ともにこのＡＭ放送の再生動作が開始される。Therefore, the output signal of the intermediate frequency signal circuit r311 is demodulated into an audio signal by the synchronous detection circuit 18', and the input coupling capacitor C9e power amplifier] 3, the output coupling capacitor 1
4 to the speaker 15 through 954KH2), the automatic search for the AM broadcast at the broadcast frequency 'BR is completed, and the reproduction operation of this AM broadcast is started.

こ幻、に対して、受信アンブナ１により受信されたｇ　
ｓ　４　ＫＨ，ｆ＞周波数ｆＲ□の受信電界強度が極め
て低い場合は、最終的にレベル弁別器１９の出力は低レ
ベルとなり中央処理装置２０はプログラマブルーディバ
イダｌＯの分局比Ｍを１５６から１５７に変換するとと
もに電子スイッチＳＷを端子すから端子ａに切換え、９
５４　ＫＨ２の放送周波数’ＢＲのＡＭ放送の受信を放
棄ブーる。g received by receiver Ambuna 1 for this illusion.
If the received electric field strength of s 4 KH,f>frequency fR□ is extremely low, the output of the level discriminator 19 will eventually become a low level, and the central processing unit 20 will change the division ratio M of the programmer blue divider IO from 156 to 157. At the same time as converting, switch the electronic switch SW from terminal to terminal a, 9
54 Abandon reception of AM broadcasting on KH2 broadcast frequency 'BR'.

以下、実施例１と同様な放送局ザーチの動作が実行され
る。Thereafter, the same broadcasting station search operation as in the first embodiment is performed.

実施例３ 第３図は、本発明の第３の実施例によるＦＭ受信機のブ
ロック１ダイアグラムを示す。Embodiment 3 FIG. 3 shows a block 1 diagram of an FM receiver according to a third embodiment of the invention.

受信アンテナ１で受信されたＦＭ無無局周波信号高周波
増幅回路２により増幅された後、周波数混合回路３に供
給される。The FM radio frequency signal received by the receiving antenna 1 is amplified by the high frequency amplification circuit 2 and then supplied to the frequency mixing circuit 3.

水晶振動子４によりその発振周波数が安定化゛された基
準周波数発振回路５は基準周波数ｆＲ１，，Ｆの発振出
力信号を第１の周波数デバイダ６に供給する。The reference frequency oscillation circuit 5, whose oscillation frequency has been stabilized by the crystal resonator 4, supplies an oscillation output signal of reference frequencies fR1, , F to the first frequency divider 6.

第１の周波数デバイダ６は所定の分周比を有することに
より周波数ｆｎ　］、、Ｆ’が１０．７　Ｉｆ（２の第
１分周出力と周波数ｒｎわが１０．７ＫＨ２の第２分周
出力とを発生する。The first frequency divider 6 has a predetermined frequency division ratio, so that the frequency fn ], , F' is the first frequency divided output of 10.7 If(2 and the second frequency divided output of frequency rn10.7KH2). occurs.

ＦＭ放送周波数’ＢＲを８２．３９ＭＨ，、とし、中間
周波数ｆＩＦを１０．７１’、７ＩＨ２とすると、局部
発振回路９０局部発振周波数ｆ。ＳＣは９８．０９　Ｍ
Ｈ２となり、中央処理装置２０により制御されたプログ
ラマブル・ディパイダニ００分周比Ｍを８７００とすれ
ば、９８．０９ＭＨ２／８７００＝　ｉ　ｏ、７ＫＨ２
）周波ａの出力がプログラマブル費ディバイダ１０ノ／
Ｊｊカから得られ、中央処理装置２ｏによって制御され
た電子スイッチＳＷの端子ａ、ｏを介して位相比較回路
７に供給される。When the FM broadcast frequency 'BR is 82.39MH, and the intermediate frequency fIF is 10.71', 7IH2, the local oscillation frequency f of the local oscillation circuit 90 is given. SC is 98.09M
H2, and if the programmable divider 00 frequency division ratio M controlled by the central processing unit 20 is 8700, 98.09MH2/8700=io, 7KH2
) Frequency a output is programmable cost divider 10/
Jj and is supplied to the phase comparator circuit 7 via terminals a and o of an electronic switch SW controlled by the central processing unit 2o.

位相比較回路７０出カは口〜パスフィルタ８を介して電
圧制御発振器として構成された局部発振回路９　（Ｃ供
給されるため、第１のＰＬＬ回路７゜８．９．１０は局
部発振回路９０局局部発振回路号の周波数と位相とを基
準周波数発振回路５０周波数と位相とにロック・せしめ
る。The output of the phase comparator circuit 70 is connected to the local oscillator circuit 9 configured as a voltage controlled oscillator through the pass filter 8. The frequency and phase of the local oscillation circuit signal are locked to the frequency and phase of the reference frequency oscillation circuit 50.

かかる第１０ＰＬＬ回路’７．ｙ　”　＃　９　、１０
）。Such 10th PLL circuit '7. y” #9, 10
).

ツク動作が完了した後、中央処理装置２ｏは亀子スイゾ
チＳＷを端子ａがら甥子すに切換える。一方、周波数混
合回路３の出方端子より得られた１０．７ＭＨ２の中間
周波信号はリミ、り増幅器１６によってＡＭ成分が除去
された後、分周比１０００の第２の周波数ディバイダ１
７に供給さｈ５る。従ッテ、Ｉ　Ｏ，７ＭＨ２／１００
０＝１０．７ＫＨ２の第２の周波数ディバイダ１７の出
方信号は゛重子スイッチＳＷの端子す、Ｏを介して位相
比較回路７の他方の入力に供給される。After the check operation is completed, the central processing unit 2o switches the terminal SW from terminal a to terminal a. On the other hand, the 10.7 MH2 intermediate frequency signal obtained from the output terminal of the frequency mixing circuit 3 is filtered by the amplifier 16 to remove the AM component, and then passed through the second frequency divider 1 with a frequency division ratio of 1000.
7 is supplied to h5. Jutte, I O, 7MH2/100
The output signal of the second frequency divider 17 of 0=10.7KH2 is supplied to the other input of the phase comparison circuit 7 via the terminals O and O of the multiplex switch SW.

従って・第２のＰＬＬ回路７．Ｂ、９，３゜１６．１７
は周波数混合回路３より得られる中間周波信号の周波数
と位相とを基準周波数発振回路５０周波数と位相とにロ
ックせしめる。Therefore, second PLL circuit 7. B, 9,3°16.17
locks the frequency and phase of the intermediate frequency signal obtained from the frequency mixing circuit 3 to the frequency and phase of the reference frequency oscillation circuit 50.

受信アンテナＩＫより受信さハた８２．３９ＭＨ２Ｏ周
波数ｆＢＨの受信電界強度が十分大きな場合は周波数混
合回路３より得られる中間周波信号め振幅レベルも大と
なるため、最終的に同期検波回路１８より得られる同期
検波出力の振１１５も犬となる。If the received field strength of the 82.39 MH2O frequency fBH received from the receiving antenna IK is sufficiently large, the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 will also be large, so that the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 will be large. The oscillation 115 of the synchronous detection output also becomes a dog.

コンデンサＣＩ　Ｉ　Ｃ２＋抵抗Ｒ１にょって平滑され
た同期検波出力が所定の基準レベルより高い場合、レベ
ル弁別器１９の出力は高レベルとなり中央処理装［２０
はプログラマブル・ディバイダｌＯの分周比を８７００
のまま保持するとともに電子スイ、ノチＳＷを端子すか
ら端子ａＫ再び切換える。When the synchronous detection output smoothed by the capacitor CI I C2 + resistor R1 is higher than the predetermined reference level, the output of the level discriminator 19 becomes a high level and the central processing unit [20
The division ratio of the programmable divider lO is 8700.
While holding it as it is, switch the electronic switch and notch SW to the terminal aK again.

従って、中間周波増幅回路１１の出力信号は郡相器２１
とトランジスタＱｙ　ｐ　Ｑｓ　＋　Ｑｏ　＋　Ｑｌｌ
ｂＱＩｔｅＱｔｔとにより借成された周知のクオドラチ
ュアＦＭ検波回路２２によってＦＭ復調され、このＦＭ
ＱｇＭ力信号は、ＦＭマルチプレックス・ステレオ復調
回路２３に供給寧り、る。がくして、このステレオ復調
回路２３より左チヤンネルオーディオ信号りと右チヤン
ネルオーディオ信号とが得られ、電力増幅器２４．．２
５を介してスピーカ２６．２７に供給さハる。Therefore, the output signal of the intermediate frequency amplifier circuit 11 is
and transistor Qy p Qs + Qo + Qll
The FM is demodulated by a well-known quadrature FM detection circuit 22 borrowed from bQIteQtt, and this FM
The QgM power signal is supplied to an FM multiplex stereo demodulation circuit 23. As a result, a left channel audio signal and a right channel audio signal are obtained from the stereo demodulation circuit 23, and the power amplifier 24. ．． 2
5 to speakers 26 and 27.

これに対して、受信アンテナ１により受信された８　２
．３９１！ｌ／ＩＨ２の周波数ｆＢＲの受信電界強度が
極めて低い場合は、最終的にレベル弁別器１９の出力は
低レベルとなり中央処理装ｆＱ　２０はプログラマブル
・ディバイダｉｏの分局比Ｍを８７００から８７０１に
変換するとともに電子スイッチｓｗを端子１〕から端子
ａに切換え、＋１２．３９ＭＨ，の放送周波数ｆ　のＦ
Ｍ放送の受信を放簗する。In contrast, 8 2 received by receiving antenna 1
．． 391! If the received electric field strength of the frequency fBR of l/IH2 is extremely low, the output of the level discriminator 19 will eventually become a low level, and the central processing unit fQ 20 will convert the division ratio M of the programmable divider io from 8700 to 8701. At the same time, the electronic switch sw is switched from terminal 1 to terminal a, and the broadcasting frequency f of +12.39MH is set.
Cannot receive M broadcasting.

ＩＲ 以下、実施例と同様な７７送局ザーチの動作が実行され
る。IR Thereafter, the same 77 station search operation as in the embodiment is executed.

実施例４ 第４図は、本発明の第４の実施例によるＦＭ受信機のブ
ロックダイアグラムを示し、第３ｒＩ！Ｊ中と同等のブ
ロックには同一の参照番号を付してその説明を省略し、
特に異なる点について以下に説明する。Embodiment 4 FIG. 4 shows a block diagram of an FM receiver according to a fourth embodiment of the present invention, in which the third rI! Blocks equivalent to those in J are given the same reference numbers and their explanations are omitted.
Particularly different points will be explained below.

特に第３図中の移相器２１とトランジスタＱ７゜Ｑｓ　
ｅ　Ｑｏ　ｒ　Ｑｔｏ　ｙ　Ｑ＋ｔ　ｓ　Ｑｌ！とによ
り栴成されたクオドラチェアＦＭ検波回路２２は第４図
においては省略されており、そのかわり第４図において
は第１のＰＬＬ回路７，８，９．１０はいわゆるＰＬＬ
＠ＦＭ検波回路としても動作い　ローノ（スフィルタ８
の出力よりＦＭ壱調出力信号が得られ１この信号はＦＭ
マルチプレックス復調回路２３に供給される。In particular, the phase shifter 21 and transistor Q7゜Qs in Fig. 3
e Qor Qto y Q+t s Ql! The quadra chair FM detection circuit 22 created by
@Also works as an FM detection circuit Ronos filter 8
An FM 1 tone output signal is obtained from the output of 1. This signal is an FM
The signal is supplied to the multiplex demodulation circuit 23.

第４図の放送局サーチの動作は、第３図のものと同様で
あり、その説明は省略する。The broadcast station search operation in FIG. 4 is the same as that in FIG. 3, and its explanation will be omitted.

以上の各実施例においては、中央処理装置２０によるプ
ログラマブル・デイノくイダ１０の分周比の保持あるい
は変更という放送局サーチの動作は中間周波数信号を同
期検波して得られた信号レベルの大小によって実行され
るため、従来のデジタルチューニングニオいてストップ
信号を得るための狭帯域フィルタ等が不要となり、ＩＣ
化に際しすなわち・プログラマブル・ディバイダ１０の
分周比Ｍに対応したある放送局の電波を受信器で受信し
た場合、第２のＰＬＬ回路７，８，９，３゜１６．１７
の周波数混合回路３より得られる中間周波信号の振巾レ
ベルが大きくかつこの中間周波信号の周波数と位相が基
準周波数発振回路の周波数と位相とに正確にロックする
時に、この中間周波信号と基準周波数発振出力信号との
同期検出信号はでの放送局のオートザーチを指示する。In each of the above embodiments, the broadcasting station search operation of maintaining or changing the frequency division ratio of the programmable decoder 10 by the central processing unit 20 is determined by the magnitude of the signal level obtained by synchronously detecting the intermediate frequency signal. This eliminates the need for narrowband filters, etc. for obtaining stop signals in conventional digital tuning systems, and the IC
In other words, when the receiver receives radio waves from a certain broadcasting station corresponding to the division ratio M of the programmable divider 10, the second PLL circuits 7, 8, 9, 3°16.17
When the amplitude level of the intermediate frequency signal obtained from the frequency mixing circuit 3 is large and the frequency and phase of this intermediate frequency signal are accurately locked to the frequency and phase of the reference frequency oscillation circuit, this intermediate frequency signal and the reference frequency The synchronization detection signal with the oscillation output signal instructs automatic search of the broadcast station.

一方、周知々ようにＰＬＬ回路は所定のロックイン・レ
ンジ又はキャプチャー拳レンジを有する。On the other hand, as is well known, the PLL circuit has a predetermined lock-in range or capture range.

従って、プログラマブル・ディバイダ１０の分周比Ｍに
対応したある放送局の電波を受信器で受信した場合、第
２のＰＬＬ回路７，８，９，３゜１６．１７の周波数混
合回路３より得られる中間周波信号の振幅レベルが小さ
くかつこの中間周波信号の周波数と位相が基準周波数発
振回路の周波数と位相とに正確にロック不可能な時に、
この中間周波信号と基準周波数発振出力信号との同期検
出信号はプログラマブル・デイノ（イダの分周比へ４に
対応して受信アンテナ１により受信された放送局の受信
電界強度が極めて低く受信に不適当であることを指示し
、さらにこの同期検出信号により受信に適当な他の放送
局を受信するため中央処理装置２０はプログラマブル・
デイノ（イダ１０の分周比を別な値に変更する。Therefore, when a receiver receives a radio wave from a certain broadcasting station corresponding to the frequency division ratio M of the programmable divider 10, the signal obtained from the frequency mixing circuit 3 of the second PLL circuit 7, 8, 9, 3°16.17 When the amplitude level of the intermediate frequency signal generated is small and the frequency and phase of this intermediate frequency signal cannot be accurately locked to the frequency and phase of the reference frequency oscillation circuit,
The synchronization detection signal between this intermediate frequency signal and the reference frequency oscillation output signal is a programmable Deino (IDA frequency division ratio of 4). The central processing unit 20 uses a programmable system to indicate that the station is suitable, and to receive other broadcast stations that are suitable for reception based on this synchronization detection signal.
Deino (Change the frequency division ratio of Ida10 to a different value.

このように１第２０ＰＬＬ回路７，８，９゜３．１６．
１７が所定のロックイン・レンジ又はキャプチャー・レ
ンジを有するとともに、中間周波信号と基準周波数発振
出力信号との同期関係を同期検波回路１８．１８’によ
って検出するため一従来の狭帯域フィルタを不要とする
ことができたＯ〔効　果〕 （１）音声信号とディジタルチューニングを行う１こめ
のストップ信号を得るために同期検波器を供用すること
にエリ、ストップ信号を得るための狭７ｉｔ域フィルタ
等が不要になり、ＩＣ化に際して外付は部品を削減する
という効果が得られる。In this way, the 1st 20th PLL circuit 7, 8, 9°3.16.
17 has a predetermined lock-in range or capture range, and the synchronous detection circuit 18.18' detects the synchronous relationship between the intermediate frequency signal and the reference frequency oscillation output signal, eliminating the need for a conventional narrow band filter. (Effects) (1) A synchronous detector was used to obtain the first stop signal for digital tuning with the audio signal, and a narrow 7-bit filter, etc. was used to obtain the stop signal. is no longer necessary, and the effect of reducing the number of external parts when converting to an IC can be achieved.

（２）　音声検波器とストップ信号を得るための同期検
波器とを個別に設けることにより、ＩＣ化に際し狭帯域
フィルタ等の外付は部品を削減するという効果が得られ
る。(2) By separately providing an audio detector and a synchronous detector for obtaining a stop signal, it is possible to reduce the number of external parts such as a narrow band filter when integrated into an IC.

（３）　前記（２）により、同期検波器を駆動するため
のパルス信号が音声信号に影替を与えない。(3) According to (2) above, the pulse signal for driving the synchronous detector does not affect the audio signal.

以上に、本発明者によってなされた発明をその実施例に
もとづき具体的に説明したが、本発明は上記実施例に限
定されるものではなく、その要旨を逸脱しない範囲で種
々変形可能であることはいうまでもない・ 例えば、音声用とストップ信号を得るために、個別に同
期検波器を用いることもできろ。この場合、ビート妨害
の減少、音声信号の再生帯域の拡大、混信の減少等が可
能になる。Above, the invention made by the present inventor has been specifically explained based on the examples thereof, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say, for example, separate synchronous detectors could be used to obtain the audio and stop signals. In this case, it is possible to reduce beat interference, expand the reproduction band of audio signals, reduce interference, etc.

〔利用分野〕[Application field]

以上の説明では、主として本発明者によってなされた発
明をその背景となったオリ用分野であるＡＭ受信機に適
用した場合について説明したが、それに限定されるもの
ではない。In the above description, the invention made by the present inventor was mainly applied to an AM receiver, which is the original field of application, but the invention is not limited thereto.

例えば、カーラジオなどにも適用することができる。For example, it can be applied to car radios, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例を示すＡＭ受信機のブロッ
ク図である。 第２図は、本発明の他の実施例を示すＡＭ受信機のブロ
ック図でおる。 第３図は、本発明のさらに他の実施例を示すＦＭ受信機
のブロック図である。 第４図は本発明のさらに他の実施例を示すＦＭ受信機の
ブロック図である０ １・・・アンテナ、２・・・高周波増幅回路、３・・・
周波数信号回路、４・・水晶振動子、５・・・基準周波
数発振回路、６・・・周波数デバイダ、７・・・位相比
較回路、８・・・ローパスフィルタ、９・・・局部発振
回路、ｌＯ・・・プログラマブルデバイダ、１１・・・
中間周波数増幅回路、１３・・・パワーアンプ、１４・
・・コンデンサ、１５・・・スピーカ、１６・・・リミ
ッタアンプ、１７・・・周波数デバイダ、１８・・・同
期検波回路、１９・・・レベル弁別器、２０・・・中央
処理装置（ＣＰＵ）、２１・・・移相器、２２・・・ク
オドラチュアＦＭ検波回路、２３・・ＦＭマルチプレッ
クスステレオ復調回路、２４・−・電力増幅器、２５・
・・電力増幅器、２６゜２７・・・スピーカー、Ｑ、〜
Ｑ１２・・・トランジスタ、Ｒ１−Ｒ１３・・・抵抗％
Ｃ，〜Ｃ８・・・コンデンサ。FIG. 1 is a block diagram of an AM receiver showing one embodiment of the present invention. FIG. 2 is a block diagram of an AM receiver showing another embodiment of the present invention. FIG. 3 is a block diagram of an FM receiver showing still another embodiment of the present invention. FIG. 4 is a block diagram of an FM receiver showing still another embodiment of the present invention. 0 1... antenna, 2... high frequency amplification circuit, 3...
Frequency signal circuit, 4... Crystal resonator, 5... Reference frequency oscillation circuit, 6... Frequency divider, 7... Phase comparison circuit, 8... Low pass filter, 9... Local oscillation circuit, lO...Programmable divider, 11...
intermediate frequency amplification circuit, 13... power amplifier, 14.
... Capacitor, 15 ... Speaker, 16 ... Limiter amplifier, 17 ... Frequency divider, 18 ... Synchronous detection circuit, 19 ... Level discriminator, 20 ... Central processing unit (CPU) , 21... Phase shifter, 22... Quadrature FM detection circuit, 23... FM multiplex stereo demodulation circuit, 24... Power amplifier, 25...
...Power amplifier, 26゜27...Speaker, Q, ~
Q12...Transistor, R1-R13...Resistance%
C, ~C8... Capacitor.

Claims (1)

【特許請求の範囲】 １、放送電波受信の有無を検出する検出信号を、同期検
波器から得るように構成したことを特徴とするＡＭ受信
機。 ２、音声信号を検出する検波器と放送電波受信の有無を
検出する検出信号とを、単一の同期検波器から得るよう
に構成したことを特徴とするＡＭ受信機。 ８、音声信号を得る検波器と放送電波受信の有無を検出
する検出信号とを個別の検波器から得るとともに、前記
検出信号を得る検波器が同期検波により構成されている
ことを特徴とするＡＭ受信機。[Scope of Claims] 1. An AM receiver characterized in that a detection signal for detecting the presence or absence of broadcast radio wave reception is obtained from a synchronous detector. 2. An AM receiver characterized in that a detector for detecting an audio signal and a detection signal for detecting the presence or absence of broadcast radio wave reception are obtained from a single synchronous detector. 8. AM characterized in that a detector for obtaining an audio signal and a detection signal for detecting the presence or absence of broadcast radio wave reception are obtained from separate detectors, and the detector for obtaining the detection signal is configured by synchronous detection. Receiving machine.
JP14651383A 1983-08-12 1983-08-12 Receiver Pending JPS6038936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14651383A JPS6038936A (en) 1983-08-12 1983-08-12 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14651383A JPS6038936A (en) 1983-08-12 1983-08-12 Receiver

Publications (1)

Publication Number Publication Date
JPS6038936A true JPS6038936A (en) 1985-02-28

Family

ID=15409334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14651383A Pending JPS6038936A (en) 1983-08-12 1983-08-12 Receiver

Country Status (1)

Country Link
JP (1) JPS6038936A (en)

Similar Documents

Publication Publication Date Title
US4654884A (en) Radio receiver with switching circuit for elimination of intermodulation interference
JPH06509691A (en) Adjacent channel controller for radio receivers
US6211925B1 (en) Video intermediate-frequency signal processing device capable of receiving FM broadcasts
US4232393A (en) Muting arrangement of a radio receiver with a phase-locked loop frequency synthesizer
JP2001177779A (en) Video intermediate frequency processor
JPH09172584A (en) Sif signal processing circuit
JPH01300772A (en) Video intermediate frequency signal processing circuit
JP2710990B2 (en) Video intermediate frequency signal processing circuit
JPS6038936A (en) Receiver
WO1999007091A1 (en) Radio receiver
JPS6223162Y2 (en)
JP3804189B2 (en) Carrier signal selection receiver
JPS6214762Y2 (en)
JPS6223161Y2 (en)
US3982198A (en) Oscillators
JP3191380B2 (en) Multi-band radio IC
JPH0946184A (en) Automatic channel selection device
JPH04247723A (en) Detector for radio communication wave
JPS584268Y2 (en) Automatic tuning receiver sweep stop signal sending device
JPS6246354Y2 (en)
JPS6236368Y2 (en)
JPH028446Y2 (en)
JPH026687Y2 (en)
JPH0529882A (en) Pll synthesizer receiver
JP2000299646A (en) Double conversion tuner