JPS6027175A - Semiconductor element and manufacture thereof - Google Patents
Semiconductor element and manufacture thereofInfo
- Publication number
- JPS6027175A JPS6027175A JP13431883A JP13431883A JPS6027175A JP S6027175 A JPS6027175 A JP S6027175A JP 13431883 A JP13431883 A JP 13431883A JP 13431883 A JP13431883 A JP 13431883A JP S6027175 A JPS6027175 A JP S6027175A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- crystal layer
- silicon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 42
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000007667 floating Methods 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000012808 vapor phase Substances 0.000 claims 1
- 238000000206 photolithography Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 66
- 238000005516 engineering process Methods 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は半導体素子およびその製造技術、さらにはＰＩ
Ｎダイオードに適用して特に有効な技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor devices and their manufacturing technology, and furthermore, to PI
The present invention relates to a technique that is particularly effective when applied to N diodes.
［背景技術］
ＰＩＮダイオード素子はＰＮ接合ダイオードのＰ領域と
Ｎ領域との間にｉ型半導体（固有半導体）領域を挟んだ
素′子構造よりなる。ｉ型半導体領域としては、ｉ型の
シリコンウェハ（シリコン基板）が用いられる（たとえ
ば昭和５４年３月３０日発行の電子通信バンドブックの
Ｐ５３３）。このようなＰＩＮダイオード素子の一例と
しては第１図に示すような素子構造が考えられる。[Background Art] A PIN diode element has an element structure in which an i-type semiconductor (intrinsic semiconductor) region is sandwiched between a P region and an N region of a PN junction diode. An i-type silicon wafer (silicon substrate) is used as the i-type semiconductor region (for example, P533 of the Electronic Communication Band Book published on March 30, 1978). As an example of such a PIN diode element, an element structure as shown in FIG. 1 can be considered.
この第１図に示すＰＩＮダイオード素子構造においては
、１００〜１５０μｍの高抵抗（Ｎｉ）シリコン基板（
ウェハ）■を用いて、通常の拡散ホトリソグラフィ技術
によって、−主表面側にＰ型高濃度拡散領域２を形成す
る。リング状のＮ＋＋散領域３はＮｉ領域表面層の反転
を防止するチャンネルストッパ層となる。また、裏面側
にＮ＋＋濃度層４を形成した後、Ｐ＋領域側に絶縁膜２
０を介して銀（Ａｇ）バンプ電極５、裏面Ｎ＋＋域側に
銀（Ａｇ）膜にてコンタクト電極６を形成している。In the PIN diode element structure shown in FIG. 1, a high resistance (Ni) silicon substrate (100 to 150 μm) (
Using a wafer (1), a P-type high concentration diffusion region 2 is formed on the -main surface side by a normal diffusion photolithography technique. The ring-shaped N++ dispersed region 3 becomes a channel stopper layer that prevents the Ni region surface layer from inverting. Furthermore, after forming the N++ concentration layer 4 on the back surface side, an insulating film 2 is formed on the P+ region side.
A silver (Ag) bump electrode 5 is formed on the backside N++ region side via a silver (Ag) contact electrode 6 using a silver (Ag) film.
ところで、ＰＩＮダイオードに要求される電気的特性か
らＮｉ層の厚さは１００〜１５０．ｃｒｍが望ましく、
またＰ＋型領域及びＮ＋型領領域高濃度を保持する必要
があるので厚くすることができない。By the way, due to the electrical characteristics required for a PIN diode, the thickness of the Ni layer is 100 to 150 mm. crm is preferable,
Further, since it is necessary to maintain high concentration in the P+ type region and the N+ type region, it is not possible to increase the thickness.
そのため、前記技術で使用するウェハ結晶は１００〜１
５０μｍと薄くする必要がある。このため製造工程での
取扱い時にウェハの割れ等の問題が生じ易く、また、ウ
ェハの大口径化が図れず量産性に欠けることが本発明者
によって明らかとされた。Therefore, the wafer crystal used in the above technology is 100 to 1
It is necessary to make it as thin as 50 μm. The inventor of the present invention has found that problems such as cracking of the wafer are likely to occur during handling in the manufacturing process, and the wafer cannot be made larger in diameter, resulting in a lack of mass productivity.
［発明の目的］
本発明の目的は、ウェハを厚い状態で処理でき、その取
扱いが容易となり、割れ等の問題を防止できる半導体素
子およびその製造技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device and its manufacturing technology that can process a thick wafer, facilitate its handling, and prevent problems such as cracking.
本発明の他の目的は、ウェハの大口径化を実現すること
ができる半導体素子およびその製造技術を提供すること
にある。Another object of the present invention is to provide a semiconductor device and its manufacturing technology that can realize a large diameter wafer.
本発明の他の目的は、シリコンの単結晶層の厚さを精密
にコントロールでき、安定した特性を得ることのできる
半導体素子およびその製造技術を提供することにある。Another object of the present invention is to provide a semiconductor device and its manufacturing technology that can precisely control the thickness of a silicon single crystal layer and obtain stable characteristics.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面がら明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、シリコンの単結晶層と、該単結晶層の不純物
濃度よりも高い不純物濃度を持つシリコンの多結晶層と
を組み合わせて加工処理することにより、前記目的を達
成できるものである。That is, the above object can be achieved by processing a combination of a silicon single crystal layer and a silicon polycrystalline layer having an impurity concentration higher than that of the single crystal layer.
［実施例１］
第２図（ａｌ〜（ｄ）は本発明の一実施例である半導体
素子の製造過程を示す断面図である。[Example 1] FIGS. 2A to 2D are cross-sectional views showing the manufacturing process of a semiconductor device according to an example of the present invention.
この実施例においては、半導体素子の製造のため、まず
第２図（ａ）に示すように、格子間酸素濃度を小さくで
きるフローティングゾーン（Ｆ Ｚ）法により形成した
シリコンの単結晶層１またとえば比抵抗が１００〜５０
０Ω口で厚さが約３００μｍ程度のシリコン高抵抗単結
晶ウェハを用意する。この程度のウェハの厚さであれば
、その直径が４インチまたは５インチ程度の大口径ウェ
ハを用いることができ量産性を増すことができる。これ
は後にｉ層として用いられる。In this example, in order to manufacture a semiconductor device, first, as shown in FIG. 2(a), a single crystalline silicon layer 1 is formed using the floating zone (FZ) method, which can reduce the interstitial oxygen concentration. Specific resistance is 100-50
A silicon high resistance single crystal wafer with a 0Ω opening and a thickness of about 300 μm is prepared. With a wafer thickness of this level, a large-diameter wafer with a diameter of about 4 inches or 5 inches can be used, and mass productivity can be increased. This will be used later as the i-layer.
次に、第２図（ｂ）に示すように、この単結晶層１１の
片面（裏面）にシリコン多結晶層１２、たとえば低抵抗
高濃度ポリシリコン層をたとえば化学気相成長（ＣＶ
Ｄ）法を用いて、−例として比抵抗が０．０２Ω口で、
厚さ１５０μｍ程度の層として形成する。この多結晶シ
リコン層はモノシラン（ＳｉＨ４）ガスを５５０℃〜９
ｏｏ℃で熱分解して得られる。反応ガスとしてＰＨ３あ
るいはＡＳＨ３を混入し、容易にＮ＋型層となすことが
できる。Next, as shown in FIG. 2(b), a silicon polycrystalline layer 12, such as a low resistance high concentration polysilicon layer, is formed on one side (back side) of this single crystal layer 11 by chemical vapor deposition (CV).
D) Using the method - for example, when the resistivity is 0.02Ω,
It is formed as a layer with a thickness of about 150 μm. This polycrystalline silicon layer is coated with monosilane (SiH4) gas at 550°C to 90°C.
Obtained by thermal decomposition at oo°C. By mixing PH3 or ASH3 as a reactive gas, an N+ type layer can be easily formed.
シリコン単結晶層ｌｌ上に堆積させる層（以下、堆積層
という）として、多結晶シリコン層を用いることが重要
である。堆積層としてエピタキシャル層を用いることも
考えられるがあまり好ましくない。エピタキシャル層形
成のためには９５（１〜１２５０℃という高温での処理
が必要なため製造上好ましくない。さらに１５０．ｕｍ
という極く厚い堆積層を得るためには、多結晶シリコン
層を同じ厚さだけ堆積するのに比べ、上述の高温処理を
非常に長時間することになる。エピタキシャル層を最も
低い反応温度（９５０”Ｃ）で得られるモノシランガス
の熱分解法によれば、反応温度は９５０℃に押さえられ
るが、この方法では２〜３μｍ程度の厚さの堆積層しか
得られない。したがって、１５０μｍという厚い堆積層
を得るには多結晶シリコン層を用いるのが最もよい。It is important to use a polycrystalline silicon layer as the layer deposited on the silicon single crystal layer ll (hereinafter referred to as a deposited layer). Although it is conceivable to use an epitaxial layer as the deposited layer, it is not so preferred. In order to form an epitaxial layer, 95 (150.um
In order to obtain such an extremely thick deposited layer, the above-mentioned high-temperature treatment must be performed for a much longer time than depositing a polycrystalline silicon layer of the same thickness. According to the thermal decomposition method of monosilane gas, which allows the epitaxial layer to be formed at the lowest reaction temperature (950"C), the reaction temperature can be kept at 950"C, but with this method, only a deposited layer with a thickness of about 2 to 3 μm can be obtained. Therefore, it is best to use a polycrystalline silicon layer to obtain a deposited layer as thick as 150 μm.
次いで、単結晶層ＩＩの一生表面を適宜の研摩装置（図
示せず）で研摩して、該単結晶層１１をたとえば１５０
μｍ程度の厚さにする。それにより、第２図（Ｃ１に示
すように、それぞれ約１５０μｍのほぼ同じ厚さを持つ
高抵抗の単結晶層１１と低抵抗の多結晶層１２とからな
るシリコンウェハ１３が得られる。Next, the surface of the single crystal layer II is polished with a suitable polishing device (not shown), so that the single crystal layer 11 has a polishing surface of, for example, 150
The thickness is about μm. As a result, as shown in FIG. 2 (C1), a silicon wafer 13 consisting of a high resistance single crystal layer 11 and a low resistance polycrystalline layer 12 each having substantially the same thickness of about 150 μm is obtained.
シリコンウェハ１３はＰＩＮダイオードに好適なウェハ
である。ＰＩＮダイオードの電気的特性を支配するｉ層
として、ＦＺウェハから得た高品質の単結晶層１１を用
いることができる。また、ｉ層の厚さは１５０μｍと望
ましい値にできる一方、取扱い（ハンドリング）に不足
する厚さを多結晶シリコン層で補っているので取扱いが
容易である。Ｎ中型多結晶シリコン層１２は１５０μｍ
と厚いが、抵抗が０．０２Ωｃｍと極めて小さいのでさ
しつかえない。The silicon wafer 13 is a suitable wafer for PIN diodes. A high quality single crystal layer 11 obtained from an FZ wafer can be used as the i-layer which governs the electrical properties of the PIN diode. Further, while the thickness of the i-layer can be set to a desirable value of 150 μm, handling is easy because the thickness insufficient for handling is compensated for by the polycrystalline silicon layer. N medium polycrystalline silicon layer 12 has a thickness of 150 μm
Although it is thick, it is not a problem because the resistance is extremely small at 0.02 Ωcm.
その後、このシリコンウェハ１３に対してホトリソグラ
フィ技術、拡散技術を用いて半導体領域を形成した後、
電極部を形成することにより、第２図（ｄ）に示すよう
なＰＩＮダイオードが得られる。After that, after forming a semiconductor region on this silicon wafer 13 using photolithography technology and diffusion technology,
By forming the electrode portion, a PIN diode as shown in FIG. 2(d) can be obtained.
まず、研摩による欠陥等を除くため、単結晶層ｌｌ側の
表面を熱酸化し、この酸化膜をエツチングにより除去す
る。次に、シリコンウニハエ３の単結晶層１１の側の表
面にシリコン酸化膜またはホトレジスト膜をマスクとし
た熱拡散またはイオン打ち込みによりボロンを導入して
、Ｐ中型拡散領域１４を所望の深さまで形成する。また
、その周囲に所定の距離をおいてＮ＋型のガードリング
領域１５を同様にしてリン等を導入して形成する。First, in order to remove defects caused by polishing, the surface of the single crystal layer 11 is thermally oxidized, and this oxide film is removed by etching. Next, boron is introduced into the surface of the silicon sea urchin fly 3 on the side of the single crystal layer 11 by thermal diffusion or ion implantation using a silicon oxide film or a photoresist film as a mask, and a P medium-sized diffusion region 14 is formed to a desired depth. do. Further, an N+ type guard ring region 15 is formed at a predetermined distance around the guard ring region 15 by introducing phosphorus or the like in the same manner.
一方、シリコンウェハ１３の裏面側、すなわち多結晶層
１２の側の表面にはリン（Ｐ）のドーピング等でＮ十型
高濃度層１６を形成する。この後、絶縁膜２０を形成し
、Ｐ＋型領域１４上にコンタクトホールを形成し、単結
晶層１１の表面側の前記Ｐ＋型領域１４上に銀バンプ電
極１７を形成し、またその反対側（裏面側）のＮ＋型型
温濃度層１６裏面には銀のコンタクトホール１８を形成
する。On the other hand, on the back side of the silicon wafer 13, that is, the surface on the side of the polycrystalline layer 12, an N0-type high concentration layer 16 is formed by doping with phosphorus (P) or the like. After that, an insulating film 20 is formed, a contact hole is formed on the P+ type region 14, a silver bump electrode 17 is formed on the P+ type region 14 on the front side of the single crystal layer 11, and the opposite side ( A silver contact hole 18 is formed on the back surface of the N+ type temperature concentration layer 16 (on the back surface side).
なお、多結晶１ｆ１２はＮ＋型高濃度Ｆｉ １６となっ
ているので、前記Ｐ＋型領域１４、Ｎ生型ガードリング
領域１５の形成時における高温熱処理により、第２図（
ｄ）に示すように、Ｎ＋＋不純物が単結晶層１工側に拡
散されて、Ｎ＋＋層１９をその高温熱処理と同時に形成
する。Note that since the polycrystal 1f12 is N+ type high concentration Fi 16, the high temperature heat treatment at the time of forming the P+ type region 14 and the N raw guard ring region 15 results in the shape shown in FIG.
As shown in d), N++ impurities are diffused to the single crystal layer 1 side, forming an N++ layer 19 at the same time as the high temperature heat treatment.
また、単結晶層１１の表面側には、５ｉ０２膜およびそ
の上のフォスフオシリケードガラス膜よりなる絶縁膜２
０が形成される。Further, on the surface side of the single crystal layer 11, there is an insulating film 2 made of a 5i02 film and a phosphor silicate glass film thereon.
0 is formed.
［実施例２］
第３図は本発明による半導体素子の実施例２を示す断面
図である。[Example 2] FIG. 3 is a sectional view showing Example 2 of the semiconductor device according to the present invention.
本実施例２は半導体素子をメサ型の形状に形成すると共
に、高抵抗Ｎ （ｉ）層よりなる単結晶層１１をたとえ
ば約１３０μｍの厚さとし、その単結晶層１１０表面側
に深さ約３０μｍのＰ十拡散領域１４Ａを形成した高耐
圧用の半導体素子である。In this second embodiment, a semiconductor element is formed in a mesa shape, a single crystal layer 11 made of a high resistance N (i) layer has a thickness of, for example, about 130 μm, and a depth of about 30 μm is formed on the surface side of the single crystal layer 110. This is a high breakdown voltage semiconductor element in which a P diffusion region 14A is formed.
この実施例も、シリコンの単結晶Ｆｔｉｌの裏面側に、
該単結晶Ｎ１１の不純物濃度よりも高い不純物濃度を持
つシリコンの多結晶Ｊｅｆ１２を有しており、単結晶層
１１ＯＮ （ｉ）層の巾を均一にコントロールでき、安
定した性能が得られる等、実施例１と同様に優れた効果
を奏することができる。In this example as well, on the back side of the silicon single crystal Ftil,
It has a polycrystalline silicon JEF12 with an impurity concentration higher than that of the single crystal N11, and the width of the single crystal layer 11ON (i) can be controlled uniformly and stable performance can be obtained. Similar to Example 1, excellent effects can be achieved.
［効果］
（１）、シリコンの単結晶層上の堆積層を該単結晶層の
不純物濃度よりも高い不純物濃度を有するシリコンの多
結晶層としていることにより、半導体素子（ウェハ）を
厚さの厚い状態の素子として加工処理できるので、ウェ
ハの取扱いが容易となり、割れ等の問題の発生を防止す
ることができる。[Effects] (1) By making the deposited layer on the silicon single crystal layer a polycrystalline silicon layer having an impurity concentration higher than that of the single crystal layer, the thickness of the semiconductor element (wafer) can be reduced. Since the wafer can be processed as a thick element, the wafer can be easily handled and problems such as cracks can be prevented.
（２）、前記（１１により、半導体ウェハの大口径化が
実現できる。また、その取扱いが容易になる。(2) According to the above (11), it is possible to realize a large diameter semiconductor wafer. Also, the handling thereof becomes easy.
（３）、高抵抗層である単結晶層のＮ（ｉ）Ｊｉの厚さ
を精密にコントロールできるので、ばらつきのない、安
定した性能の半導体素子を得ることができる。(3) Since the thickness of the N(i)Ji single crystal layer, which is a high resistance layer, can be precisely controlled, it is possible to obtain a semiconductor device with consistent performance and stable performance.
［４１，ｉ層として高品質の単結晶ウェハから得られた
層を用いることができるので、良好な特性の半導体素子
が得られる。[41, Since a layer obtained from a high-quality single crystal wafer can be used as the i-layer, a semiconductor element with good characteristics can be obtained.
（５）、多結晶層のＮ＋型高濃度化をリンドーピングで
行うことができるので、Ｐ＋型不純物のだれを防止でき
、Ｐ＋型不純物プロファイルを急峻に形成でき、高周波
特性の良好な半導体素子を得ることが可能である。(5) Since the N+ type concentration of the polycrystalline layer can be increased by phosphorus doping, it is possible to prevent the P+ type impurity from sagging and form a steep P+ type impurity profile, resulting in a semiconductor device with good high frequency characteristics. It is possible to obtain.
（６）、多結晶層の不純物濃度を高くすることができる
ので、素子の表裏を電極端子とする半導体素子の場合に
は、基板厚みによる直列抵抗が、ハイトープポリシリコ
ンに置き換えられることにより下がり、素子の特性改善
を図ることができる。(6) Since the impurity concentration of the polycrystalline layer can be increased, in the case of semiconductor devices with electrode terminals on the front and back sides of the device, the series resistance due to the substrate thickness is reduced by replacing it with high top polysilicon. , it is possible to improve the characteristics of the element.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、半導体素子の構造は前記のものに限定される
ものではない。For example, the structure of the semiconductor device is not limited to the above.
また、素子の裏面側におけるＮ＋高濃度層の形成は、Ｐ
÷拡散層の形成後に、リンドープト・ポリシリコンのデ
ポジションにより形成することによって行ってもよい。In addition, the formation of the N+ high concentration layer on the back side of the element is
It may also be formed by depositing phosphorus-doped polysilicon after forming the diffusion layer.
［利用分野］
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＰＩＮダイオードに
適用した場合について説明したが、それに限定されるも
のではなく、たとえば、パワートランジスタ、パワーＩ
Ｃ１高耐圧ダイオード、高耐圧トランジスタ、バリキャ
ップダイオード、ツェナーダイオード、ショットキダイ
オード等の様々な半導体素子に適用できる。[Field of Application] In the above description, the invention made by the present inventor was mainly applied to the field of application, which is the background of the invention, which is the PIN diode, but the invention is not limited thereto. Power I
It can be applied to various semiconductor elements such as a C1 high voltage diode, a high voltage transistor, a varicap diode, a Zener diode, and a Schottky diode.
第１図は考えられる半導体素子の断面図、第２図（ａｌ
〜（ｄｌは本発明の実施例１である半導体素子の製造過
程を順次示す断面図、
第３図は本発明の実施例２である半導体素子の断面図で
ある。
１１・・・シリコンの単結晶層、１２・・・シリコンの
多結晶層、１３・・・シリコンウェハ、１４．１４Ａ・
・・Ｐ１型領域、１５・・・Ｎ＋型ガードリング領域、
１６・・・Ｎ＋型高濃度層、１７・・・銀バンプ電極、
１Ｂ・・・コンタクト電極、１９・・・Ｎ４″型層、２
０・・・酸化膜。
第 １ 図
第 ３ 図Figure 1 is a cross-sectional view of a possible semiconductor device, and Figure 2 (al
~(dl is a cross-sectional view sequentially showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 11...Silicone unit Crystal layer, 12... Polycrystalline layer of silicon, 13... Silicon wafer, 14.14A.
...P1 type region, 15...N+ type guard ring region,
16... N+ type high concentration layer, 17... Silver bump electrode,
1B... Contact electrode, 19... N4'' type layer, 2
0...Oxide film. Figure 1 Figure 3
Claims (1)
けられ、該単結晶層の不純物濃度よりも高い不純物濃度
を有するシリコンの多結晶層とを備えてなることを特徴
とする半導体素子。 ２、単結晶層が真性半導体の一生表面に不純物を拡散さ
せた拡散領域を有してなる高抵抗単結晶層であることを
特徴とする特許請求の範囲第１項記載の半導体素子。 ３、単結晶層と多結晶層とがほぼ同じ厚さであることを
特徴とする特許請求の範囲第１項記載の半導体素子。 ４、シリコンの単結晶層の裏面に、該単結晶層の不純物
濃度よりも高い濃度を有するシリコンの多結晶層を気相
成長させ、前記単結晶層を所要の厚さに研摩し、前記単
結晶層の一生表面に不純物を拡散させ、前記単結晶層の
一生表面および前記多結晶層の裏面に電極を形成するこ
とよりなる半導体素子の製造方法。 ５、単結晶層がフローティングゾーン法により形成され
た高抵抗単結晶ウェハであることを特徴とする特許請求
の範囲第４項記載の半導体素子の製造方法。 ６、多結晶層の不純物濃度がリンのドーピングにより高
濃度化されることを特徴とする特許請求の範囲第４項記
載の半導体素子の製造方法。[Claims] 1. Comprising a silicon single crystal layer and a silicon polycrystalline layer provided on the back side of the single crystal layer and having an impurity concentration higher than that of the single crystal layer. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the single crystal layer is a high resistance single crystal layer having a diffusion region in which impurities are diffused on the surface of an intrinsic semiconductor. 3. The semiconductor device according to claim 1, wherein the single crystal layer and the polycrystalline layer have approximately the same thickness. 4. A polycrystalline silicon layer having an impurity concentration higher than that of the single crystal layer is grown in vapor phase on the back surface of the single crystal layer of silicon, and the single crystal layer is polished to a required thickness. 1. A method for manufacturing a semiconductor device, which comprises diffusing impurities onto the surface of a crystal layer and forming electrodes on the surface of the single crystal layer and the back surface of the polycrystalline layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the single crystal layer is a high resistance single crystal wafer formed by a floating zone method. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the impurity concentration of the polycrystalline layer is increased by doping with phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13431883A JPS6027175A (en) | 1983-07-25 | 1983-07-25 | Semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13431883A JPS6027175A (en) | 1983-07-25 | 1983-07-25 | Semiconductor element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027175A true JPS6027175A (en) | 1985-02-12 |
Family
ID=15125498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13431883A Pending JPS6027175A (en) | 1983-07-25 | 1983-07-25 | Semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027175A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7800204B2 (en) | 2008-07-31 | 2010-09-21 | Mitsubishi Electric Corporation | Semiconductor device and method of fabricating the same |
-
1983
- 1983-07-25 JP JP13431883A patent/JPS6027175A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7800204B2 (en) | 2008-07-31 | 2010-09-21 | Mitsubishi Electric Corporation | Semiconductor device and method of fabricating the same |
| US8420496B2 (en) | 2008-07-31 | 2013-04-16 | Mitsubishi Electric Corporation | Semiconductor device and method of fabricating the same |
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