JPS60193380A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60193380A JPS60193380A JP4984484A JP4984484A JPS60193380A JP S60193380 A JPS60193380 A JP S60193380A JP 4984484 A JP4984484 A JP 4984484A JP 4984484 A JP4984484 A JP 4984484A JP S60193380 A JPS60193380 A JP S60193380A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- point metal
- layer
- film
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000004065 semiconductor Substances 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 43
- 238000002844 melting Methods 0.000 claims abstract description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 239000002019 doping agent Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 230000008018 melting Effects 0.000 claims description 32
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000002156 mixing Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 21
- 150000002500 ions Chemical class 0.000 abstract description 14
- 239000010409 thin film Substances 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 51
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000000243 solution Substances 0.000 description 5
- 238000005755 formation reaction Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241000272201 Columbiformes Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＭＯ８ＬＳＩで代表される高集積度半導体装置
の製造方法、特に浅い不純物ドープ層の表面あるいはゲ
ート多結晶シリコンあるいはそれら双方の表面が金属硅
化物層で被覆され低抵抗化されている半導体装置の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a highly integrated semiconductor device such as MO8LSI, and in particular to a method for manufacturing a highly integrated semiconductor device such as MO8LSI, in which the surface of a shallow impurity doped layer, the surface of gate polycrystalline silicon, or both surfaces are metal. The present invention relates to a method of manufacturing a semiconductor device coated with a silicide layer to reduce resistance.
（従来技術とその問題点）
近年、ＭＯ８電界効果トランジスタ（以下、ＭＯＳＦＥ
Ｔと略称する）は高密度集積回路の基本素子として広く
用いられておシ、スイッチング速度、利得等の電気的特
性の向上、更に集積回路の高密度化のためにチャネル長
の短縮が昧題となっている。(Prior art and its problems) In recent years, MO8 field effect transistor (hereinafter referred to as MOSFE)
(abbreviated as T) is widely used as a basic element of high-density integrated circuits, and it is becoming increasingly important to improve electrical characteristics such as switching speed and gain, and to shorten the channel length in order to increase the density of integrated circuits. It becomes.
チャネル長の短縮に伴なう閾値電圧の低下、ソース・ド
レイン間耐圧の低下等、いわゆる短チヤネル効果の抑制
のためソース・ドレイン電極となる不純物ドープ鳩の接
付深さをも浅くする必要があるが、シート抵抗上昇を引
き起こし、寄生抵抗の原因となる１、多くの場合、ソー
ス・ドレイン領域の延長部分を素子間相互接続配線とじ
て用いるがこの寄生抵抗のため信号の伝播遅延時間増大
や電圧降下など集積回路としての性能劣化を避けられな
い。また多結晶シリコン全周いたゲートｉｍ＃！。In order to suppress so-called short channel effects, such as a decrease in threshold voltage and a decrease in source-drain breakdown voltage due to a shortened channel length, it is necessary to reduce the bonding depth of the impurity-doped doves that serve as the source and drain electrodes. However, it causes an increase in sheet resistance and causes parasitic resistance1.In many cases, the extended portion of the source/drain region is used as interconnection wiring between elements, but this parasitic resistance increases signal propagation delay time and Performance degradation as an integrated circuit cannot be avoided, such as voltage drop. Also, the gate with polycrystalline silicon all around im#! .
の場合も、短チヤネル化のため加工精度の向上や高次配
線層の断線を回避しようとすると、厚さの低減は必須と
なシやはシシート抵抗の上昇を引き起こし寄生抵抗の原
因になる。In this case, in order to improve processing accuracy and avoid disconnections in higher-order wiring layers due to shorter channels, it is essential to reduce the thickness, which also causes an increase in sheet resistance and causes parasitic resistance.
これらシート抵抗上昇の対策としてソース・ドレインと
なる不純物ドープ層表面、更にゲート多結晶シリコン表
面を低抵抗率の金属硅化物層で被う方法が提案されてい
る。金属硅化物としては熱的安定性の観点からＭＯやＴ
ｉ等高融点金属の硅化物の使用が望ましい。ＭＯ硅化物
はシリコンプロセスに通常用いる７ツ酸系のエツチング
液に耐性が高いが固有抵抗率は１００μΩ・αと比較釣
部く、Ｔｉ硅化物は固有抵抗率がＭＯ硅化物の１／４〜
１１５程度と低抵抗化の観点では良好であるがフッ酸系
のエツチング液に容易に侵されるという様に単一の硅化
物のみでは、硅化物に要求される特性（低固有抵抗率、
劇薬品性４ｆ）すべてを同時に満足することは困難であ
る。この問題に対処するため第１図に示すような構造が
考えられる。すなわちＭＯＳＦＥＴの洩いソースφドレ
インとなる不純物ドープ層１０４とゲートとなる薄い多
結晶シリコン１０３０表面に、まず固有抵抗率の低いＴ
ｉ硅化物の如き第１の硅化物層１０５を被層し、更にそ
れに重ねてＭｏｉ化物の如きフッ酸系のエツチング液に
対１・する耐性に優れた第２の硅化物層１０６を被着し
た２層の硅化物層を設けた構造である。As a countermeasure to these increases in sheet resistance, a method has been proposed in which the surfaces of impurity-doped layers serving as sources and drains, as well as the gate polycrystalline silicon surfaces, are covered with metal silicide layers of low resistivity. From the viewpoint of thermal stability, MO and T are used as metal silicides.
It is desirable to use silicides of high melting point metals such as i. MO silicide is highly resistant to the 7-acid-based etching solution normally used in silicon processes, but its specific resistivity is 100 μΩ・α compared to that of Ti silicide, and the specific resistivity of Ti silicide is 1/4 to 1/4 that of MO silicide.
115, which is good from the viewpoint of low resistance, but it is easily attacked by hydrofluoric acid etching solutions.
It is difficult to satisfy all 4f) of harmful drug properties at the same time. In order to deal with this problem, a structure as shown in FIG. 1 can be considered. That is, first, a T layer with low specific resistivity is placed on the surface of the impurity doped layer 104 that will become the leaky source φ drain of the MOSFET and the thin polycrystalline silicon 1030 that will become the gate.
A first silicide layer 105 such as an i-silicide is coated, and a second silicide layer 106 having excellent resistance to a hydrofluoric acid-based etching solution such as a moi-silicide is superimposed on it. It has a structure with two silicide layers.
（発明の目的）
本発明の目的は知チャネルＭＩＳＦＥＴのソース・ドレ
インとなる浅い不純物ドープ層並びに薄いゲート多結晶
シリコンのいずれか一方あるいは両方の表面を旨融点金
属硅化物２層構造で被覆した構造の製造方法を提供する
ことである。(Objective of the Invention) The object of the present invention is to provide a structure in which either or both surfaces of the shallow impurity doped layer and the thin gate polycrystalline silicon that serve as the source and drain of the channel MISFET are coated with a two-layer structure of high melting point metal silicide. An object of the present invention is to provide a manufacturing method.
（発明の構成）
本発明によれば、少なくとも表面の一部に単結晶シリコ
ン層あるいは多結晶シリコン層もしくはそれら双方を備
えた基板上に第１の高融点金属膜を蛙積する工程と、■
族またはＶ族のドーパントイオンもしくは該ドーパント
イオンとシリコン結晶中にお−てｐ型あるいはｎ型を示
さない非ドーパントイオンとを重ねてイオン注入するこ
とによって前記単結晶シリコン層あるいは多結晶シリコ
ン層もしくはそれら双方と前記第１の高融点金属膜との
界面を混合する工程と、第２の高融点金属膜を堆積する
工程と、４００〜６００℃の温度範囲で熱処理全行うこ
と釦よシ前記イオン注入にょ９混合された界面において
高融点金属硅化物形成反応を生ぜしめる工程と、未反応
で残留する尚融点金属を選択的にエツチングすることに
より各々平滑かつ均一な高融点金属硅化物２層構造を前
記単結晶シリコン層あるいは多結晶シリコン層もしくは
それら双方の表面に自己整合的に形成する工程と、注入
されたドーパントを高温アニールによシ活性化し前記高
融点金属硅化物層下に自己整合的に不純物ドープ層を形
成する工程とを含むことを特徴とする半導体装置の製造
方法が得られる。(Structure of the Invention) According to the present invention, the step of depositing a first high melting point metal film on a substrate having a single crystal silicon layer, a polycrystal silicon layer, or both on at least a part of the surface;
The monocrystalline silicon layer, polycrystalline silicon layer, or The step of mixing the interface between both of them and the first high melting point metal film, the step of depositing the second high melting point metal film, and the heat treatment in a temperature range of 400 to 600°C are all performed. A smooth and uniform two-layer structure of high melting point metal silicide is created by a step of causing a reaction to form a high melting point metal silicide at the mixed interface of the injection molding, and selectively etching the unreacted remaining melting point metal. forming the dopant in a self-aligned manner on the surface of the single crystal silicon layer, the polycrystalline silicon layer, or both, and activating the implanted dopant by high-temperature annealing to form the dopant in a self-aligned manner under the refractory metal silicide layer. There is obtained a method for manufacturing a semiconductor device, which comprises the steps of: forming an impurity-doped layer.
（構成と効果の詳細な説明）
本発明による製造方法は本発明者等が見出した以下の如
き事実に基づくものである。第２図（ａ）の如く、シリ
コン単結晶基板２０１にゲート絶縁膜２０２、ゲート多
結晶シリコン２０３を形成したのち、第２図（ｂ）に示
す様にＴｉ等第１の尚融点金属薄膜２０４を被着し、こ
れを通して■族またはＶ族のドーパントイオン２０５を
注入するか、もしくは該ドーパントイオンとシリコン結
晶中で導電型を示さない非ドーパントイオン、例えばシ
リコンイオンとを重ねて注入することにより、ソース・
ドレイン領域の単結晶基板と高融点金属界面並びにゲー
ト多結晶シリコンと高融点金属界面に各々界面度範囲で
熱処理を実施すると、第２図（ｄ）の如く前記界面混合
層２０６に自己整合的に極めて平坦かつ平滑でピンホー
ルがない高品質な高融点金属硅化物２層構造２０８，２
０９が形成され得る。更にこの後、８００℃程度ある込
はそれ以上の高温で熱処理することＫよ如注入されたド
ーパントイオンを活性化し前記高融点金属硅化物２層構
造の直下に自己整合して浅す不純物ドープ層２１０を形
成し得る。(Detailed explanation of structure and effects) The manufacturing method according to the present invention is based on the following facts discovered by the present inventors. As shown in FIG. 2(a), after forming a gate insulating film 202 and gate polycrystalline silicon 203 on a silicon single crystal substrate 201, as shown in FIG. 2(b), a first melting point metal thin film 204 such as Ti is formed. or by implanting the dopant ions and non-dopant ions that do not exhibit a conductivity type in the silicon crystal, such as silicon ions, in a superimposed manner. ,sauce·
When the interface between the single crystal substrate and the high melting point metal in the drain region and the interface between the gate polycrystalline silicon and the high melting point metal are heat-treated within the interfacial degree range, the interfacial mixed layer 206 is self-aligned as shown in FIG. 2(d). Extremely flat and smooth high-quality high-melting point metal silicide two-layer structure 208, 2 with no pinholes
09 may be formed. Furthermore, after this, heat treatment is performed at a high temperature of about 800° C. (or higher in some cases) to activate the implanted dopant ions and form a self-aligned and shallow impurity doped layer just below the high melting point metal silicide two-layer structure. 210 may be formed.
一例として第１の高融点金属膜として厚さ２００ＡのＴ
ｉｉ、第２の高融点金属膜として厚さ１００ＸのＭｏを
用い、砒素をドーパントイオンとした場合には、接合深
さ０．１μｍのｎ型不純物ドープ層上に平坦かつ平滑な
Ｔ１硅化物、Ｍｏ硅化物の２層構造を形成し得た。この
時硅化物層のシート抵抗は４Ω／口であり、砒素イオン
注入のみによるｎ型不純物ドープ層のシート抵抗に比し
１桁以上低い値にできた。また上層のＭｏ硅化物はフッ
酸系のエツチング液に対して安定であシ、硅化物上に被
着される層間絶縁膜［＋Ｖ等冒次配線とのコンタクト大
を開口する際、フッ酸系の湿式１．チングが使用できた
。また、Ｍｏ硅化物層はＭ配緋との間で十分低抵抗なオ
ーミック！極を形成し得ること、また５５０℃程度のＭ
アロイ温度にも十分耐える耐熱性金示した。以上のよう
に単層の金属硅化物では満たし得ない特性を金属硅化物
２層構造によって満たし得る。As an example, T with a thickness of 200A is used as the first high melting point metal film.
ii. When Mo with a thickness of 100X is used as the second high melting point metal film and arsenic is used as a dopant ion, a flat and smooth T1 silicide is formed on the n-type impurity doped layer with a junction depth of 0.1 μm; A two-layer structure of Mo silicide could be formed. At this time, the sheet resistance of the silicide layer was 4 Ω/gate, which was more than an order of magnitude lower than the sheet resistance of the n-type impurity doped layer formed only by arsenic ion implantation. In addition, the upper layer Mo silicide is stable against hydrofluoric acid-based etching solutions, and when opening large contact holes with additional wiring such as +V in the interlayer insulating film deposited on the silicide, hydrofluoric acid-based etching solutions are used. Wet method 1. Ching could be used. In addition, the Mo silicide layer has a sufficiently low resistance between the M and the ohmic! It is possible to form a pole, and M at about 550°C
The heat-resistant gold showed sufficient resistance to alloying temperatures. As described above, the metal silicide two-layer structure can satisfy the characteristics that cannot be satisfied with a single layer of metal silicide.
本発明の方法で、尚融点金属硅化物形成反応は４００〜
６００℃の比較的低温で行なうが、この温度範囲は均質
、平滑な高融点金属硅化物全単結晶シリコンあるいは多
結晶シリコン表面のイオン注入による界面混合層に自己
整合的に形成するため極めて重要である。これはイオン
注入による界面混合層での金属硅化物形成反応の開始温
度が全くイオン注入しない場合の界面での反応の開始温
度に比べて低い事実から、この温度差全オリ用して自己
整合的に反応をさせること、また界面混合層では反応開
始進行が均一に進み易いことに依っているためである。In the method of the present invention, the melting point metal silicide forming reaction is
The process is carried out at a relatively low temperature of 600°C, and this temperature range is extremely important in order to form a homogeneous, smooth, high melting point metal silicide all-single-crystal silicon or polycrystalline silicon surface in a self-aligned interfacial mixed layer by ion implantation. be. This is due to the fact that the starting temperature of the metal silicide forming reaction in the interfacial mixed layer due to ion implantation is lower than the starting temperature of the reaction at the interface when no ions are implanted. This is because it depends on the fact that the reaction is caused to occur and that the reaction initiation progresses easily in the interfacial mixed layer.
これに対しイオン注入しない場合の界面ではシリコン表
面に存在する自然酸化膜等が金属硅化物形成反応開始温
度全上昇させる原因となりてお９、更にその膜厚の不均
一性が形成される金属硅化物の平滑性、均一性を損なう
原因となっている。従って、前記界面混合層の形成と、
低温での金属硅化物形成反応との組み合わせは得られる
金属硅化物の平滑性、均一性、自己整合形成など微細な
構造を持つ尚密度集積回路への応用のための必須条件の
達成に極めて重要である。On the other hand, at the interface when ions are not implanted, the natural oxide film existing on the silicon surface causes a total increase in the starting temperature of the metal silicide formation reaction. This causes damage to the smoothness and uniformity of objects. Therefore, the formation of the interfacial mixed layer;
The combination of metal silicide formation reactions at low temperatures is extremely important for achieving the smoothness, uniformity, and self-aligned formation of the resulting metal silicide, which are essential conditions for application to high-density integrated circuits with fine structures. It is.
本発明者らの行った実験によれば、界面混合層を形成し
た後、直接８００℃程度あるいはそれ以上の局温処理を
行うと、界面混合層の端部から硅化物が伸長してしまい
、軸度の良い自己整合形成が不可能であった。また、第
１の高融点金属薄膜堆積直後にイオン注入を行ない界面
混合層を形成しているが第２０篩融点金属薄膜を堆積後
にイオン注入し界面混合層を形成する場合に比べてイオ
ン注入時の加速電圧に余裕が大きくとれ、２層構造とし
てより厚い硅化物層を得られる利点がある。According to experiments conducted by the present inventors, if a local temperature treatment of about 800°C or higher is performed directly after forming an interfacial mixed layer, the silicide will extend from the edge of the interfacial mixed layer. It was impossible to form a self-aligned structure with good axiality. In addition, although ion implantation is performed immediately after the deposition of the first high melting point metal thin film to form an interfacial mixed layer, the ion implantation time is lower than when ions are implanted after depositing the 20th sieve melting point metal thin film to form an interfacial mixed layer. This has the advantage that there is a large margin in the accelerating voltage and that a thicker silicide layer can be obtained as a two-layer structure.
本発す９実施例では第１の高融点金属と第２の高融点金
属は別の材料であったが、同じ材料でありても構わない
のは勿薗である。ま７Ｃ夾実施では単結晶Ｓｉ基板金用
いたがＳＯ８基板やＳＯＸ基板を用いてもよい。In the present nine embodiments, the first high melting point metal and the second high melting point metal were made of different materials, but it goes without saying that they may be made of the same material. In the 7C implementation, a gold single-crystal Si substrate was used, but an SO8 substrate or a SOX substrate may also be used.
また前記実施例では単結晶Ｓｉ上、多結晶Ｓｉ上に共に
２層の高融点金属硅化物層を形成する場合について述べ
たが、これに限らず単結晶Ｓｉ上のみあるいは多結晶Ｓ
ｔ上のみに前記２層膜を形成してもよいことはいうまで
もない。Furthermore, in the above embodiments, two high melting point metal silicide layers are formed on both single crystal Si and polycrystalline Si, but the invention is not limited to this.
It goes without saying that the two-layer film may be formed only on t.
単結晶Ｓｉ上のみに形成する場合であれば、例えば、単
結晶８１基板やＳＯＳ基板上に５ｉ０２等の絶縁膜を形
成し、所望の場所全開孔してチタン等の尚融点金属膜を
形成しｆｃあとＡ８等全イオン注入して界面混合を行な
い、そのおとすぐモリブデン等の高融点金属膜を形成し
、あとは前記実施例と同様に行なえばよい。If it is to be formed only on single-crystal Si, for example, an insulating film such as 5i02 is formed on a single-crystal 81 substrate or an SOS substrate, holes are opened in all desired locations, and a low-melting point metal film such as titanium is formed. After fc, all ions such as A8 are implanted to perform interfacial mixing, and immediately after that, a film of a high melting point metal such as molybdenum is formed, and the rest is carried out in the same manner as in the previous embodiment.
多結晶Ｓ１上にのみ形成する場合であれば、例えば、単
結晶８１基根上に８１０！等の絶縁膜を形成し。If it is to be formed only on the polycrystal S1, for example, 810! is formed on the single crystal 81 root. Form an insulating film such as
その上にＣＶＤ法等で多結晶Ｓ１膜を形成し、この多結
晶５ｉＪｉｌｉ所望の形状にバターニングしたあと前記
実施例と同様に２層膜の形成を行なえばよい。A polycrystalline S1 film is formed thereon by CVD or the like, and this polycrystalline S1 film is patterned into a desired shape, and then a two-layer film is formed in the same manner as in the previous embodiment.
第１図は微細化されたＭＯＳＦＥＴのソース・ドレイン
となる非常に洩−不純物ドープ層並びに薄いゲート多結
晶シリコンの各々の表面を高融点金属硅化物２層で被覆
し低抵抗化し九半導体集積回路の構造を示す部分断面図
、第２図（ａ） 、 （ｂ） 、 （ｅ） 。
（ｄ）は第１図の構造を笑現するための本発明の実施例
を示す部分断面図である。
図において、各記号は以下のものを示す。
１０１．２０１・・・シリコン基板。
１０２．２０２・・・ゲート絶縁膜。
１０３．２０３・・・ゲート多結晶シリコン。
１０４．２１０・・・浅い不純物ドープ層。
１０５．２０８・・・第１の高融点金属硅化物層。
１０６．２０９・・・第２の高融点金属硅化物層。
２０４・・・第１の高融点金属薄膜。
２０５・・・ドーパントイオンもしくはドーパントイオ
ンと非ドーパントイオンの組み合わせ。
２０６・・・高融点金属とシリコンの界面混合層。
２０７・・・第２の高融点金属薄膜。
第１図
第２図
第２図Figure 1 shows a highly leaky impurity-doped layer that will become the source and drain of a miniaturized MOSFET, as well as the surfaces of the thin gate polycrystalline silicon, each coated with two layers of high-melting point metal silicide to reduce resistance. Partial cross-sectional views showing the structure of FIGS. 2(a), (b), and (e). (d) is a partial sectional view showing an embodiment of the present invention for embodying the structure of FIG. 1; In the figure, each symbol indicates the following. 101.201...Silicon substrate. 102.202...Gate insulating film. 103.203...Gate polycrystalline silicon. 104.210...Shallow impurity doped layer. 105.208...first high melting point metal silicide layer. 106.209...Second high melting point metal silicide layer. 204...First high melting point metal thin film. 205...Dopant ion or combination of dopant ion and non-dopant ion. 206...Interfacial mixed layer of high melting point metal and silicon. 207...Second high melting point metal thin film. Figure 1 Figure 2 Figure 2
Claims (1)
晶シリコン層もしくはそれら双方を備えた基板上に第１
の高融点金属膜を堆積する工程と、１．１Ｎ族またはＶ
族のドーパントイオンもしくは該ドーパントイオンとシ
リコン結晶中においてｐ型あるいはｎ型を示さない非ド
ーパントイオンとを重ねてイオン注入することによって
前記単結晶シリコン層あるいは多結晶シリコン層もしく
はそれら双方と前記第１の高融点金属膜との界面を混合
する工程と、第２の高融点金属膜を堆積する工程と、４
００〜６００℃の温度範囲で熱処理を行うことによシ前
記イオン注入によ）混合された界面において萬融点金属
硅化物形成反応會生ぜしめる工程と、未反応で残留する
高融点金属を選択的に工、テングすることにより各々平
滑かつ均一な高融点金属硅化物２層構造を前記単結晶シ
リコン層あるいは多結晶シリコン層もしくはそれら双方
の表面に自己整合的に形成する工程と、注入されたドー
パントを高温アニールによ）活性化し前記高融点金属硅
化物層下に自己整合的に不純物ドープ層を形成する工程
とを含むことｔ−特徴とする半導体装置の製造方法。A first layer is formed on a substrate having a single crystal silicon layer, a polycrystalline silicon layer, or both on at least a portion of the surface.
a step of depositing a high melting point metal film of 1.1N group or V
The monocrystalline silicon layer, the polycrystalline silicon layer, or both of them and the first a step of mixing the interface with the high melting point metal film; a step of depositing a second high melting point metal film;
A process of causing a reaction to form a melting point metal silicide at the mixed interface (by the ion implantation) by performing heat treatment in a temperature range of 00 to 600°C, and selectively removing the high melting point metal remaining unreacted. forming a smooth and uniform high-melting point metal silicide two-layer structure on the surface of the single crystal silicon layer or the polycrystalline silicon layer or both of them in a self-aligned manner by etching and polishing, and implanted dopant. (by high-temperature annealing) to form an impurity doped layer under the refractory metal silicide layer in a self-aligned manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4984484A JPS60193380A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4984484A JPS60193380A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60193380A true JPS60193380A (en) | 1985-10-01 |
Family
ID=12842375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4984484A Pending JPS60193380A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60193380A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240017A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01103873A (en) * | 1987-06-23 | 1989-04-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01257324A (en) * | 1988-04-07 | 1989-10-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0277122A (en) * | 1988-06-16 | 1990-03-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPH02194524A (en) * | 1988-12-24 | 1990-08-01 | Samsung Electron Co Ltd | Method of ferming low resistance connection at low resistance area of vlsi device |
| JPH03175626A (en) * | 1989-12-04 | 1991-07-30 | Nmb Semiconductor:Kk | Ic and its manufacture |
| JPH04354329A (en) * | 1991-05-31 | 1992-12-08 | Nec Corp | Production of semiconductor device |
| US6033978A (en) * | 1994-07-05 | 2000-03-07 | Nec Corporation | Process of selectively producing refractory metal silicide uniform in thickness regardless of conductivity type of silicon thereunder |
| KR100395776B1 (en) * | 2001-06-28 | 2003-08-21 | 동부전자 주식회사 | Method for manufacturing a silicide layer of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207372A (en) * | 1981-06-15 | 1982-12-20 | Nec Corp | Manufacture of metal oxide semiconductor integrated circuit device |
| JPS5863165A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device having multilayer electrode structure |
-
1984
- 1984-03-15 JP JP4984484A patent/JPS60193380A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207372A (en) * | 1981-06-15 | 1982-12-20 | Nec Corp | Manufacture of metal oxide semiconductor integrated circuit device |
| JPS5863165A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device having multilayer electrode structure |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240017A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01103873A (en) * | 1987-06-23 | 1989-04-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01257324A (en) * | 1988-04-07 | 1989-10-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0277122A (en) * | 1988-06-16 | 1990-03-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPH02194524A (en) * | 1988-12-24 | 1990-08-01 | Samsung Electron Co Ltd | Method of ferming low resistance connection at low resistance area of vlsi device |
| JPH03175626A (en) * | 1989-12-04 | 1991-07-30 | Nmb Semiconductor:Kk | Ic and its manufacture |
| JPH04354329A (en) * | 1991-05-31 | 1992-12-08 | Nec Corp | Production of semiconductor device |
| US6033978A (en) * | 1994-07-05 | 2000-03-07 | Nec Corporation | Process of selectively producing refractory metal silicide uniform in thickness regardless of conductivity type of silicon thereunder |
| KR100395776B1 (en) * | 2001-06-28 | 2003-08-21 | 동부전자 주식회사 | Method for manufacturing a silicide layer of semiconductor device |
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