JPH0237093B2 - HANDOTAISOCHINOSEIZOHOHO - Google Patents

HANDOTAISOCHINOSEIZOHOHO

Info

Publication number
JPH0237093B2
JPH0237093B2 JP908581A JP908581A JPH0237093B2 JP H0237093 B2 JPH0237093 B2 JP H0237093B2 JP 908581 A JP908581 A JP 908581A JP 908581 A JP908581 A JP 908581A JP H0237093 B2 JPH0237093 B2 JP H0237093B2
Authority
JP
Japan
Prior art keywords
silicon substrate
film
gate electrode
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP908581A
Other languages
Japanese (ja)
Other versions
JPS57124476A (en
Inventor
Sunao Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP908581A priority Critical patent/JPH0237093B2/en
Publication of JPS57124476A publication Critical patent/JPS57124476A/en
Priority to US06/645,536 priority patent/US4622735A/en
Priority to US06/832,647 priority patent/US4830971A/en
Publication of JPH0237093B2 publication Critical patent/JPH0237093B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Description

【発明の詳现な説明】 本発明は特に高速床・高集積密床を持぀MIS型
集積回路に甚いる半導䜓装眮の補造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a method of manufacturing a semiconductor device used in an MIS type integrated circuit having high speed and high integration density.

近幎集積回路の集積密床は幎々増加し、いわゆ
る超LSIが盛んに研究開発されおいる。集積密床
を増加させるには回路を構成する玠子の寞法を
益々小さくしお行く必芁がある。然るにMOSト
ランゞスタの寞法が小さくなり、特にチダネル長
が短くなるに぀れお、いわゆるシペヌトチダネル
効果が生じトランゞスタのスレシホヌルド電圧が
著るしく䜎䞋するこずが知られおいる。これは䞻
ずしおドレヌン電圧による空乏局がチダネル領域
に䟵入するこずにより、チダネル領域の電荷がゲ
ヌト電圧のみならず、ドレヌン電圧によ぀おも倧
きく圱響されおいるからである。このシペヌトチ
ダネル効果を防ぐ手段ずしおは、チダネル領域ぞ
むオン泚入するこずにより、この郚分の基板濃床
を䞊げ空乏局の䟵入をおさえる方法、ゲヌト酞化
膜厚を薄くしおゲヌト電極の電界の圱響をより倧
きくするなどの方法がある。又䞀方゜ヌス・ドレ
むンの拡散深さXjを浅くするず、やはりチ
ダネル領域ぞの空乏局の䟵入がおさえられシペヌ
トチダネル効果を防ぐこずが出来るが、Xjを浅
くするず通垞の工皋では拡散局による配線が゜ヌ
ス・ドレむンず同時に圢成される為及び又は比
䟋瞮小により配線領域の巟が狭たるため゜ヌス・
ドレむン及び拡散局による配線領域の局抵抗が高
くなり回路の動䜜速床が著しく枛少するずいう問
題がある。 In recent years, the integration density of integrated circuits has increased year by year, and so-called super LSIs have been actively researched and developed. Increasing the integration density requires smaller and smaller dimensions of the elements that make up the circuit. However, it is known that as the dimensions of a MOS transistor become smaller, especially as the channel length becomes shorter, a so-called short channel effect occurs and the threshold voltage of the transistor decreases significantly. This is mainly because a depletion layer caused by the drain voltage invades the channel region, so that the charge in the channel region is greatly influenced not only by the gate voltage but also by the drain voltage. As a means to prevent this short channel effect, there are two methods: implanting ions into the channel region to increase the substrate concentration in this area and suppressing the invasion of the depletion layer, and reducing the thickness of the gate oxide film to increase the influence of the electric field of the gate electrode. There are ways to do this. On the other hand, if the diffusion depth (Xj) of the source/drain is made shallow, the invasion of the depletion layer into the channel region can be suppressed and the short channel effect can be prevented. Because the source and drain are formed at the same time and/or because the width of the wiring area is narrowed due to proportional reduction, the source and drain
There is a problem in that the layer resistance of the wiring region due to the drain and diffusion layers increases and the operating speed of the circuit decreases significantly.

本発明者は、ゲヌト電極の少くずも偎壁を絶瞁
物で芆぀おおいお党面にPd等の金属膜を堆積さ
せ、加熱合金化しお゜ヌス・ドレむン偎郚に接続
する配線領域衚面にもマスク合わせするこずなく
ゲヌトず自己敎合した圢でメタルシリサむドを蚭
眮し、しかるのち残郚の金属膜を陀去するこずを
考えた。 The present inventor covers at least the side walls of the gate electrode with an insulator, deposits a metal film such as Pd on the entire surface, and heats and alloys it to match the mask on the surface of the wiring region connected to the side of the source/drain. The idea was to install the metal silicide in a self-aligned manner with the gate and then remove the remaining metal film.

しかし、基䜓衚面のnatural oxideがその䞊の
金属膜ずシリコンずの合金化を劚げシリサむドず
基板間のオヌミツクを充分にはずりにくい。埓぀
お、比䟋瞮小に察凊しおメタルシリサむド貌り付
けにより浅いXjず䜎抵抗局を図぀おもそれが充
分達成できない。又、合金化時には共晶枩床に䞊
げれば良い筈であるが、このnatural oxideによ
りそれ以䞊の枩床が必芁ずなるため、チダネルに
ドヌプした䞍玔物が再分垃したり、Xjが深くな
぀おしたう欠点がある。又、高融点金属、䟋えば
Moやでは、1000〜1100℃の高枩凊理をしない
ずシリサむドは圢成されないずいう欠点があ぀
た。このように加熱によるシリサむド圢成では浅
いXj、䜎抵抗局を図぀お比䟋瞮小MISに察凊す
るには問題があ぀た。 However, the natural oxide on the substrate surface prevents alloying of the metal film thereon with silicon, making it difficult to maintain sufficient ohmic contact between the silicide and the substrate. Therefore, even if a shallow Xj and a low resistance layer are attempted by pasting metal silicide in order to cope with the proportional reduction, this cannot be achieved satisfactorily. Also, during alloying, it should be possible to raise the temperature to the eutectic temperature, but since this natural oxide requires a higher temperature, there are disadvantages such as redistribution of impurities doped into the channel and deepening of Xj. be. Also, high melting point metals, e.g.
Mo and W have the disadvantage that silicide cannot be formed unless they are treated at a high temperature of 1000 to 1100°C. As described above, forming silicide by heating has a problem in achieving a shallow Xj and low resistance layer to cope with proportional reduction MIS.

本発明は以䞊の点に鑑みなされたものであり、
ゲヌト電極の少くずも偎壁を絶瞁物で芆぀おおい
お党面に金属膜を被着させ、この金属膜ずシリコ
ンずの界面郚に基䜓ず反察導電型の䞍玔物をむオ
ン泚入するこずにより゜ヌス・ドレむンず共にこ
の配線領域衚面にもマスク合わせするこずなくゲ
ヌトず自己敎合した圢でメタルシリサむドを圢成
するず同時に基䜓内に䞍玔物を導入し、しかるの
ち残郚の金属膜を陀去するようにしたものであ
る。これによりメタルシリサむドず基䜓ずのオヌ
ミツクが良奜になり、又、高枩にする必芁はなく
なるので比䟋瞮小MISの浅い䜎抵抗局が埗られる
ようになる。又、高融点金属を甚いおも䜎枩でシ
リサむド圢成できるので比䟋瞮小MSIの浅い䜎抵
抗局が同様に圢成できる。 The present invention has been made in view of the above points,
At least the side walls of the gate electrode are covered with an insulating material, a metal film is deposited on the entire surface, and an impurity of the opposite conductivity type to the base is ion-implanted into the interface between the metal film and silicon, so that the source and drain can be bonded together. Metal silicide is formed on the surface of this wiring region in a self-aligned manner with the gate without mask alignment, and at the same time impurities are introduced into the substrate, and then the remaining metal film is removed. This improves the ohmic contact between the metal silicide and the substrate, and eliminates the need for high temperatures, making it possible to obtain a shallow low-resistance layer for proportionally reduced MIS. Further, since silicide can be formed at a low temperature even if a high melting point metal is used, a shallow low resistance layer of proportional reduction MSI can be similarly formed.

以䞋、本発明の実斜䟋を図面を参照しながら詳
现に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第図は通垞の工皋により䟋えば型シリコ
ン基䜓䞊にゲヌト絶瞁膜ずゲヌト電極甚
のポリSiを圢成した状態を瀺しおいる。
はフむヌルド酞化膜である。 FIG. 1a shows a state in which a gate insulating film 12 and a poly-Si film 13 for a gate electrode are formed on, for example, a P-type silicon substrate 11 by a normal process. 14
is the field oxide film.

次いでり゚ハヌ党面に䟋えばSiO2を気盞
成長法により玄2000Å成長させる第図。 Next, SiO 2 15, for example, is grown to a thickness of about 2000 Å over the entire surface of the wafer by vapor phase growth (FIG. 1b).

次に、リアクテむブ・むオン゚ツチング法ス
パツタリング・゚ツチング法でも良いによりり
゚ハヌ党面のSiO2を゚ツチングするず、ポリSi
ゲヌトの端郚にのみSiO2を残眮し、゜
ヌス・ドレむンずなる領域のシリコン衚面及
びポリシリコンの衚面を露出させる第図
。 Next, when the SiO 2 on the entire surface of the wafer is etched using a reactive ion etching method (a sputtering etching method may also be used), polySi is etched.
SiO 2 15 is left only at the end of the gate 13, and the silicon surface 16 and the surface of the polysilicon 13 in the regions that will become the source and drain are exposed (FIG. 1c).

次に、り゚ハヌ党面にたずえばタングステ
ンを玄400Å真空蒞着する第図。 Next, for example, W (tungsten) 17 is vacuum-deposited to a thickness of about 400 Å over the entire surface of the wafer (FIG. 1d).

次いでり゚ハヌ党面にAsむオンを䟋えば加速
電圧300KeV、ドヌズ量×1016cm- 2で界面にむ
オン泚入するず膜がSiず反応しお゜ヌス・ドレ
むン䞊及びポリSiゲヌト䞊にタングステンシリサ
むドWSi2′″が玄1200Å圢
成される。同時にシリサむド䞋の基板Si内には
PN接合が圢成される第図。次いでゲヌ
ト端郚に蚭けられたSiO2をずり陀いお、再
びAsを䟋えば40KeVの加速電圧で×1014cm-2
むオン泚入しお浅いPN接合を圢成する。次
に未反応の膜を゚ツチング陀去すれば第図
の劂くシリサむドがゲヌトポリSi及び゜ヌス・ド
レむン郚に互に自己敎合しお圢成された構造が埗
られる第図。 Next, when As ions are implanted into the interface on the entire surface of the wafer at an acceleration voltage of 300 KeV and a dose of 2 x 10 16 cm - 2 , the W film reacts with Si, forming tungsten silicide (WSi 2 ) on the source/drain and poly-Si gate. )18, 18', 18'' are formed with a thickness of about 1200 Å.At the same time, in the substrate Si under the silicide,
A PN junction is formed (Fig. 1e). Next, the SiO 2 15 provided at the edge of the gate is removed, and As is applied again to 1×10 14 cm -2 at an accelerating voltage of 40 KeV, for example.
A shallow PN junction 20 is formed by ion implantation. Next, if the unreacted W film is removed by etching, it is shown in Figure 2 f.
A structure is obtained in which silicide is formed in self-alignment with the gate polysilicon and the source/drain regions (FIG. 1f).

以䞋は通垞のMOS・LSIの補造工皋によりLSI
チツプが完成される。即ち、党面に絶瞁膜
CVDSiO2が蚭眮され、゜ヌス、ゲヌト、
ドレむン郚にコンタクトホヌルが開口され、
最埌にAlの配線及びPSGの保護膜が圢
成される。 The following is an LSI manufactured by the normal MOS/LSI manufacturing process.
The chip is completed. That is, an insulating film (CVDSiO 2 ) 21 is installed on the entire surface, and the source, gate,
A contact hole 22 is opened in the drain part,
Finally, an Al wiring 23 and a PSG protective film 24 are formed.

ここで、第図は第図に倫々察
応した䞊面図でドレむンから延びる拡散配線局
゜ヌス・ドレむンず同じ工皋で圢成が瀺され
おいる。このトランゞスタは䟋えばスむツチング
Trずしお甚いられ、ゲヌトに䟋えば5Vを印加し
おおいおむンバヌタ図瀺せずから䟋えば5V
の電圧が゜ヌスに入力されるず、ドレむンには
5V−VTHしきい倀が出力され、拡散配線局を
通しお他のトランゞスタのゲヌトに入力される。
第図に瀺した゜ヌス及びドレむンは他の
入力及び出力端子である。 Here, FIGS. 2a and 2b are top views corresponding to FIGS. 1a and 1f, respectively, and show a diffusion wiring layer (formed in the same process as the source and drain) extending from the drain. This transistor can be used for example in switching
It is used as a transistor, and when 5V is applied to the gate, 5V is applied from an inverter (not shown).
When a voltage of is input to the source, the drain has
5V-V TH (threshold) is output and input to the gates of other transistors through the diffusion wiring layer.
The source and drain 23 shown in FIG. 1G are other input and output terminals.

以䞊の方法により䜜られたMOSトランゞスタ
は、゜ヌス、ドレむン郚及びゲヌト郚に玄1500Å
のタングステンシリサむドが圢成されおいる為゜
ヌス、ドレむン拡散配線郚及びゲヌト郚は〜
Ω口ずいう極めお䜎い抵抗が埗られ、シリサむ
ドを甚いない埓来の方法で䜜぀た拡散局ρs50
Ω口に比べ、ドレむン又は゜ヌスから延
圚する拡散局配線に斌ける、信号の遅延時間は著
しく枛少するこずが出来た。ドレむン又は゜ヌ
スず拡散局配線の局抵抗は共に遅延に利くが䞀
般に配線領域の長さがこれに接続する゜ヌスやド
レむンの寞法により長く、埓぀お゜ヌスやドレむ
ンより抵抗が高いので配線領域衚面にメタルシリ
サむドを圢成する効果は倧きい。配線領域はドレ
むン、゜ヌス䞡方に蚭けおも構わない。 The MOS transistor made by the above method has a thickness of about 1500 Å in the source, drain and gate parts.
Since tungsten silicide is formed, the source and drain diffusion wiring areas and the gate area are
An extremely low resistance of Ω/mouth was obtained, and the diffusion layer (ρs50
The signal delay time in the diffusion layer wiring extending from the drain (or source) can be significantly reduced compared to Ω/gate). Both the layer resistance of the drain (or source) and the diffusion layer wiring are useful for delay, but in general, the length of the wiring region is longer than the dimensions of the source or drain connected to it, and therefore the resistance is higher than that of the source or drain. The effect of forming metal silicide is great. The wiring region may be provided in both the drain and the source.

又、メタルシリサむドを付けるためにマスク工
皋を䞀回増やすずマスク合わせ䜙裕を取るために
その分集積床が䜎䞋するが本発明によれば、ゲヌ
ト電極に察しおメタルシリサむドを自己敎合しお
圢成しおいるので高集積密床化に奜適である
0.7〜1Ό有利。又、折角䜎抵抗局化にしたにも
かかわらずマスク合わせずれによりシリヌズ抵抗
が倉わりトランゞスタ特性の制埡が困難になるこ
ずもない。 Furthermore, if the masking process is increased by one step to attach metal silicide, the degree of integration will decrease due to mask alignment allowance, but according to the present invention, metal silicide is formed by self-aligning with the gate electrode. Therefore, it is suitable for high integration density (0.7 to 1 ÎŒ advantageous). In addition, even though the layer has a low resistance, the series resistance does not change due to misalignment of the mask, making it difficult to control the transistor characteristics.

本発明では゜ヌス、ドレむン及びゲヌト郚にシ
リサむドを圢成するのにタングステンずシリコン
の界面郚にAsをむオン泚入しお圢成しおいる。
埓぀おタングステン膜の蒞着前にシリコン衚面に
残存しおいるごく薄い酞化膜の圱響でシリサむド
の圢成が䞍均䞀にな぀たり、又シリサむド−シリ
コンの接觊抵抗が高くなるなどの問題が生じな
い。加えお、WSi2を圢成するのに1000℃〜1100
℃ずいう高枩工皋を入れる必芁がない。 In the present invention, silicide is formed in the source, drain, and gate portions by ion-implanting As into the interface between tungsten and silicon.
Therefore, problems such as non-uniform formation of silicide due to the influence of a very thin oxide film remaining on the silicon surface before the tungsten film is deposited, and high contact resistance between silicide and silicon do not occur. In addition, 1000℃~1100℃ to form WSi 2
There is no need for a high temperature process of ℃.

ここでは、ゲヌト近傍に浅い䜎濃床の型䞍玔
物の局によるPN接合を圢成しおいる為、シペヌ
トチダネル効果も小さく、又、ゲヌトず゜ヌス、
ドレむンずの容量結合も小さく、玠子の高速動䜜
に察しお極めお有利な構造をも぀おいる。この
局は、予めSiO2を薄く圢成しおおけば、第
図のようにむオン泚入しお特別に圢成しなく
おもその埌の熱工皋で生じる暪方向ぞの拡散によ
぀お必然的に圢成されおしたう。 Here, a PN junction is formed by a shallow, low concentration N-type impurity layer near the gate, so the short channel effect is small, and the gate and source
Capacitive coupling with the drain is also small, and the structure is extremely advantageous for high-speed operation of the device. This N
If a thin layer of SiO 2 15 is formed in advance, the layer will naturally be formed by lateral diffusion that occurs during the subsequent thermal process, even if it is not specially formed by ion implantation as shown in Figure 1 f. It will be formed.

以䞊の実斜䟋では、金属膜ずしおの堎合を䟋
ずしお述べたがこの他Mo、Ir、Ta、Nb、Pd、
Pt、Ni他いかなる金属でも、基板の半導䜓材料
ず安定な化合物を圢成するものなら䜕でもよい。
Pdを甚いるずPd2SiよりPdSiが倚量に圢成される
ので加熱法により圢成したものに比べ2/3〜1/2の
䜎い䜎抵抗になり有利である。 In the above embodiments, W was used as an example of the metal film, but other materials such as Mo, Ir, Ta, Nb, Pd,
Any metal such as Pt or Ni may be used as long as it forms a stable compound with the semiconductor material of the substrate.
When Pd is used, a larger amount of PdSi is formed than that of Pd 2 Si, so the resistance is 2/3 to 1/2 lower than that formed by heating, which is advantageous.

又、以䞊の実斜䟋では400Åのを党郚1500Å
のWSi2にかえる為、×1016cm-2ずいう高濃床の
むオン泚入を行぀たが、これは䟋えば×1015cm
-2ずいう䜎いドヌズ量でもよい。この堎合はSi−
の界面に玄200〜300ÅのWSi2が圢成される䞈
であるが䟋えばこの埌800℃のN2䞭で玄時間熱
凊理するず残りのもすべおWSi2にかえるこず
が出来る。埓来法の様に1000〜1100℃ずいう高枩
工皋を必芁ずしないのはAsのむオン泚入によ぀
お−Si界面に存圚しおいた薄い酞化膜が砎壊さ
れWSi2が圢成されたため、ずWSi2の界面には
䜕ら酞化物などの䞡者の反応を劚げるものがない
からである。埓぀お、浅いXjをも぀た䜎抵抗局
が圢成できる。又800℃の熱アニヌルの替りに
CWレヌザヌ又は電子ビヌムによるアニヌルを甚
いおもよい。 In addition, in the above example, all of the 400 Å W is 1500 Å
In order to change to WSi 2 of
A dose as low as -2 may be used. In this case, Si−
The length is such that about 200 to 300 Å of WSi 2 is formed at the W interface, but if the film is then heat treated in N 2 at 800° C. for about 1 hour, all the remaining W can be converted to WSi 2 . The reason why a high temperature process of 1000 to 1100°C is not required as in the conventional method is because the thin oxide film existing at the W-Si interface is destroyed by the As ion implantation and WSi 2 is formed. This is because there is nothing at the interface between the two , such as oxides, that would hinder the reaction between the two. Therefore, a low resistance layer with a shallow Xj can be formed. Also, instead of thermal annealing at 800℃
Annealing with a CW laser or electron beam may also be used.

又、䞊蚘の実斜䟋は基板ずしお型シリコンの
堎合のみを述べたが型シリコンでもよい。 Further, in the above embodiments, only P-type silicon was used as the substrate, but N-type silicon may also be used.

又、むオン泚入する䞍玔物ずしおAsの堎合の
みを述べたがその他、、Gaなどいかなるむ
オンであ぀おも基板ず反察導䌝型ずいう条件を満
たしおおけば同様に䜿える事は明らかである。 Moreover, although only the case of As is described as the impurity to be ion-implanted, it is clear that any other ions such as B, P, Ga, etc. can be similarly used as long as they satisfy the condition that they are of the opposite conductivity type to the substrate.

又、しきい倀制埡のため、゜ヌス、ドレむンよ
り浅いチダネルドヌプ局を圢成しおもよい。又、
リアクテむブむオン゚ツチング法のかわりに、ゲ
ヌト電極材料に型䞍玔物を䟋えば×1020cm-3
以䞊添加した倚結晶シリコンを甚い、䟋えば950
℃以䞋のり゚ツト雰囲気䞭で酞化し、基板䞊の薄
い酞化膜のみ陀去するこずによりゲヌトを陀いお
メタルシリサむドを圢成するこずもできる。又、
自己敎合しお蚭眮する膜もシリコン酞化膜あるい
はシリコン窒化膜膜あるいは䞡者からなる膜を堆
積しお圢成しおもよい。 Further, in order to control the threshold value, a channel doped layer may be formed that is shallower than the source and drain. or,
Instead of reactive ion etching, N-type impurities are added to the gate electrode material, for example, at 1×10 20 cm -3
For example, 950
Metal silicide can also be formed by oxidizing in a wet atmosphere at temperatures below .degree. C. and removing only the thin oxide film on the substrate, excluding the gate. or,
The self-aligned film may also be formed by depositing a silicon oxide film, a silicon nitride film, or a film made of both.

又、以䞊の説明ではポリSiのゲヌトの堎合に぀
いおのみ述べたがポリSi以倖のゲヌト材料、䟋え
ばスパツタリングで圢成したMoSi2やWSi2やあ
るいはMoやのリフラクトリメタルでもよいこ
ずは明らかである。 Furthermore, in the above explanation, only the case of a poly-Si gate has been described, but it is clear that gate materials other than poly-Si, such as MoSi 2 or WSi 2 formed by sputtering, or refractory metal such as Mo or W, may also be used. .

【図面の簡単な説明】[Brief explanation of drawings]

第図〜は本発明の䞀実斜䟋を瀺す図、第
図はその䞊面図である。図に斌お、   シリコン基䜓、  ポリシリコ
ン、ゲヌト、  CVD、SiO2膜、  
膜、  シリサむド、


N-局。 1A to 1G are views showing one embodiment of the present invention, and FIG. 2 is a top view thereof. In the figure, 11... silicon substrate, 13... polysilicon, gate, 15... CVD, SiO 2 film, 17...
W film, 18, 18, 18... W silicide, 20
...N - layer.

Claims (1)

【特蚱請求の範囲】  シリコン基䜓の䞀䞻面䞊にゲヌト絶瞁膜及び
ゲヌト電極を圢成する工皋ず、該ゲヌト電極の偎
壁郚に絶瞁物をこのゲヌト電極ず自己敎合させお
蚭眮する工皋ず、金属膜を党面に被着する工皋
ず、該金属膜ず前蚘シリコン基䜓の界面郚に前蚘
シリコン基䜓ず反察導電型の䞍玔物をむオン泚入
するこずによりメタルシリサむドを圢成するず同
時に前蚘シリコン基䜓内に䞍玔物を導入する工皋
ず、反応せずに残぀た前蚘金属膜を゚ツチング陀
去するこずにより、メタルシリサむド局を残眮す
る工皋ずからなるこずを特城ずする半導䜓装眮の
補造方法。  䞍玔物のむオン泚入埌、未反応の金属膜を゚
ツチング陀去する前にアニヌルするこずにより、
前蚘メタルシリサむドの膜厚を増加せしめる工皋
を含むこずを特城ずする前蚘特蚱請求の範囲第
項蚘茉の半導䜓装眮の補造方法。  アニヌルの方法ずしお炉に斌る熱アニヌルを
甚いるこずを特城ずする前蚘特蚱請求の範囲第
項蚘茉の半導䜓装眮の補造方法。  アニヌルの方法ずしおCWレヌザヌビヌムあ
るいはCW電子ビヌムを甚いるこずを特城ずする
前蚘特蚱請求の範囲第項蚘茉の半導䜓装眮の補
造方法。  ゲヌト電極の偎壁郚に絶瞁物を自己敎合させ
お蚭眮する方法ずしお気盞成長法によりシリコン
酞化膜、あるいは窒化膜、あるいは䞡者からなる
膜を堆積する工皋ず、リアクテむブむオン゚ツチ
ングあるいは、スパツタリング゚ツチングを行な
うこずを特城ずする前蚘特蚱請求の範囲第項蚘
茉の半導䜓装眮の補造方法。  ゲヌト電極偎壁郚に絶瞁物を自己敎合させお
蚭眮する工皋ずしお、ゲヌト電極材料に型䞍玔
物を×1020cm-3以䞊添加した倚結晶シリコンを
甚い950℃以䞋のり゚ツト雰囲気䞭に斌る酞化ず
この酞化によ぀お圢成された前蚘シリコン基䜓䞊
の酞化膜を陀去するこずを特城ずする前蚘特蚱請
求の範囲第項蚘茉の半導䜓装眮の補造方法。  反応せずに残぀た金属膜を゚ツチング陀去し
た埌、ゲヌト電極の偎壁郚の絶瞁物を陀去し、再
び前蚘シリコン基䜓ず反察導電型のむオンを前蚘
シリコン基䜓の少なくずも前蚘絶瞁物によ぀お芆
われおいた郚分にむオン泚入するこずを特城ずす
る前蚘特蚱請求の範囲第項蚘茉の半導䜓装眮の
補造方法。[Scope of Claims] 1. A step of forming a gate insulating film and a gate electrode on one main surface of a silicon substrate, and a step of installing an insulator on a side wall of the gate electrode in self-alignment with the gate electrode. A metal silicide is formed by depositing a metal film on the entire surface, and ion implantation of an impurity having a conductivity type opposite to that of the silicon substrate is performed at the interface between the metal film and the silicon substrate, and at the same time, impurities are introduced into the silicon substrate. 1. A method for manufacturing a semiconductor device, comprising a step of introducing a metal silicide layer, and a step of etching away the metal film remaining without reacting to leave a metal silicide layer. 2 After implanting impurity ions, annealing is performed before etching away the unreacted metal film.
Claim 1, characterized in that it includes a step of increasing the film thickness of the metal silicide.
A method for manufacturing a semiconductor device according to section 1. 3. Claim 2, characterized in that thermal annealing in a furnace is used as the annealing method.
A method for manufacturing a semiconductor device according to section 1. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a CW laser beam or a CW electron beam is used as the annealing method. 5. As a method for installing an insulator in a self-aligned manner on the side walls of the gate electrode, there is a process of depositing a silicon oxide film, a nitride film, or a film consisting of both by vapor phase growth, and reactive ion etching or sputtering. A method of manufacturing a semiconductor device according to claim 1, characterized in that ring etching is performed. 6. As a process of installing an insulator on the side walls of the gate electrode in a self-aligned manner, polycrystalline silicon doped with N-type impurities of 1×10 20 cm -3 or more is used as the gate electrode material, and the insulator is placed in a wet atmosphere at a temperature of 950°C or less. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising oxidizing the silicon substrate and removing an oxide film formed by the oxidation on the silicon substrate. 7 After etching away the metal film remaining without reaction, removing the insulating material on the side wall of the gate electrode, and again covering ions of the opposite conductivity type to the silicon substrate with at least the insulating material of the silicon substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein ions are implanted into a portion where the ion is removed.
JP908581A 1980-12-12 1981-01-26 HANDOTAISOCHINOSEIZOHOHO Expired - Lifetime JPH0237093B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP908581A JPH0237093B2 (en) 1981-01-26 1981-01-26 HANDOTAISOCHINOSEIZOHOHO
US06/645,536 US4622735A (en) 1980-12-12 1984-08-29 Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US06/832,647 US4830971A (en) 1980-12-12 1986-02-25 Method for manufacturing a semiconductor device utilizing self-aligned contact regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP908581A JPH0237093B2 (en) 1981-01-26 1981-01-26 HANDOTAISOCHINOSEIZOHOHO

Publications (2)

Publication Number Publication Date
JPS57124476A JPS57124476A (en) 1982-08-03
JPH0237093B2 true JPH0237093B2 (en) 1990-08-22

Family

ID=11710773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP908581A Expired - Lifetime JPH0237093B2 (en) 1980-12-12 1981-01-26 HANDOTAISOCHINOSEIZOHOHO

Country Status (1)

Country Link
JP (1) JPH0237093B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161372A (en) * 1982-02-10 1983-09-24 Nec Corp Manufacture of mos integrated circuit
JPS5999774A (en) * 1982-11-29 1984-06-08 Fujitsu Ltd Manufacture of semiconductor device
JPH0644572B2 (en) * 1983-03-23 1994-06-08 株匏䌚瀟東芝 Method for manufacturing semiconductor device
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
JPS6037770A (en) * 1983-08-10 1985-02-27 Seiko Epson Corp Semiconductor device
JPS61129873A (en) * 1984-11-28 1986-06-17 Seiko Epson Corp Equipment for manufacturing semiconductor
CA1235824A (en) * 1985-06-28 1988-04-26 Vu Q. Ho Vlsi mosfet circuits using refractory metal and/or refractory metal silicide
JPS62162362A (en) * 1986-01-10 1987-07-18 Mitsubishi Electric Corp Mos integrated circuit and manufacture thereof
JPS641283A (en) * 1987-06-23 1989-01-05 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH01298768A (en) * 1988-05-27 1989-12-01 Sony Corp Manufacture of mis transistor

Also Published As

Publication number Publication date
JPS57124476A (en) 1982-08-03

Similar Documents

Publication Publication Date Title
JP2806477B2 (en) Method of manufacturing shallow silicide junction
US4830971A (en) Method for manufacturing a semiconductor device utilizing self-aligned contact regions
JP2605008B2 (en) Method for manufacturing semiconductor device
US6248637B1 (en) Process for manufacturing MOS Transistors having elevated source and drain regions
US5097300A (en) Semiconductor device and manufacturing method thereof
JP2692617B2 (en) Method for manufacturing semiconductor device
US6218276B1 (en) Silicide encapsulation of polysilicon gate and interconnect
JPH0237093B2 (en) HANDOTAISOCHINOSEIZOHOHO
JPH09129752A (en) Preparation of cmos integrated circuit
US6081007A (en) Semiconductor device comprising MIS transistor with high concentration channel injection region
JP2675713B2 (en) Semiconductor device and manufacturing method thereof
US7109116B1 (en) Method for reducing dendrite formation in nickel silicon salicide processes
JPH08213610A (en) Field effect transistor and its manufacturing method
JP3391181B2 (en) Semiconductor device and manufacturing method thereof
JP3190858B2 (en) Semiconductor device and method of manufacturing the same
JP3496723B2 (en) Method for manufacturing semiconductor device
JP3129867B2 (en) Method for manufacturing semiconductor device
JPS6226573B2 (en)
EP0851486A1 (en) A process for manufacturing a semiconductor device
US6500740B1 (en) Process for fabricating semiconductor devices in which the distribution of dopants is controlled
JPH09162392A (en) Semiconductor device
KR100401500B1 (en) Method of fabricating semiconductor devices
JPH09213655A (en) Semiconductor device and manufacture thereof
KR100266017B1 (en) Method for fabricating semiconductor device
JP3380069B2 (en) Method for manufacturing MOS semiconductor device