JPS60192531U - Power element drive circuit - Google Patents
Power element drive circuitInfo
- Publication number
- JPS60192531U JPS60192531U JP8078184U JP8078184U JPS60192531U JP S60192531 U JPS60192531 U JP S60192531U JP 8078184 U JP8078184 U JP 8078184U JP 8078184 U JP8078184 U JP 8078184U JP S60192531 U JPS60192531 U JP S60192531U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- enhancement type
- channel enhancement
- mo3fet
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の駆動回路を示す図で、第２図は他の従来
の駆動回路を示す図、第３図はこの考案の駆動回路の一
実施例を示す図、第４図は各部動作波形の例を示す図で
ある。
図中、１は電力用ＭＯ３ＦＥＴ、２は負荷、３は負荷側
電源、４は抵抗器、５は駆動用電源、６はＣＭＯＳバッ
ファ回路、１１はＭＯＳ ＦＥＴ、１２はｐｎｐトラ
ンジスタである。なお、図中の同一符号は同一または相
当部分を示す。Fig. 1 is a diagram showing a conventional drive circuit, Fig. 2 is a diagram showing another conventional drive circuit, Fig. 3 is a diagram showing an embodiment of the drive circuit of this invention, and Fig. 4 is a diagram showing the operation of each part. It is a figure which shows the example of a waveform. In the figure, 1 is a power MO3FET, 2 is a load, 3 is a load side power supply, 4 is a resistor, 5 is a driving power supply, 6 is a CMOS buffer circuit, 11 is a MOS FET, and 12 is a pnp transistor. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
形ＭＯ３ＦＥＴのゲート、ソース端子に、エミッタ、コ
レクタ端子がそれぞれ接続されたｐｎｐ ｌ’ランジス
タと、前記第１のｎチャネルエンハンスメント形ＭＯ３
ＦＥＴのゲート端子にソース端子が接続され、前記ｐｎ
ｐ Ｉ’ランジスタのベース端子にゲート端子が接続さ
れた第２のｎチャネルエンハンスメント形ＭＯ３ＦＥＴ
と、正極端子が前記第２のｎチャネルエンハンスメント
形ＭＯ３ＦＥＴのドレイン端子に接続され、負極端子が
前記第１のｎチャネルエンハンスメント形ＭＯ３ＦＥＴ
のソース端子に接続された駆動用電源と、電源端子が前
記駆動用電源の正、負極端子にそれぞれ接続され、出力
端子が前記第２のｎチャネルエンハンスメント形ＭＯ３
ＦＥＴのゲート端子に接続されたＣＭＯＳバッファ回路
とから構成杢れたことを特徴とする電力用素子の駆動回
路。a pnp l' transistor whose emitter and collector terminals are respectively connected to the gate and source terminals of a first n-channel enhancement type MO3FET that controls load power; and the first n-channel enhancement type MO3
The source terminal is connected to the gate terminal of the FET, and the pn
p A second n-channel enhancement type MO3FET whose gate terminal is connected to the base terminal of the transistor
, the positive terminal is connected to the drain terminal of the second n-channel enhancement type MO3FET, and the negative terminal is connected to the drain terminal of the first n-channel enhancement type MO3FET.
a driving power source connected to the source terminal of the driving power source, a power source terminal connected to the positive and negative terminals of the driving power source, and an output terminal of the second n-channel enhancement type MO3.
1. A power element drive circuit comprising a CMOS buffer circuit connected to a gate terminal of an FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8078184U JPS60192531U (en) | 1984-05-29 | 1984-05-29 | Power element drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8078184U JPS60192531U (en) | 1984-05-29 | 1984-05-29 | Power element drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60192531U true JPS60192531U (en) | 1985-12-20 |
Family
ID=30626954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8078184U Pending JPS60192531U (en) | 1984-05-29 | 1984-05-29 | Power element drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192531U (en) |
-
1984
- 1984-05-29 JP JP8078184U patent/JPS60192531U/en active Pending
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