JPS5996914U - amplifier circuit - Google Patents

amplifier circuit

Info

Publication number
JPS5996914U
JPS5996914U JP19379882U JP19379882U JPS5996914U JP S5996914 U JPS5996914 U JP S5996914U JP 19379882 U JP19379882 U JP 19379882U JP 19379882 U JP19379882 U JP 19379882U JP S5996914 U JPS5996914 U JP S5996914U
Authority
JP
Japan
Prior art keywords
transistor
amplifier circuit
fet
collector
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19379882U
Other languages
Japanese (ja)
Other versions
JPS635290Y2 (en
Inventor
真彦 宮下
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP19379882U priority Critical patent/JPS5996914U/en
Publication of JPS5996914U publication Critical patent/JPS5996914U/en
Application granted granted Critical
Publication of JPS635290Y2 publication Critical patent/JPS635290Y2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の増幅回路を示す図、第２図および第３図
は、従来の増幅回路の等価回路を示す図、第４図は本考
案の一実施例を示す図、第５図お占び第６図は、本考案
の増幅回路の等価回路を示す図、第７図は本考案の構成
を用いて増幅器を構成した一実施例を示す図、第８図お
よび第９図は、本考案の他の実施例を示す図である。Figure 1 shows a conventional amplifier circuit, Figures 2 and 3 show equivalent circuits of the conventional amplifier circuit, Figure 4 shows an embodiment of the present invention, and Figures 5 and 3 show equivalent circuits of the conventional amplifier circuit. Figure 6 is a diagram showing an equivalent circuit of the amplifier circuit of the present invention, Figure 7 is a diagram showing an embodiment of an amplifier configured using the configuration of the present invention, and Figures 8 and 9 are: It is a figure which shows the other Example of this invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＦＥＴのソースと第１のトランジスタのコレクタとを接
続し、前記ＦＥＴのドレインと前記第１のトランジスタ
のベースと第２のトランジスタのベースとを接続し、前
記第２のトランジスタのコレクタと前記ＦＥＴのドレイ
ンとを接続し、前記第１のトランジスタのエミッタと第
２のトランジスタのエミッタをそれぞれ第１の抵抗、第
２の抵抗を介して接続することを特徴とする増幅回路。The source of the FET and the collector of the first transistor are connected, the drain of the FET and the base of the first transistor and the base of the second transistor are connected, and the collector of the second transistor and the collector of the FET are connected. An amplifier circuit characterized in that the emitter of the first transistor and the emitter of the second transistor are connected via a first resistor and a second resistor, respectively.
JP19379882U 1982-12-21 1982-12-21 amplifier circuit Granted JPS5996914U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19379882U JPS5996914U (en) 1982-12-21 1982-12-21 amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19379882U JPS5996914U (en) 1982-12-21 1982-12-21 amplifier circuit

Publications (2)

Publication Number Publication Date
JPS5996914U true JPS5996914U (en) 1984-06-30
JPS635290Y2 JPS635290Y2 (en) 1988-02-13

Family

ID=30416730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19379882U Granted JPS5996914U (en) 1982-12-21 1982-12-21 amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5996914U (en)

Also Published As

Publication number Publication date
JPS635290Y2 (en) 1988-02-13

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