JPS60175444A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60175444A
JPS60175444A JP59030216A JP3021684A JPS60175444A JP S60175444 A JPS60175444 A JP S60175444A JP 59030216 A JP59030216 A JP 59030216A JP 3021684 A JP3021684 A JP 3021684A JP S60175444 A JPS60175444 A JP S60175444A
Authority
JP
Japan
Prior art keywords
gallium arsenide
semiconductor
silicon
substrate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59030216A
Other languages
Japanese (ja)
Inventor
Satoshi Minojima
美濃島　智
Kazuya Hashimoto
和也 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59030216A priority Critical patent/JPS60175444A/en
Publication of JPS60175444A publication Critical patent/JPS60175444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To integrate a low noise amplifier circuit by connecting a small scale gallium arsenide semiconductor and a large scale silicon semiconductor via thermal melting through low melting point conductive material. CONSTITUTION:In a semiconductor device, a gallium arsenide substrate 2 in which a connecting lead terminal 7 on the substrate 2 and a connecting lead terminal 8 on a silicon substrate 1 are deposited with solder ball 3 is connected with the terminals 7, 8 by thermally melted solder by passing the thermal step of approx. 300 deg.C by superposing the substrates 2, 1 oppositely at upper and lower sides. When low noise gallium arsenide transistor is used for an input transistor 6, the same circuit noise amount as the case that all are formed of gallium arsenide semiconductors even if the circuit except it is composed of silicon semiconductor.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係り、高集積低雑音増幅回路に好
適な半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a highly integrated low-noise amplifier circuit.

に発明の背景〕 一般に、低雑音増幅回路はその目的からできるだけ信号
源に近づけるために、例えば磁気ディスク装置の磁気ヘ
ッドを塔載している可能ヘッドバー上に実装されており
、スペース、重さ。BACKGROUND OF THE INVENTION In general, low-noise amplification circuits are mounted on a head bar on which the magnetic head of a magnetic disk drive is mounted, for example, in order to be as close to the signal source as possible for the purpose of low-noise amplification circuits, which saves space and weight. .

高さ制限などがあり、高集積化が要求されている０ 又低雑音増幅回路を実現する場合その結晶構造の違いに
よりガリウムヒ素半導体の方がシリコン半導体よりもト
ランジスタ自身が発生する雑音が小さく、ガリウムヒ素
半導体を使用した方が有利である。しかし従来技術では
、ガリウムヒ素半導体は均一な結晶を使るのが難しく、
高集積化には向いていない。There are height restrictions and high integration is required.0 Also, when realizing a low-noise amplifier circuit, the noise generated by the transistor itself is smaller in gallium arsenide semiconductors than in silicon semiconductors due to the difference in their crystal structures. It is advantageous to use a gallium arsenide semiconductor. However, with conventional technology, it is difficult to use uniform crystals for gallium arsenide semiconductors.
Not suitable for high integration.

このためシリコン半導体を使用して回路を構成した場合
には回路雑音が大きく、又単体のガリウムヒ素トランジ
スータを使用し回路を構成した場合には配線長が長くな
り、外来雑音の影響を受け易くなるという欠点があった
。For this reason, when a circuit is constructed using a silicon semiconductor, the circuit noise is large, and when a circuit is constructed using a single gallium arsenide transistor, the wiring length becomes long, making it susceptible to external noise. There was a drawback.

〔発明の目的〕[Purpose of the invention]

本発明の目的とするところは、前記の如き従来の問題点
を除去するものであり、ガリウムヒ素半導体を使用した
高集積増幅回路により回路雑音を／トさくできるという
効果を有する半導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned conventional problems, and to provide a semiconductor device having the effect of suppressing circuit noise using a highly integrated amplifier circuit using a gallium arsenide semiconductor. There is a particular thing.

〔発明の概要〕[Summary of the invention]

この発明の特徴とするところは、低融点導電性材料を介
して、その熱溶融により小規模ガリウムヒ素半導体と大
規模シリコン半導体を物理的、電気的に接続しガリウム
ヒ素手導体、シリコン半導体混在の高集積低雑音増幅回
路を実現することである。The feature of this invention is that it physically and electrically connects a small-scale gallium arsenide semiconductor and a large-scale silicon semiconductor through thermal melting of a low-melting-point conductive material. The objective is to realize an integrated low-noise amplifier circuit.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例につき図面を用いて詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図は本発明の一実施例である半導体装置の断面図を
示すものである。図中、シリコン基板ｌとガリウムヒ素
基板２は、ハンダ３により接続されている。シリコン基
板１は、アルミワイヤ１１により外部接続端子５に接続
されている。FIG. 1 shows a sectional view of a semiconductor device which is an embodiment of the present invention. In the figure, a silicon substrate 1 and a gallium arsenide substrate 2 are connected by solder 3. The silicon substrate 1 is connected to an external connection terminal 5 by an aluminum wire 11.

シリコン基板１は、セラミック基板１２にダイボンディ
ングされている。ガリウムヒ素トランジスタ６は接続引
き出し端子７，８ハンダ３を介してシリコン素子９Ｋｍ
続されている。The silicon substrate 1 is die-bonded to the ceramic substrate 12. The gallium arsenide transistor 6 is connected to a silicon element 9Km via connection lead terminals 7, 8 and solder 3.
It is continued.

第２図は本発明の一実施例である半導体装置の回路図を
示すものである。図中、ガリウムヒ素トランジスタ６、
シリコン抵抗９シリコン素子による定電流源１３．シリ
コン素子による後段増幅回路１４により増幅回路を構成
している。FIG. 2 shows a circuit diagram of a semiconductor device which is an embodiment of the present invention. In the figure, a gallium arsenide transistor 6,
Silicon resistor 9 Constant current source using silicon element 13. An amplification circuit is constituted by a rear-stage amplification circuit 14 made of a silicon element.

この様に構成された半導体装置は、ガリウムヒ素基板２
上の接続引き出し端子７とシリコン基板１上の接続引き
出し端子８に蒸着によりノ・ンダボール３をつけたガリ
ウムヒ素基板２とシリコン基板１を上下に対向して重ね
合わせ３００°Ｃ程度の熱工程を通すことによりハンダ
の熱溶融により接続引き出し端子７，８をハンダを介し
て接続させることができる。又接続引き出し端子７，８
は内部アルミ配線により各々ガリウムヒ素トランジスタ
６、シリコン抵抗９に接続されている。又第２図の如き
回路では、回路雑音は殆んど初段入カドランジスタロが
発生する雑音が支配的である。したがって入力トランジ
スタに低雑音のガリウムヒ素トランジスタを使用してお
けばそれ以外の回路は、シリコン半導体で構成してもす
べてガリウムヒ素半導体で構成した場合と回路雑音量は
同じである。したがって第１図及び第２図に示す如き構
成により高集積低雑音増幅回路を実現できる。A semiconductor device configured in this manner has a gallium arsenide substrate 2
The gallium arsenide substrate 2 with the solder balls 3 attached to the connection lead-out terminals 7 on the top and the connection lead-out terminals 8 on the silicon substrate 1 by vapor deposition and the silicon substrate 1 are stacked vertically facing each other and subjected to a heat process at about 300°C. By passing the solder through, the connecting terminals 7 and 8 can be connected via the solder by thermally melting the solder. Also, connection pull-out terminals 7, 8
are connected to a gallium arsenide transistor 6 and a silicon resistor 9, respectively, by internal aluminum wiring. In the circuit shown in FIG. 2, the circuit noise is dominated by the noise generated by the first stage input quadrant distal. Therefore, if a low-noise gallium arsenide transistor is used as the input transistor, the amount of circuit noise will be the same even if the other circuits are made of silicon semiconductors as if they were all made of gallium arsenide semiconductors. Therefore, a highly integrated low-noise amplifier circuit can be realized by the configuration shown in FIGS. 1 and 2.

〔発明の効果〕〔Effect of the invention〕

以上述べた如き構成であるから本発明にあっては次の如
き効果が得られる。With the configuration as described above, the following effects can be obtained in the present invention.

（１）　ガリウムヒ素半導体を使用した低雑音増幅路の
高集積化ができるため低雑音増幅回路を読み出し信号源
の近くに置くことができ（２）　ガリウムヒ素トランジ
スタとシリコン素子の接続を最少源に短かくすることが
できるため 外来雑音１回路雑音を小さくすることができる。(1) Since the low-noise amplifier circuit using gallium arsenide semiconductor can be highly integrated, the low-noise amplifier circuit can be placed near the readout signal source. (2) The connection between the gallium arsenide transistor and the silicon element can be minimized. Since it can be shortened, external noise and single circuit noise can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の一実施例である半導体装置の断面図
。 第２図は、本発明の一実施例である半導体装置の回路図
。 １・・・シリコン基板、　２・・・ガリウムヒ素基板３
・・・ハンダ ６・・・ガリウムヒ素トランジスタ ７．８・・・接続引き出し端子。 代唖へ汗程士　高　欄　明　大FIG. 1 is a sectional view of a semiconductor device that is an embodiment of the present invention. FIG. 2 is a circuit diagram of a semiconductor device that is an embodiment of the present invention. 1... Silicon substrate, 2... Gallium arsenide substrate 3
...Solder 6...Gallium arsenide transistor 7.8...Connection extraction terminal. To the mute, the person who sweats is high.

Claims (1)

【特許請求の範囲】[Claims] ガリウムヒ素半導体を実装している半導体装置に粘いて
、低融点導電性材料による接続端子をもった該ガリウム
ヒ素半導体と該低融点導電性材料による接続端子をもっ
たシリコン半導体より成り該低融点導電性材料の熱溶融
により、該ガリウムヒ素半導体を該シリコン半導体上に
最短距離で実装し、ガリウムヒ素半導体とシリコン半導
体とにより回路を形成することを特許とする半導体装置
。A semiconductor device mounted with a gallium arsenide semiconductor is made of a gallium arsenide semiconductor having a connection terminal made of a low melting point conductive material and a silicon semiconductor having a connection terminal made of the low melting point conductive material. This semiconductor device is patented in that the gallium arsenide semiconductor is mounted on the silicon semiconductor at the shortest possible distance by thermal melting of a flexible material, and a circuit is formed by the gallium arsenide semiconductor and the silicon semiconductor.
JP59030216A 1984-02-22 1984-02-22 Semiconductor device Pending JPS60175444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59030216A JPS60175444A (en) 1984-02-22 1984-02-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59030216A JPS60175444A (en) 1984-02-22 1984-02-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60175444A true JPS60175444A (en) 1985-09-09

Family

ID=12297525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59030216A Pending JPS60175444A (en) 1984-02-22 1984-02-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60175444A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05109977A (en) * 1991-10-18 1993-04-30 Mitsubishi Electric Corp Semiconductor device
US5444300A (en) * 1991-08-09 1995-08-22 Sharp Kabushiki Kaisha Semiconductor apparatus with heat sink
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444300A (en) * 1991-08-09 1995-08-22 Sharp Kabushiki Kaisha Semiconductor apparatus with heat sink
JPH05109977A (en) * 1991-10-18 1993-04-30 Mitsubishi Electric Corp Semiconductor device
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits

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