JPH0365028B2 - - Google Patents
Info
- Publication number
- JPH0365028B2 JPH0365028B2 JP63182534A JP18253488A JPH0365028B2 JP H0365028 B2 JPH0365028 B2 JP H0365028B2 JP 63182534 A JP63182534 A JP 63182534A JP 18253488 A JP18253488 A JP 18253488A JP H0365028 B2 JPH0365028 B2 JP H0365028B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- superconductor
- low
- electronic circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002887 superconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 14
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910001128 Sn alloy Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000002889 diamagnetic material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Containers, Films, And Cooling For Superconductive Devices (AREA)
Description
【発明の詳細な説明】
本発明は、低温で使用されるジヨセフソン素子
等を用いた電子回路装置等を構成せる電子回路装
置チツプを実装するための低温用配線基板に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low-temperature wiring board for mounting an electronic circuit device chip that constitutes an electronic circuit device using Josephson elements and the like used at low temperatures.
斯種低温用配線基板は、室温と低温との間のヒ
ートサイクルを受けるので、低温用配線基板の基
板本体と電子回路装置チツプとの間に比較的大な
る熱膨張係数の差を有する場合、低温用配線基板
の配線層と電子回路装置チツプの接続用端子乃至
配線層との連結部に破損を生ずるおそれを有する
ものである。 This type of low-temperature wiring board is subjected to heat cycles between room temperature and low temperature, so if there is a relatively large difference in thermal expansion coefficient between the board body of the low-temperature wiring board and the electronic circuit device chip, There is a risk of damage to the connecting portion between the wiring layer of the low-temperature wiring board and the connection terminal or wiring layer of the electronic circuit device chip.
この為従来、低温用配線基板の基板本体と電子
回路装置チツプとの間に熱膨張係数の差ができ得
る限りない様に、電子回路装置チツプがシリコ
ン、サフアイヤ、セラミツク等でなるとして、基
板本体がシリコンでなる低温用配線基板が提案さ
れている。 For this reason, conventionally, the electronic circuit device chip is made of silicon, sapphire, ceramic, etc., so that there is no difference in thermal expansion coefficient between the board body of the low-temperature wiring board and the electronic circuit device chip. A low-temperature wiring board made of silicon has been proposed.
然し乍ら斯る基板本体がシリコンでなる低温用
配線基板の場合、基板本体の機械的強度が弱いた
め、取扱いに不便であつた等の欠点を有してい
た。 However, in the case of such a low-temperature wiring board whose main body is made of silicon, it has drawbacks such as being inconvenient to handle because the mechanical strength of the board main body is weak.
よつて、本発明は斯る欠点のない低温用配線基
板を提案せんとするもので、以下詳述するところ
より明らかとなるであろう。 Therefore, the present invention aims to propose a low-temperature wiring board free from such drawbacks, which will become clear from the detailed description below.
図は本発明による低温用配線基板の一例を示
し、30〜44重量％のNiを含むFe−Ni系合金でな
る基板本体１を有し、その基板本体１の表面に
Nb、50％Pb−50％Sn合金等でなる超伝導体層２
を介して、SiO2等でなる絶縁層３が形成され、
その絶縁層３上に84％Pb−12％In−４％Au合
金、Ta等でなる超伝導体配線層４が、その所要
の一部につき絶縁層３に穿設形成せる開口７を通
じて超伝導体層２に連結されてなる態様で形成さ
れてなる構成を有する。尚、この場合、超伝導体
層２をNbでなるものとするとき、その超伝導体
層２を基板本体１の表面に直接例えば3000Åの厚
さに形成し得、また、絶縁層３をSiO2でなるも
のとするとき、その絶縁層３をNbでなる超伝導
体層２上に例えば5000Åの厚さに形成し得る。
又、超伝導体層２を50％Pb−50％Sn合金でなる
ものとするとき、その超伝導体層２を基板本体１
の表面に例えば鍍金により形成されたCuでなる
導電性層を介して例えば1μｍの厚さに例えば鍍
金法により形成し得、又、絶縁層３をSiO2でな
るものとするとき、その絶縁層３を50％Pb−50
％Sn合金でなる超伝導体層２上に例えば7000Å
の厚さに形成し得る。 The figure shows an example of a low-temperature wiring board according to the present invention, which has a board body 1 made of an Fe-Ni alloy containing 30 to 44% by weight of Ni.
Superconductor layer 2 made of Nb, 50%Pb-50%Sn alloy, etc.
An insulating layer 3 made of SiO 2 or the like is formed through the
On the insulating layer 3, a superconductor wiring layer 4 made of 84%Pb-12%In-4%Au alloy, Ta, etc. is superconducting through an opening 7 formed in the insulating layer 3 in a necessary part thereof. It has a configuration in which it is connected to the body layer 2. In this case, when the superconductor layer 2 is made of Nb, the superconductor layer 2 can be formed directly on the surface of the substrate body 1 to a thickness of, for example, 3000 Å, and the insulating layer 3 can be made of SiO2. 2 , the insulating layer 3 can be formed on the superconductor layer 2 made of Nb to a thickness of, for example, 5000 Å.
Furthermore, when the superconductor layer 2 is made of a 50% Pb-50% Sn alloy, the superconductor layer 2 is formed on the substrate body 1.
For example, when the insulating layer 3 is made of SiO2 , the insulating layer 3 to 50%Pb−50
For example, 7000 Å on the superconductor layer 2 made of %Sn alloy.
It can be formed to a thickness of .
以上が、本発明による低温用配線基板の一例構
成であるが、斯る構成によれば、低温で使用され
るジヨセフソン素子等を用いた電子回路装置（図
示せず）等を構成し且つ一面上に接続用端子乃至
配線層６を有するそれ自体は公知の電子回路装置
チツプ５を、その接続用端子乃至配線層６を超伝
導体配線層４に半田付け等によつて連結せしめ
て、実装し得ること明らかであるが、この場合、
基板本体１が30〜44重量％のNiを含むFe−Ni系
合金でなるので、電子回路装置チツプ５がシリコ
ン、サフアイヤ、セラミツク等でなる場合、基板
本体１が電子回路装置チツプ５との間に熱膨張係
数の差を有しないか有するとしても僅かしか有し
ないものである。因みに基板本体１が35重量％の
Niを含むFe−Ni系合金である場合、その基板本
体１の熱膨張係数は、シリコンの熱膨張係数−
0.02％とほぼ等しく、又、基板本体１が32重量％
のNiを含むFe−Ni系合金である場合、その基板
本体１の熱膨張係数は、サフアイヤ及びセラミツ
クの熱膨張係数−0.1％とほぼ等しいものである。
従つて本発明による低温用配線基板の場合、それ
が室温と低温との間のヒートサイクルを受けて
も、超伝導体配線層４と電子回路装置チツプ５の
接続用端子乃至配線層６との連結部に破損を生ず
る懼れを有しないものである。 The above is an example of the configuration of a low-temperature wiring board according to the present invention. According to such a configuration, an electronic circuit device (not shown) using Josephson elements etc. used at low temperatures can be configured and An electronic circuit device chip 5, which is known per se and has connection terminals or a wiring layer 6, is mounted by connecting the connection terminals or wiring layer 6 to the superconductor wiring layer 4 by soldering or the like. In this case, it is clear that we get
Since the substrate body 1 is made of a Fe-Ni alloy containing 30 to 44% by weight of Ni, if the electronic circuit device chip 5 is made of silicon, sapphire, ceramic, etc. There is no difference in the coefficient of thermal expansion between the two, or if there is, there is only a small difference. By the way, the board body 1 is 35% by weight.
In the case of a Fe-Ni alloy containing Ni, the thermal expansion coefficient of the substrate body 1 is the thermal expansion coefficient of silicon -
Almost equal to 0.02%, and the board body 1 is 32% by weight
In the case of an Fe--Ni alloy containing Ni, the thermal expansion coefficient of the substrate body 1 is approximately equal to the thermal expansion coefficient of sapphire and ceramic -0.1%.
Therefore, in the case of the low temperature wiring board according to the present invention, even if it undergoes a heat cycle between room temperature and low temperature, the connection between the superconductor wiring layer 4 and the connection terminals of the electronic circuit device chip 5 or the wiring layer 6 is maintained. There is no risk of damage to the connecting part.
又、本発明による低温用配線基板の場合、基板
本体１がFe−Ni系合金でなるので、基板本体１
の機械的強度が、基板本体１がシリコンでなる場
合に比し格段的に大であり、従つて取扱いが、基
板本体１がシリコンでなる場合に比し格段的に便
となるものである。更に本発明による低温用配線
基板の場合、基板本体１がFe−Ni系合金でなる
ので、基板本体１の熱伝導性が比較的高く、この
為低温用配線基板を冷却して低温で用いる場合
の、その冷却を各部一様に容易になすことが出来
得るものである。 Furthermore, in the case of the low-temperature wiring board according to the present invention, since the board body 1 is made of a Fe-Ni alloy, the board body 1
The mechanical strength of the substrate body 1 is significantly greater than that in the case where the substrate body 1 is made of silicon, and therefore handling is much easier than in the case where the substrate body 1 is made of silicon. Furthermore, in the case of the low-temperature wiring board according to the present invention, since the board body 1 is made of an Fe-Ni alloy, the thermal conductivity of the board body 1 is relatively high, and therefore, when the low-temperature wiring board is cooled and used at low temperatures. It is possible to uniformly cool each part easily.
又、本発明による低温用配線基板の場合、基板
本体１の表面に形成された超伝導体層２を有する
ので、その超伝導体層２に、図示の如く、超伝導
体配線層４の一部を絶縁層３に形成せる開口７を
通じて連結せしめ得、一方その超伝導体配線層４
の一部に、同様に図示の如く、電子回路装置チツ
プ５の接続用端子乃至配線層６の一部を連結せし
め得、依つて電子回路装置チツプ５の接続用端子
乃至配線層６の一部を、超伝導体層２に連結し得
るものである。この為超伝導体層２を接地導体と
して、これに電子回路装置チツプ５の接地をなす
ことが出来るものである。依つて本発明による低
温用配線基板によれば、その超伝導体層２を接地
導体として用いることにより、電子回路装置チツ
プ５を高密度に実装し得るものである等の大なる
特徴を有するものである。 Further, in the case of the low temperature wiring board according to the present invention, since it has a superconductor layer 2 formed on the surface of the board body 1, a part of the superconductor wiring layer 4 is formed on the superconductor layer 2 as shown in the figure. can be connected through openings 7 formed in the insulating layer 3, while the superconductor wiring layer 4
Similarly, as shown in the figure, connection terminals of the electronic circuit device chip 5 or a portion of the wiring layer 6 can be connected to a portion of the connection terminal of the electronic circuit device chip 5 or a portion of the wiring layer 6. can be connected to the superconductor layer 2. Therefore, the electronic circuit device chip 5 can be grounded by using the superconductor layer 2 as a ground conductor. Therefore, the low temperature wiring board according to the present invention has great features such as being able to mount electronic circuit device chips 5 at high density by using the superconductor layer 2 as a ground conductor. It is.
尚、本発明による低温用配線基板の場合、基板
本体１がFe−Ni系合金であつて磁性を有し、こ
の為電子回路装置チツプ５上のジヨセフソン素子
等が動作の影響を受ける懼れがあると考えられる
も、基板本体１の表面に超伝導体層２を有し、そ
れがマイナス効果によつて反磁性体として作用す
るので、電子回路装置チツプ５上のジヨセフソン
素子等が動作の影響を受けるおそれを実質的に有
しないものである。 In the case of the low-temperature wiring board according to the present invention, the board body 1 is made of an Fe-Ni alloy and has magnetism, so there is a risk that Josephson elements on the electronic circuit device chip 5 will be affected by the operation. Although it is thought that there is a superconductor layer 2 on the surface of the substrate body 1, which acts as a diamagnetic material due to a negative effect, the Josephson element etc. on the electronic circuit device chip 5 may be affected by the operation. There is no substantial risk of exposure to
図は本発明による電子回路装置チツプを実装す
る為の低温用配線基板を示す略線的断面図であ
る。
図中、１は基板本体、２は超伝導体層、３は絶
縁層、４は超伝導体配線層、５は電子回路装置チ
ツプ、６は接続用端子乃至配線層を夫々示す。
The figure is a schematic cross-sectional view showing a low-temperature wiring board on which an electronic circuit device chip according to the present invention is mounted. In the figure, 1 is a substrate body, 2 is a superconductor layer, 3 is an insulating layer, 4 is a superconductor wiring layer, 5 is an electronic circuit device chip, and 6 is a connection terminal or wiring layer.
Claims (1)
る基板本体を有し、該基板本体の表面に超伝導体
層を介して絶縁層が形成され、該絶縁層上に超伝
導体配線層が形成されてなる事を特徴とする電子
回路装置チツプを実装するための低温用配線基
板。 ２ 30〜44重量％のNiを含むFe−Ni系合金によ
る基板本体を有し、該基板本体の表面に超伝導体
層を介して絶縁層が形成され、該絶縁層上に超伝
導体配線層が形成され、上記絶縁層の所要の位置
に開口が形成され、上記超伝導体配線層中の所要
の超電導体配線層が上記開口を通じて上記超伝導
体層に連結されてなる事を特徴とする電子回路装
置チツプを実装するための低温用配線基板。[Scope of Claims] 1. It has a substrate body made of an Fe-Ni alloy containing 30 to 44% by weight of Ni, and an insulating layer is formed on the surface of the substrate body via a superconductor layer, and the insulating layer A low-temperature wiring board for mounting an electronic circuit device chip, characterized by having a superconductor wiring layer formed thereon. 2 It has a substrate body made of a Fe-Ni alloy containing 30 to 44% by weight of Ni, an insulating layer is formed on the surface of the substrate body via a superconductor layer, and superconductor wiring is formed on the insulating layer. a layer is formed, an opening is formed at a required position in the insulating layer, and a required superconductor wiring layer in the superconductor wiring layer is connected to the superconductor layer through the opening. Low-temperature wiring board for mounting electronic circuit device chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63182534A JPS6457683A (en) | 1988-07-21 | 1988-07-21 | Low temperature wiring board for mounting electronic circuit device chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63182534A JPS6457683A (en) | 1988-07-21 | 1988-07-21 | Low temperature wiring board for mounting electronic circuit device chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6457683A JPS6457683A (en) | 1989-03-03 |
| JPH0365028B2 true JPH0365028B2 (en) | 1991-10-09 |
Family
ID=16119986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63182534A Granted JPS6457683A (en) | 1988-07-21 | 1988-07-21 | Low temperature wiring board for mounting electronic circuit device chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457683A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0710005B2 (en) * | 1989-08-31 | 1995-02-01 | アメリカン テレフォン アンド テレグラフ カムパニー | Superconductor interconnection device |
| DE69013310T2 (en) * | 1989-12-22 | 1995-04-27 | Westinghouse Electric Corp | Housing for power semiconductor components. |
| JP3000049B2 (en) * | 1992-03-09 | 2000-01-17 | 京セラ株式会社 | Wiring board |
-
1988
- 1988-07-21 JP JP63182534A patent/JPS6457683A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6457683A (en) | 1989-03-03 |
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