GB1099930A - Improvements in or relating to semiconductor devices - Google Patents

Improvements in or relating to semiconductor devices

Info

Publication number
GB1099930A
GB1099930A GB603/67A GB60367A GB1099930A GB 1099930 A GB1099930 A GB 1099930A GB 603/67 A GB603/67 A GB 603/67A GB 60367 A GB60367 A GB 60367A GB 1099930 A GB1099930 A GB 1099930A
Authority
GB
United Kingdom
Prior art keywords
deposited
insulating layer
aperture
pads
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB603/67A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB1099930A publication Critical patent/GB1099930A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1,099,930. Semi-conductor devices. FAIRCHILD CAMERA & INSTRUMENT CORPORATION. Jan. 4, 1967 [May 31, 1966]. No. 603/67. Heading H1K. Contact pads on a solid state circuit are formed on an insulating layer overlying the components and their interconnections, the pads being arranged so that they overlie circuit components. As shown, Fig. 3, an integrated circuit comprises a transistor 22 formed by diffusion in a silicon wafer and connected to other components by a conductor 32 deposited on a silicon dioxide layer 30. A second insulating layer 34 is deposited over the wafer, an aperture 36 is etched, and a contact pad 16 is deposited on the surface and is connected to region 26 by conductive material filling aperture 36. The connection to region 26 may also be made by etching an aperture 37 in oxide layer 30 and filling with conductive material simultaneously with the production of interconnection 32, depositing the second insulating layer 34 and etching an aperture to expose the first part of the connection, and then depositing the contact pad 16. In a modification, Fig. 4, region 26 is contacted by a conductive strip 52, formed simultaneously with interconnections 32, and extending a short distance over the surface of the oxide layer 30. The second insulating layer 34 is now deposited and part of strip 52 is exposed either by masking during the deposition or by etching. The pad 16 is then deposited on layer 34 and is provided with a portion 50 which contacts strip 52 to complete the connection. The second insulating layer may be of natural or synthetic silicates, refractory metal oxides, mixtures of silica and other metal oxides, and sintered glasses and may be applied by thermal vacuum deposition, sputtering or vapour phase deposition. The contact pads may be of aluminium vapour deposited and may be shaped by a photo-engraving technique. Connections may be applied to the pads by soldering, thermocompression bonding or ultrasonic bonding. The circuit may contain transistors, diodes, FET's, MOS devices, resistors, capacitors, or inductors and may be of the hybrid or thinfilm types.
GB603/67A 1966-05-31 1967-01-04 Improvements in or relating to semiconductor devices Expired GB1099930A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US55413766A 1966-05-31 1966-05-31

Publications (1)

Publication Number Publication Date
GB1099930A true GB1099930A (en) 1968-01-17

Family

ID=24212191

Family Applications (1)

Application Number Title Priority Date Filing Date
GB603/67A Expired GB1099930A (en) 1966-05-31 1967-01-04 Improvements in or relating to semiconductor devices

Country Status (4)

Country Link
DE (1) DE1589779A1 (en)
FR (1) FR1516377A (en)
GB (1) GB1099930A (en)
NL (1) NL6703271A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2637667A1 (en) * 1975-08-22 1977-02-24 Hitachi Ltd SEMI-CONDUCTOR ARRANGEMENT

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925387B2 (en) * 1980-06-10 1984-06-16 株式会社東芝 semiconductor equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2637667A1 (en) * 1975-08-22 1977-02-24 Hitachi Ltd SEMI-CONDUCTOR ARRANGEMENT

Also Published As

Publication number Publication date
FR1516377A (en) 1968-03-08
NL6703271A (en) 1967-12-01
DE1589779A1 (en) 1970-05-06

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