JPS60149167A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60149167A JPS60149167A JP25750984A JP25750984A JPS60149167A JP S60149167 A JPS60149167 A JP S60149167A JP 25750984 A JP25750984 A JP 25750984A JP 25750984 A JP25750984 A JP 25750984A JP S60149167 A JPS60149167 A JP S60149167A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- film
- conductor layer
- leakage current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 29
- 229910052681 coesite Inorganic materials 0.000 abstract description 15
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 15
- 229910052682 stishovite Inorganic materials 0.000 abstract description 15
- 229910052905 tridymite Inorganic materials 0.000 abstract description 15
- 239000000377 silicon dioxide Substances 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 11
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 238000005452 bending Methods 0.000 abstract 1
- 238000001125 extrusion Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は２層ゲート構造を有する半導体装置に関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a semiconductor device having a two-layer gate structure.
多結晶シリコン層を第一ゲートとし、その上に重なる第
二ゲートとの間の絶縁膜として、第一ゲートである多結
晶シリコン層の熱酸化膜を用いた場合を検討する。従来
技術によれば、第一導電形のシリコン基板を熱酸化し第
Ｓ ｔ Ｏ２膜を形成し。A case will be considered in which a polycrystalline silicon layer is used as a first gate, and a thermal oxidation film of the polycrystalline silicon layer, which is the first gate, is used as an insulating film between the polycrystalline silicon layer and a second gate overlying the first gate. According to the prior art, a first conductivity type silicon substrate is thermally oxidized to form a S t O2 film.
その上に多結晶シリコンを堆積し、ホトエツチングによ
り不要部分を除去して第一ゲートを形成する０
次に第一ゲートをマスクにして露出した第−ＳｉＯ□膜
をエツチングで除去したシリコン基板表面を露出させて
、基板と異なる導電形の不純物を拡散させてソースとド
レイン領域を形成する。その後、第一ゲートの多結晶シ
リコンを熱酸化し。Polycrystalline silicon is deposited on top of it, and unnecessary parts are removed by photoetching to form a first gate.Next, using the first gate as a mask, the exposed -SiO□ film is removed by etching, and the silicon substrate surface is then etched. The substrate is exposed and impurities of a conductivity type different from that of the substrate are diffused to form source and drain regions. After that, the polycrystalline silicon of the first gate is thermally oxidized.
ゝ 第一ゲートと第二ゲート間の絶縁膜である第二８ｉ
０．膜を形成してからその上に第二ゲートを形成する。ゝ The second 8i is an insulating film between the first gate and the second gate.
0. After forming the film, a second gate is formed thereon.
第二ゲートとしては多結晶シリコン或は種々の金属が用
いられる。Polycrystalline silicon or various metals are used for the second gate.
上記構造を上記の従来方法で形成すると、第一ゲートと
第二ゲート間にリーク電流が流れ２層ゲート構造を有す
る素子に悪い影響を及ぼすことカニ知られている。この
リーク電流は第一ゲートの多結晶シリコン層に対して第
二ゲートを正にノイイアスした場合に特に顕著であシ、
逆の極性にノくイアスを加えた場合は非常に少ない０こ
の構造を用いて第一ゲートをどこにも接続していないフ
ローティングゲートとし、第一ゲートの４結晶シリコン
表面を熱酸化したＳｉＯ□膜を介して、多結晶シリコン
または金属からなる第二ゲートを重ねて形成したフロー
ティングゲート形の不揮発性メモリトランジスタを構成
すると、フローティングゲートに注入された電子は、半
永久的に保持されるべきところ、第二ゲートが正にバイ
アスされると第一ゲートのフローティングゲートから第
一ゲートと 、第二ゲート間の絶縁膜を通すリーク電流
が流れ。It is known that when the above structure is formed by the above conventional method, a leakage current flows between the first gate and the second gate and adversely affects the device having the two-layer gate structure. This leakage current is particularly noticeable when the second gate is positively biased with respect to the polycrystalline silicon layer of the first gate.
If the opposite polarity is added to the opposite polarity, there will be very little 0 Using this structure, the first gate is made into a floating gate that is not connected to anything, and the SiO When a floating gate type non-volatile memory transistor is formed by overlapping a second gate made of polycrystalline silicon or metal through When the second gate is positively biased, a leakage current flows from the floating gate of the first gate through the insulating film between the first gate and the second gate.
蓄えられた電子が漏れて流出し不揮発性が損われる大き
な欠点があったＯ
以上は不揮発性メモリトランジスタを例にとシリーク電
流の発生と問題点を説明したが、多結晶シリコンを第一
導体層と第二導体層との間の眉間絶縁物の一部に第一導
体層の熱酸化による５ｉｎ２膜をはさむ構造のＲＡＭ
（ｒａｎｄｏｍ ａｃｃｅｓｓｍｅｍｏｒｙ ）用のメ
モリセルや、折りたたみゲート（ｆｏｌｄｅｄ ｇａｔ
ｅ ） 構造の電荷移送素子ＣＯＤなど多くの半導体素
子にとって同様に重要な問題である０
また以上述べてきた欠点はリーク電流に注目しているが
、リーク電流の大きさのみでなく耐圧に関しても、単結
晶シリコン基板を酸化して形成される同じ厚さの５ｉ０
２膜に比べて約１／２程度に低下することが知られてい
る０
問題となるリーク電流の原因は次の様に説明できる０従
来方法は第１図にその断面を示したが既に述べた様に単
結晶シリコン基板（１）の上に５ｉｎ２膜（２）を形成
し、この上の多結晶シリコン層の不要部分（３′）を除
去し第一導体層（３）を形成する（第１図（イ）。次に
（３）をマスクにして５ｉｎ２膜（２）を部分的にエツ
チングして除去しシリコン基板表面を露出させる。（３
）の端部（４）の下のＳｉＯ２膜には切り込みが生じる
（第１図（ロ））。There was a major drawback in that the stored electrons leaked out and the non-volatility was impaired. A RAM with a structure in which a 5in2 film formed by thermal oxidation of the first conductor layer is sandwiched between a part of the eyebrow insulator between the first conductor layer and the second conductor layer.
memory cells for (random access memory) and folded gates.
This is an equally important issue for many semiconductor devices such as the charge transfer device COD with e) structure.Although the above-mentioned drawbacks focus on leakage current, it is important to note that not only the magnitude of leakage current but also the withstand voltage is concerned. 5i0 of the same thickness formed by oxidizing a single crystal silicon substrate
It is known that the leakage current decreases to about 1/2 compared to the 2-layer film.The cause of the leakage current that becomes a problem can be explained as follows.The cross section of the conventional method is shown in Fig. As described above, a 5in2 film (2) is formed on a single crystal silicon substrate (1), and an unnecessary portion (3') of the polycrystalline silicon layer thereon is removed to form a first conductor layer (3). Figure 1 (a). Next, using (3) as a mask, the 5in2 film (2) is partially etched and removed to expose the silicon substrate surface. (3)
) A notch is formed in the SiO2 film under the end (4) of the (FIG. 1(b)).
ここで必要に応じてソースまたはドレインの不純物拡散
層（５）を自己整合的に形成することも可能である。次
に高温で第一導体層（３）を酸化し。Here, it is also possible to form a source or drain impurity diffusion layer (5) in a self-aligned manner if necessary. Next, the first conductor layer (3) is oxidized at high temperature.
５ｉｎ２膜（６）を形成する。この時第−導体層と端部
（４）の下では５ｉｎ２膜が多結晶シリコン側と単結晶
シリコン側と単結晶シリコン基板側の両方から成長する
ため容積が増し端部（４）は上へ押上げられる（第１図
ｅ１）。この状態でＳｉＯ□膜（６）の上に多結晶シリ
コン或いは金属等からなる第二導体層（７）を形成する
と、第一導体層（３）の押上げられた端部（４）と第二
導体層（７）に生じる突出部（８）にとの間４Ｓｉ０２
膜（６）に発生する機械的な歪の影響によシ、第一導体
層（３）と第二導体層（７）との間にリーク電流が流れ
、また耐圧が低下するＯ
また第二導体層（７）とシリコン基板（１）間には耐圧
低下の現象がみられるが、その原因も突出部（８）とシ
リコン基板（１）との間のＳｉｎ、膜の厚さが少ないこ
と、機械的な歪の存在、そして突出部（８）に伴う電界
集中などが原因である０このような欠点を解決しようと
する技術が、特開昭４９−１５３８８号公報や、特開昭
４９−１２８６８５号公報に記載されている。A 5in2 film (6) is formed. At this time, the 5in2 film grows from both the polycrystalline silicon side, the single crystal silicon side, and the single crystal silicon substrate side under the -th conductor layer and the end (4), so the volume increases and the end (4) moves upward. It is pushed up (Fig. 1 e1). When a second conductor layer (7) made of polycrystalline silicon or metal is formed on the SiO□ film (6) in this state, the pushed-up end (4) of the first conductor layer (3) and the 4Si02 between the protrusions (8) and the two conductor layers (7)
Due to the influence of mechanical strain occurring in the membrane (6), a leakage current flows between the first conductor layer (3) and the second conductor layer (7), and the withstand voltage decreases. A decrease in breakdown voltage is observed between the conductor layer (7) and the silicon substrate (1), but this is also caused by the small thickness of the Sin film between the protrusion (8) and the silicon substrate (1). , the existence of mechanical distortion, and electric field concentration accompanying the protrusion (8). Techniques that attempt to solve these drawbacks are disclosed in Japanese Patent Laid-Open No. 49-15388 and Japanese Patent Laid-Open No. 49-1989. It is described in the publication No.-128685.
しかしながら、これらは、イオン打込みによる酸化膜成
長への影響について全く考慮しておらず本願発明とはそ
の立場を異にする技術である０〔発明の目的〕
本発明は、上記の欠点を除きリーク電流が小さく、また
耐圧にも優れた半導体装置とその製造方法を提供するも
のである。However, these techniques do not take into account the influence of ion implantation on oxide film growth and are in a different position from the present invention. The present invention provides a semiconductor device with a small current and excellent breakdown voltage, and a method for manufacturing the same.
すなわち１本発明では、シリコン基板中の不純物濃度が
異なると、酸化速度が異なることを発見したことに基づ
く。That is, one aspect of the present invention is based on the discovery that the oxidation rate differs when the impurity concentration in the silicon substrate differs.
不純物濃度が高い程、酸化速度が速いため、すでに酸化
膜が形成された場合でも、更に充分な酸化速度が得られ
る。The higher the impurity concentration, the faster the oxidation rate, so even if an oxide film has already been formed, a more sufficient oxidation rate can be obtained.
これにより、基板側の酸化速度の遅いことによる（すで
にゲート酸化膜程度の膜厚に酸化されていいる為）ゲー
ト電極めリーク防止−又は、ドレインとの間の耐圧を向
上し得る構造を得る。This provides a structure that can prevent leakage from the gate electrode due to the slow oxidation rate on the substrate side (because it has already been oxidized to a thickness similar to that of the gate oxide film) or improve the breakdown voltage between the gate electrode and the drain.
更に、イオン打込み法による不純物導入によれば、シリ
コン基板に損傷を与える為、更に、酸化速度を速めるこ
とができる。Furthermore, since impurity introduction by ion implantation damages the silicon substrate, the oxidation rate can be further increased.
すなわち、本発明は、イオン打込みを利用した製法によ
り、耐圧の必要な部分の酸化膜厚を厚く形成した半導体
装置及び、当該製造方法である。That is, the present invention is a semiconductor device in which a thick oxide film is formed in a portion where a withstand voltage is required by a manufacturing method using ion implantation, and a manufacturing method thereof.
次に本発明を実施例を用いて説明する。第一導体層と第
二導体層間のリーク電流や耐圧の問題は上記の原因から
明らかなように、第一導体層形成後の工程が大きな影響
を及ぼす。第２図ＫＪは基板゛（１）上にＳｉＯ２層（
２）および第一導体層（３）ととすべき層を形成し、こ
の層の不要部分（３′）を除去し第一導体（３）を設置
した状態を示す。第２図（ロ）は第一導体層（３）を形
成後５ｉｎ２層（２）の上部（２１）を部分的にエツチ
ングで減らした状態を示す。その後、第一導体層（３）
を熱酸化してＳｉＯ□膜（６）を形成する。第２導体層
（７）はその上に形成される（第２図Ｈ）ｏこの場合、
Ｓ ｓ ０２層（２）の上部（２′）を部分的にエツチ
ングすることはＳｉＯ２層表−面を清浄化する意味で好
ましい。Next, the present invention will be explained using examples. As is clear from the above-mentioned causes, the steps after forming the first conductor layer have a large influence on the problems of leakage current and breakdown voltage between the first conductor layer and the second conductor layer. Figure 2 KJ shows a SiO2 layer (
2) and the first conductor layer (3) are formed, an unnecessary portion (3') of this layer is removed, and the first conductor (3) is installed. FIG. 2(b) shows a state in which the upper part (21) of the 5-inch two-layer (2) is partially etched away after the first conductor layer (3) is formed. After that, the first conductor layer (3)
is thermally oxidized to form a SiO□ film (6). A second conductor layer (7) is formed thereon (FIG. 2H); in this case,
It is preferable to partially etch the upper part (2') of the Ss02 layer (2) in order to clean the surface of the SiO2 layer.
本発明の第１の絶縁層はＳｉＯ２暎またはフォスフオシ
リケードガラス、またはボロシリケートガラスまたはそ
れらの複合物を使用することができる。また、第二導体
層は多結晶シリコン層を用いれば良い。第一導体層の端
部（４）の押し上げと、第二導体層の突出部（８）の突
出しの程度はＳｉＯ２層（２）の上部のエツチングによ
シ除去される深さｔに関係する。従って第２図に示した
ＳｉＯ２層（２）（一般には３００〜１５００人、多く
の場合４００〜１３００λ程度である。）の表面の除去
層（２′）の厚さｔをどの範囲内に選べばよいかが重要
になる。リーク電流の大きさから見たｔの値は第１層導
体の熱酸化により形成される ＳｉＯ２膜（６）の厚さ
の１層２以内であることが必要であり第一導体層下の
ＳｉＯ□膜（２）の厚さが１２００人で、第一、第二導
体間の５ｉ０２膜（６）の厚さが。The first insulating layer of the present invention can be made of SiO2 or phosphorus silicate glass, or borosilicate glass, or a composite thereof. Furthermore, a polycrystalline silicon layer may be used as the second conductor layer. The degree of pushing up of the end (4) of the first conductor layer and the protrusion of the protrusion (8) of the second conductor layer are related to the depth t removed by etching of the upper part of the SiO2 layer (2). . Therefore, within what range should you choose the thickness t of the removal layer (2') on the surface of the SiO2 layer (2) (generally 300 to 1500, in most cases about 400 to 1300λ) shown in Figure 2? What is important is whether it is good or not. The value of t in terms of the magnitude of leakage current must be within 1 layer 2 of the thickness of the SiO2 film (6) formed by thermal oxidation of the first layer conductor.
The thickness of the SiO□ film (2) is 1200 mm, and the thickness of the 5i02 film (6) between the first and second conductors.
ＳｉＯ２膜（２）の２倍を越えない素子の場合は実験結
果によればｔの厚さは６００人を越えないことが必要な
ことがわかった。また、他の膜厚のＳｉＯ２層に対して
も大略５ｉｏ２１の厚さの１層２以内で目的を達成する
ことが出来る。この程度のエツチングであれば、わずか
に突出部（８が形成されても、リーク電流の面からは実
質上突起のないものと同等である。In the case of a device whose thickness does not exceed twice the thickness of the SiO2 film (2), it has been found from experimental results that the thickness of t must not exceed 600 mm. Further, even for SiO2 layers having other film thicknesses, the purpose can be achieved within one layer 2 with a thickness of approximately 5io21. With this level of etching, even if a slight protrusion (8) is formed, it is equivalent to substantially no protrusion from the perspective of leakage current.
このことについて、更に詳細には後述する。This will be discussed in more detail later.
第３図は第一導体層（３）を形成してから露出したＳ
ｉ ０２ 層（２）の表面を１００λ以下すなわち実質
的にはほとんどエツチングせず（当然、全くエツチング
せず本発明の効果を奏することができるが他の工程にさ
らされたりし自然に軽くエツチングされることもある。Figure 3 shows the S exposed after forming the first conductor layer (3).
The surface of the i 02 layer (2) is not etched by 100λ or less, that is, it is substantially not etched (of course, it is possible to achieve the effect of the present invention without being etched at all, but if it is exposed to other processes, it may be lightly etched naturally). Sometimes.
）に第一導体層（３）の熱酸化を行なった場合であり、
図３（／１から明らかな様に、第二導体層の突出は全く
見られず、また第一導体層の端部の押し上げもほとんど
見られない。), the first conductor layer (3) is thermally oxidized,
As is clear from FIG. 3(/1), no protrusion of the second conductor layer is observed, and hardly any pushing up of the end of the first conductor layer is observed.
この様な場合には第一導体層と第二導体層間のり−ク電
流は非常に小さく、実用上問題のないレベルとなり、ま
た耐圧も上昇することがわかった０なお、第３図Ｋ）
ｌｄ） （／１は第２図の各々に対応する製造工程に示
す図である。各番号も第２図に示したものと同様である
０
本発明を適用した素子は形成後の断面構造から明らかで
ある。第１図に示す如く ＳｉＯ２膜（２）を第一導体
層をマスクにしてその存在しない部分について完全にと
ち去ると、次の熱酸化工程はシリコン基板に対しては基
板表面から酸化が始まり。In such a case, the leakage current between the first conductor layer and the second conductor layer is extremely small, reaching a level that poses no problem in practice, and the withstand voltage also increases (Fig. 3 K).
ld) (/1 is a diagram showing the manufacturing process corresponding to each of FIG. 2. Each number is the same as that shown in FIG. 2.0 The device to which the present invention is applied can be As shown in Fig. 1, when the SiO2 film (2) is completely removed on the part where it does not exist using the first conductor layer as a mask, the next thermal oxidation process is performed on the silicon substrate. Oxidation begins.
０．４５であることが知られているので第１図の工程を
とったものは−の値から容易に知ることが出来る。Since it is known that the value is 0.45, it can be easily determined from the - value that the process shown in FIG. 1 has been taken.
これに対して第３図の如くＳｉＯ２膜（２）を全くエッ
チせずに第一導体層の熱酸化を行なった場合は、Ｓ ｒ
０２膜（２）の厚さをＤとすると−の値は０．４５（
１−Ｐ ）となり、−に比べて比べて非ｄ ｄ
常に小さくなる。第２図は上記２例の中間となる１Ｄ−
ｔ
が−の大きさは０．４５（１−−）となる。まｄ ｄ
た第１図の特別な例として、第一導体層の下部以外の５
ｉｎ２膜を第一導体層をマスクにして完全に除去した後
、さらにエツチングを継続すると第一導体層の下のＳｉ
Ｏ２の端部はますます深くえぐられて端部（４）は下の
Ｓ ｒ ０２の外側へ突き出して来る。この様な構造で
は第１図ｅｉにおける（４）の形状と（８）の突出が−
そう強調され、リーク電流と耐圧により大きな悪影響を
及ぼす。On the other hand, when the first conductor layer is thermally oxidized without etching the SiO2 film (2) at all as shown in FIG.
If the thickness of the 02 film (2) is D, the negative value is 0.45 (
1-P), and non-d d is always smaller than -. Figure 2 shows 1D- which is between the above two examples.
When t is -, the magnitude is 0.45 (1--). As a special example in Figure 1, 5 parts other than the lower part of the first conductor layer
After completely removing the in2 film using the first conductor layer as a mask, etching is continued to remove the Si under the first conductor layer.
The end of the O2 is hollowed out more and more deeply and the end (4) protrudes outside of the S r 02 below. In such a structure, the shape of (4) and the protrusion of (8) in Figure 1 ei are -
This is emphasized and has a major negative impact on leakage current and withstand voltage.
第４図は上記のそれぞれの場合に対応した実施例の測定
結果である。縦軸は第１ゲートと第２ゲート間のリーク
電流測定値を、リーク電流に効く第一、第二導体層の端
部の単位長さ当υの値に換算して示したものである。横
軸は第一導体層に対である。FIG. 4 shows the measurement results of Examples corresponding to each of the above cases. The vertical axis shows the measured value of the leakage current between the first gate and the second gate, converted into the value of υ, which is equivalent to the unit length of the end portions of the first and second conductor layers, which affects the leakage current. The horizontal axis represents the first conductor layer.
第４図のＡは第１図の工程において、シリコン単結晶基
板（１）の上に１２０ＯＡの熱酸化８ｉ０□膜（２）を
設け、この上に厚さ５０００人の多結晶シリコンからな
る第一導体層（３）を設けてから露出した５ｉｎ２膜を
エッチし、完全の４出部分のＳｉＯ２換が除去されてか
らさらに８００人の５ｉＣＩＪｊ：のエッチ時間だけエ
ツチングを行い第１導体層の端部（４）の効果を使用し
たもので、リーク電流は最も太きく （Ｖ［））が２０
Ｖで８．６Ｘ１０−９Ａ／ｃｍであった。第４図Ｂは、
第一導体層（３）の存在しない部分のＳ ｉ０２膜を完
全に除くのみで特別なエッチ時間の追加を行わなかった
ものであり、す９ ’Ｋ 流ハＶ。カ２０ Ｖテ５．０
Ｘ １０−９Ａ ７ｃｍとなった。第４図のＣは第２
図と同じ工程を用いたもので、Ｓｉ ０２膜（２）の表
面除去層（２′）の厚さｔは６００人のものである。ま
た第４図りは第３図の工程をちったもので５Ｉ０２膜（
２）の表面は実質質にエツチングされていないが１００
λ程度以下の厚さがエツチングによシ除去されているに
過ぎない０
本発明の効果を比較し明らかにするため従来技術を用い
第１図のｅｌの如き断面構造を有する第一導体層がフロ
ーティングゲートとなっているＮチャネルの不揮発性メ
モリトランジスタを形成した。その際第一導体層を設け
た後、シリコン単結晶基板表面の５ｉ０２膜を完全に除
去した後、さらに８００人のＳｉＯ□膜をエッチしうる
時間だけ追加エッチを行なった。このため第１図１の断
面構造はより強調され第４図Ａと同等のリーク電流が流
れると推定できるものである０この構造を採用した不揮
発性メモリトランジスタを用い次の如き動作実験を行な
った。第ニゲ−トドレインに２０Ｖ以上の正バイアス電
圧を加えて書き込みを行ない、フローティングゲート電
子を注入して。A in FIG. 4 shows that a 120 OA thermally oxidized 8i0□ film (2) is provided on a silicon single crystal substrate (1) in the process shown in FIG. After one conductor layer (3) is provided, the exposed 5in2 film is etched, and after the SiO2 exchange in the 4th part is completely removed, etching is performed for an etching time of 800 people to remove the edge of the first conductor layer. The effect of part (4) is used, and the leakage current is the largest at (V[)) at 20
V was 8.6×10 −9 A/cm. Figure 4B is
This method only completely removed the Si02 film in the areas where the first conductor layer (3) did not exist, without adding any special etching time. Ka20 Vte5.0
X 10-9A 7cm. C in Figure 4 is the second
The same process as in the figure was used, and the thickness t of the surface removal layer (2') of the Si 02 film (2) was 600. In addition, the fourth diagram is a 5I02 film (
The surface of 2) is not etched into the parenchyma, but 100
Only a thickness of about .lambda. An N-channel nonvolatile memory transistor with a floating gate was formed. At this time, after providing the first conductor layer and completely removing the 5i02 film on the surface of the silicon single crystal substrate, additional etching was performed for a time sufficient to etch an additional 800 SiO□ films. For this reason, the cross-sectional structure shown in Figure 1 is more emphasized, and it can be assumed that a leakage current equivalent to that shown in Figure 4A flows through it.Using a non-volatile memory transistor employing this structure, the following operation experiment was conducted. . Writing is performed by applying a positive bias voltage of 20 V or more to the second gate drain, and floating gate electrons are injected.
しきい電圧を書込み前の＋３ｖからこの書込み方法で到
達しうる最大値に近い＋１３’／程度まで変化させ書込
みを終了した。その後、ドレーン電圧をＯ■として第二
ゲートのみ正電圧パルスを加えたところ、フローティン
グゲートから第二ゲートにリーク電流が流れ記憶された
状態に対応するしきい電圧が減少して行った。一方、こ
の種のメモリトランジスタを集積してＩＣを構成し書込
みを行う場合にあるメモリトランジスタが書込まれた後
に再度第二ゲートに書込みパルスと同じパルス幅１１１
１ｓ、高さ２０Ｖ以上１周期１０ｍ５の書込み用パルス
がドレーンに正電圧が加えられることなく１秒間すなわ
ち１００回加わることは大いにありうることであるが、
その際に流れるリーク電流によるしきい電圧の変化を第
５図カーブＡに示した。第二ゲートに加えられるパルス
電圧を３０■とすれば、しきい電圧は６．５ Ｖ減少し
、書込み後のしきい電圧の半分以下となシ、書込み前の
しきい電圧値との差が３導以内となるため実用上識売し
にくい。このような電圧パルスの印加の仕方はこの種の
メモリトランジスタの書き込み方法から考えてほぼスタ
ンダードに近いものと考えられる。このため実用に供す
るためには、このパルスが加わった後実用上はしきい電
圧の減少分を上記ためには第４図Ａに比べてリーク電流
の値が約Ａ＠度にすることが是非とも必要である０これ
には第４図Ｃに相当するところまで低下させる必要があ
る。これに必要な手段としては、すでに述べたごとく、
５ｉ０２嘆（２）の表面除去層（２′）の厚さｔｌｓｔ
ｏ２膜の厚さのｉ以下にすればよい。さらにまたこのよ
うなパルス電圧が書込み後第二ゲートだけに２回くシか
えされて加えられる場合や。Writing was completed by changing the threshold voltage from +3V before writing to approximately +13'/approximately the maximum value that could be reached by this writing method. Thereafter, when the drain voltage was set to O■ and a positive voltage pulse was applied only to the second gate, a leakage current flowed from the floating gate to the second gate, and the threshold voltage corresponding to the memorized state decreased. On the other hand, when writing is performed by integrating this type of memory transistor to form an IC, after a certain memory transistor is written, the pulse width 111, which is the same as the write pulse, is applied to the second gate again.
It is very possible that a write pulse of 1 s, height of 20 V or more and 1 period of 10 m5 is applied for 1 second, or 100 times, without a positive voltage being applied to the drain.
Curve A in FIG. 5 shows the change in threshold voltage due to the leakage current flowing at this time. If the pulse voltage applied to the second gate is 30V, the threshold voltage will decrease by 6.5 V, and it will be less than half of the threshold voltage after writing, and the difference from the threshold voltage value before writing will be Since it is within 3rd conductor, it is difficult to judge in practical terms. This method of applying voltage pulses is considered to be almost standard considering the writing method of this type of memory transistor. Therefore, in order to put it into practical use, it is recommended that the leakage current value be approximately A@degrees compared to Figure 4A in order to reduce the threshold voltage after this pulse is applied. This requires a reduction to a point corresponding to FIG. 4C. As already mentioned, the means necessary for this are:
Thickness tlst of surface removal layer (2') of 5i02 (2)
The thickness may be less than or equal to the thickness i of the o2 film. Furthermore, there is a case where such a pulse voltage is applied to only the second gate twice after writing.
書込み条件の２倍の時間第二ゲートに印加された後で正
しく読み出せるに十分な保障となるリーク電流値として
は第４図Ｃの約半分であることが望ましく、これに対応
するｔの値は約４００人であった。またメモリトランジ
スタの書込み後の記憶保持特性にさらに厳しい条件をつ
ける場合、例えば書込み前後のしきい電圧差が数ｖしか
ない様な書込み条件で書込まれた後、第二ゲートにリー
クを誘引する様な電圧パルスがくりかえし加えられる使
用例に耐えるメモリトランジスタとしてはｔ＝０あるい
は１００λ以内の第三図（）ハの如き断面構造が必要で
あり、その様な構造を有する第４図りの如きリーク電流
値のメモリトランジスタを製作して実験した結果高さ＋
２０Ｖ以上５０Ｖ以内１幅１ｍ８周期１０ｍ５のパルス
を３０分間も断続的に印加したにもかかわらず、書込ま
れたメモリトランジスタのしきい電圧変動は第５図りに
示すごと＜ ０． Ｉ Ｖ以内であり記憶保持特性に全
く問題のない優れた不揮発性メモＩＪ ）ランジスタで
あることが明らかであり、不揮発性の最も厳しく要求さ
れる用途に適することがわかった。It is desirable that the leakage current value that is sufficient to ensure correct reading after being applied to the second gate for twice the time of the write condition is about half of the value of C in Figure 4, and the corresponding value of t. There were about 400 people. Furthermore, if stricter conditions are imposed on the memory retention characteristics of the memory transistor after writing, for example, after writing under writing conditions where the threshold voltage difference before and after writing is only a few volts, leakage may be induced in the second gate. For a memory transistor that can withstand applications in which such voltage pulses are repeatedly applied, it is necessary to have a cross-sectional structure as shown in Figure 3 ()C within t = 0 or 100λ, and to prevent leakage as shown in Figure 4 with such a structure. As a result of fabricating and experimenting with a memory transistor with a current value, the height +
Even though a pulse of 20V or more and 50V or more and a width of 1m8 and a period of 10m5 was applied intermittently for 30 minutes, the threshold voltage fluctuation of the written memory transistor was < 0.0 as shown in Figure 5. It is clear that the transistor is an excellent non-volatile memo transistor with no problems in memory retention characteristics and is suitable for applications with the most stringent non-volatility requirements.
本発明の代表的な実施態様を述べると第一の絶絶層はシ
リコン単結晶基板の熱酸化膜であり、第一導体層には多
結晶シリコンのゲート層を含み。In a typical embodiment of the present invention, the first isolation layer is a thermally oxidized film of a silicon single crystal substrate, and the first conductor layer includes a polycrystalline silicon gate layer.
シリコン単結晶基板表面の一部に、基板内部と異なる導
電形の領域が存在しＭＯＳトランジスタのソースまたは
ドレーンまたは導電層または静電容量を構成する電極の
一部として作用することを特徴とする半導体装置である
。A semiconductor characterized in that a region of a conductivity type different from the inside of the substrate exists in a part of the surface of a silicon single crystal substrate and acts as a source or drain of a MOS transistor, a conductive layer, or a part of an electrode constituting a capacitance. It is a device.
第１図は従来方法で作られる二層ゲート構造の製作過程
１４）１０１と完成後の断面四を示す。
第２図は本発明の一実施例を示す説明図であシ。
その製作過程（イ）（ロ）と完成時の断面（ハ）を示す
。
第３図は本発明の別の実施例の製作過程（イ）（ロ）と
完成後の断面図（ハ）を示す。
第４図は第二導体を正に電圧Ｖ。を加え第一導体との間
に流れるリーク電流を測定した結果である。リーク電流
は第一導体の周辺長に比例するので第一導体の周辺の単
位長さ当りのリーク電流値とＶ。との関係を示しだ。カ
ーブＡ、Ｂは二種類の従来方法、カーブＣ，Ｄは本発明
の実施例に相当する測定結果である。
第５図はこの２層ゲート構造をフローティングゲートを
有する不揮発性メモリトランジスタに適用した場合の、
リーク電流によるしきい電圧の減少を示す奥側結果を示
す。Ａは従来方法の例、Ｄは本発明の実施例に対応する
。
１、・・・・・・半導体基板、２．６・・・・・・絶縁
膜、３・・・・・・ゲート電極、５・・・・・・不純物
領域部 ／ 図
第２図
２ ／ 夕
第３図
−２７、ｆ
第 ４図
■
２り
第 夕 図FIG. 1 shows a manufacturing process 14) 101 of a two-layer gate structure made by a conventional method and a cross section 4 after completion. FIG. 2 is an explanatory diagram showing one embodiment of the present invention. The manufacturing process (a) and (b) and the completed cross section (c) are shown. FIG. 3 shows the manufacturing process (a) and (b) of another embodiment of the present invention, and a sectional view after completion (c). Figure 4 shows the second conductor at a positive voltage V. This is the result of measuring the leakage current flowing between the first conductor and the first conductor. Since the leakage current is proportional to the circumference length of the first conductor, the leakage current value per unit length of the circumference of the first conductor is V. Show the relationship. Curves A and B are measurement results corresponding to two conventional methods, and curves C and D are measurement results corresponding to an embodiment of the present invention. Figure 5 shows the case where this two-layer gate structure is applied to a nonvolatile memory transistor with a floating gate.
The back side results show a decrease in threshold voltage due to leakage current. A corresponds to an example of a conventional method, and D corresponds to an example of the present invention. 1. Semiconductor substrate, 2.6 Insulating film, 3 Gate electrode, 5 Impurity region / Figure 2 Figure 2 / Evening Figure 3-27, f Figure 4 ■ 2nd Evening Figure
Claims (1)
膜と、該第１の絶縁膜上に設けられたゲート電極と、該
ゲート電極と自己整合的に設けられたソースおよびドレ
イン領域とを有する半導体装置において、上記ゲート電
極は、その端部が上方へ曲げられて形成されて成ること
を特徴とする半導体装置。 ２、特許請求の範囲第１項記載の半導体装置において、
上記ゲート電極の端部は、上記ゲート電極とソース及び
ドレイン領域との重なった部分であることを特徴とする
半導体装置。 ３、所定の半導体基板の上部に第１の絶縁層を形成する
工程、前記第１の絶縁層上に多結晶シリ；コン層を形成
する工程、前記多結晶シリコン層を所望形状となす工程
、前記多結晶シリコン基板ン層クとして、前記半導体基
板に不純物をイオン打込みによシ導入する工程、前記多
結晶シリコン層及び、前記半導体層に熱酸化膜を形成す
る工程を含むことを特徴とする半導体装置の製造方法。[Claims] 1. A semiconductor substrate and a semiconductor device provided on the substrate. In a semiconductor device having a first insulating film, a gate electrode provided on the first insulating film, and source and drain regions provided in self-alignment with the gate electrode, the gate electrode is A semiconductor device characterized in that its end portion is bent upward. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that an end portion of the gate electrode is a portion where the gate electrode overlaps the source and drain regions. 3. forming a first insulating layer on a predetermined semiconductor substrate; forming a polycrystalline silicon layer on the first insulating layer; forming the polycrystalline silicon layer into a desired shape; The layering of the polycrystalline silicon substrate includes a step of introducing impurities into the semiconductor substrate by ion implantation, and a step of forming a thermal oxide film on the polycrystalline silicon layer and the semiconductor layer. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25750984A JPS60149167A (en) | 1984-12-07 | 1984-12-07 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25750984A JPS60149167A (en) | 1984-12-07 | 1984-12-07 | Semiconductor device and manufacture thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9513576A Division JPS5320781A (en) | 1976-08-10 | 1976-08-10 | Production of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60149167A true JPS60149167A (en) | 1985-08-06 |
Family
ID=17307284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25750984A Pending JPS60149167A (en) | 1984-12-07 | 1984-12-07 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149167A (en) |
-
1984
- 1984-12-07 JP JP25750984A patent/JPS60149167A/en active Pending
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