JPS6122661A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6122661A JPS6122661A JP59143022A JP14302284A JPS6122661A JP S6122661 A JPS6122661 A JP S6122661A JP 59143022 A JP59143022 A JP 59143022A JP 14302284 A JP14302284 A JP 14302284A JP S6122661 A JPS6122661 A JP S6122661A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- silicon dioxide
- silicon
- dioxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 21
- 230000015654 memory Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 64
- 239000000377 silicon dioxide Substances 0.000 abstract description 32
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は溝を用いて容量を形成する半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device that uses grooves to form a capacitor.
（従来技術とその問題点）
現在ＭＯＳダイナミックメモリセルとして広い用いられ
ているセルは、１つのトランジスタと１つ・のコンデン
サからなるメモリセルである。（以下ＩＴＩＣセルと略
す。）
第１図にとのＩＴＩＣセルの模式的断面図を示す。(Prior Art and its Problems) A cell currently widely used as a MOS dynamic memory cell is a memory cell consisting of one transistor and one capacitor. (Hereinafter abbreviated as ITIC cell.) FIG. 1 shows a schematic cross-sectional view of the ITIC cell.
第１図において３がキャパシタ電極で反転層６との間に
絶縁膜５をはさむことによシ記憶容量を形成している。In FIG. 1, numeral 3 denotes a capacitor electrode, and an insulating film 5 is sandwiched between it and an inversion layer 6 to form a storage capacitor.
２はスイッチングトランジスタのゲート電極でワード線
に接続されておシ、ビット線に接続されている拡散層４
と反転層６の間での電荷の移動を制御する。７は隣接メ
モリセルとの分離領域である。従来例において記憶容量
の大きさは、キャパシタ電極３の面積と絶縁膜５の誘電
率及び膜厚によって決定されている。Reference numeral 2 denotes a gate electrode of a switching transistor connected to a word line, and a diffusion layer 4 connected to a bit line.
and the inversion layer 6. 7 is an isolation region from adjacent memory cells. In the conventional example, the size of the storage capacity is determined by the area of the capacitor electrode 3 and the dielectric constant and thickness of the insulating film 5.
近来メモリの大規模化は微細加工技術の進展に伴うメモ
リセルサイズの縮小化によって達成されておシ、従来例
で示したＩＴＩＣセル構造ではキャパシタ電極面積は減
少するばかシである。このため、従来例のＩＴＩＣセル
では絶縁膜５の膜厚を薄くすることによシ記憶容量の大
幅な減少を防いでいた。しかし現在では絶縁膜の膜厚も
もはや限界に近づいている。一方メモリの大規模化を実
現するためにはメモリセルの微細化は必要であシ、この
ため従来構造のＩＴＩＣセルでは高誘電率の絶縁膜を用
いない限シ記憶容量の大きさは減少する一方である。し
かしながら高誘電率の絶縁膜は現在模索段階で近いうち
に実用化されるのは困難である。このように従来型のＩ
ＴＩＣセルは今後増々記憶容量が減少するという問題を
有している。このような記憶容量の減少は、情報の読み
出しを困難にするばかシでなく、雑音に対しても弱くな
シ大きな問題である。このため従来のＩＴＩＣセルでは
もはや対処しきれなくなってきている。In recent years, large-scale memories have been achieved by reducing memory cell sizes with advances in microfabrication technology, and in the ITIC cell structure shown in the conventional example, the capacitor electrode area is reduced. For this reason, in the conventional ITIC cell, a significant decrease in storage capacity was prevented by reducing the thickness of the insulating film 5. However, the thickness of the insulating film is now approaching its limit. On the other hand, in order to increase the scale of memory, it is necessary to miniaturize memory cells, and for this reason, in ITIC cells with conventional structures, the storage capacity decreases unless an insulating film with a high dielectric constant is used. On the other hand. However, an insulating film with a high dielectric constant is currently in the exploratory stage and it is difficult to put it into practical use in the near future. In this way, the conventional I
TIC cells have a problem that their storage capacity will decrease more and more in the future. Such a reduction in storage capacity does not only make it difficult to read information, but also makes it vulnerable to noise, which is a big problem. For this reason, conventional ITIC cells are no longer able to cope with this problem.
このような情勢の中で、従来のメモリセルの容量部の平
面面積を増加させることなく容量を形成する面積を増加
させる方法として、たとえば第４３回応用物理学会学術
講演会の講演予稿集４３４ページに「深い溝のキャパシ
タ形成への応用」と題して発表された講演においては半
導体基板上に溝を設け、その溝の内壁に絶縁膜を形成し
、さらに電極を形成して容量を形成するものが示されて
いる。（以下溝容量と略す）これによシ、容量形成領域
の平面面積を増加させることなく記憶容量を増加させて
いる。Under these circumstances, as a method of increasing the area where the capacitor is formed without increasing the planar area of the capacitor part of the conventional memory cell, for example, there is a method to increase the area where the capacitor is formed without increasing the planar area of the capacitor part of the conventional memory cell. In a lecture titled ``Application of deep grooves to capacitor formation,'' he talked about forming a groove on a semiconductor substrate, forming an insulating film on the inner wall of the groove, and then forming an electrode to form a capacitor. It is shown. (hereinafter abbreviated as groove capacitance) This increases the storage capacity without increasing the planar area of the capacitor formation region.
第２図（ａｌ〜（ｃｌに従来の溝を用いた容量部の製造
プロセスを示す。FIG. 2 shows a manufacturing process of a capacitive part using conventional grooves (al to cl).
第２図（ａ）は、シリコン基板２１上に絶縁膜として二
酸化珪素膜２２を形成した後、その表面を容量形成領域
部を除いてフォトレジスト２３で被った状態を示したも
のである。FIG. 2(a) shows a state in which a silicon dioxide film 22 is formed as an insulating film on a silicon substrate 21, and then its surface is covered with a photoresist 23 except for the capacitor formation region.
第２図（ｂ）は、前記フォトレジスト２３をエツチング
マスクとして異方性エツチング技術によシ前記二酸化珪
素膜２２をエツチング除去し、さらに前記フォトレジス
ト２３を除去した後前記二酸化珪素＠２２′をエツチン
グマスクとして、再び異方性エツチング技術によ）前記
シリコン基板２１をエツチング除去して溝Ａを形成した
状態を示したものである。FIG. 2(b) shows that the silicon dioxide film 22 is etched away by an anisotropic etching technique using the photoresist 23 as an etching mask, and after the photoresist 23 is removed, the silicon dioxide @22' is removed. This figure shows a state in which the silicon substrate 21 is etched away (again using an anisotropic etching technique as an etching mask) to form a groove A.
第２図ｆｅ）は、前記二酸化珪素膜２２′を除去した後
少なくとも前記溝Ａの内壁面を含むように薄い二酸化珪
素膜２４を形成し、さらに多結晶シリコン２５を少なく
とも前記溝Ａの内壁面を含むように形成して容量部を形
成した状態を示したものである。FIG. 2 fe) shows that after removing the silicon dioxide film 22', a thin silicon dioxide film 24 is formed so as to include at least the inner wall surface of the trench A, and polycrystalline silicon 25 is further coated on at least the inner wall surface of the trench A. This figure shows a state in which the capacitor portion is formed by forming the capacitor portion so as to include the capacitor portion.
しかしながら、このような従来の製造方法によって溝を
形成すると溝の上下のシリコン基板端部２６．２７が直
角になる。このためシリコン基板２１とキャパシタ電極
２５との間に形成した絶縁膜２４にかかる電界強度がこ
の溝の上下の端部２６．２７において大きくなる。つま
ルミ界集中が生じる。このため絶縁膜２４の耐圧が劣化
し信頼性上大きな問題である。However, when a groove is formed by such a conventional manufacturing method, the silicon substrate ends 26 and 27 above and below the groove are at right angles. Therefore, the electric field strength applied to the insulating film 24 formed between the silicon substrate 21 and the capacitor electrode 25 becomes large at the upper and lower ends 26 and 27 of this groove. In other words, lumi field concentration occurs. For this reason, the withstand voltage of the insulating film 24 deteriorates, which poses a serious problem in terms of reliability.
（発明の目的）
本発明は、このような従来の欠点を除去せしめて、信頼
性の高い溝容量を形成する製造方法を提供することにあ
る。(Object of the Invention) An object of the present invention is to provide a manufacturing method that eliminates such conventional drawbacks and forms a highly reliable groove capacity.
（発明の構成）
本発明によれば半導体基板上に溝を形成し、該溝を用い
てメモリセルの容量部を形成する半導体装置の製造方法
において、溝形成部およびその周辺の半導体基板表面を
下に凸の円弧形状に加工した後、異方性エツチング技術
を用いて前記加工部分の一部分をエツチング除去して溝
を形成することを特徴とする半導体装置の製造方法が得
られる。(Structure of the Invention) According to the present invention, in a method for manufacturing a semiconductor device in which a groove is formed on a semiconductor substrate and the groove is used to form a capacitor portion of a memory cell, the surface of the semiconductor substrate in and around the groove formation portion is A method for manufacturing a semiconductor device is obtained, which comprises processing the semiconductor device into a downwardly convex arc shape and then etching away a portion of the processed portion using an anisotropic etching technique to form a groove.
（実施例）
以下本発明の実施例について図面を参照して詳細に説明
する。(Example) Examples of the present invention will be described in detail below with reference to the drawings.
第３図（ａ） 、 ｔｂ） 、 ｆｅ） 、 （ｄ）
、 （ｅ） 、 （ｆ）は本発明における溝を用いて容
量部を形成する製造プロセスを順を追って示した模式的
断面図である。Figure 3 (a), tb), fe), (d)
, (e) and (f) are schematic cross-sectional views sequentially showing the manufacturing process of forming a capacitive part using grooves according to the present invention.
第３図（ａ）は、単結晶シリコン基板３１上に二酸化珪
素膜３２、窒化珪素膜３３、二酸化珪素膜３４を順次形
成した後、その表面上を容量形成領域部を除いてフォト
レジスト３５で被った状態を示す。二酸化珪素膜３２は
熱酸化法又はＣＶＤ法によシ又二酸化珪素膜３４はＣＶ
Ｄ法によシ容易に形成できる。FIG. 3(a) shows that after a silicon dioxide film 32, a silicon nitride film 33, and a silicon dioxide film 34 are sequentially formed on a single-crystal silicon substrate 31, a photoresist 35 is applied to the surface of the film except for the capacitor formation region. Indicates the covered state. The silicon dioxide film 32 is formed by a thermal oxidation method or a CVD method, and the silicon dioxide film 34 is formed by a CVD method.
It can be easily formed by method D.
第３図（ｂｌは、前記フォトレジスト３５をエツチング
マスクとして異方性エツチング技術によシ前記二酸化珪
素膜３４．窒化珪素膜３３．二酸化珪素膜３２を順次エ
ツチング除去した状態を示す。FIG. 3 (bl) shows a state in which the silicon dioxide film 34, silicon nitride film 33, and silicon dioxide film 32 are sequentially etched away by an anisotropic etching technique using the photoresist 35 as an etching mask.
第３図（ｃ）は、前記フォトレジスト３５を除去した後
前記窒化珪素膜３３′を耐熱酸化マスクとして容量形成
領域上の前記シリコン基板３１を熱酸化法によシ酸化し
二酸化珪素膜３６を形成した状態を示したものである。FIG. 3(c) shows that after the photoresist 35 is removed, the silicon substrate 31 on the capacitor formation region is oxidized by a thermal oxidation method using the silicon nitride film 33' as a heat-resistant oxidation mask to form a silicon dioxide film 36. This figure shows the formed state.
このように熱酸化法によシ二酸化珪素膜３６を形成する
と、通常のＬＯＣＯ８法によるフィールド酸化膜の形成
時と同様に二酸化珪素膜の横方向へのしみ込みいわゆる
バーズビークが生じる。そしてこのしみ込み量および形
状については前記二酸化珪素３２′の膜厚、窒化珪素３
３′の膜厚および二酸化珪素３６の成長膜厚を選択する
ことによジ制御することができる。When the silicon dioxide film 36 is formed by the thermal oxidation method in this manner, the silicon dioxide film permeates in the lateral direction, resulting in so-called bird's beaks, similar to when a field oxide film is formed by the usual LOCO8 method. The amount and shape of this penetration are determined by the thickness of the silicon dioxide 32' and the thickness of the silicon nitride 32'.
The film thickness can be controlled by selecting the film thickness of silicon dioxide 3' and the growth film thickness of silicon dioxide 36.
第３図（ｄ）は、異方性エツチング技術によシ前記二酸
化珪素膜３６をエツチング除去した状態を示す。前記二
酸化珪素膜３６をエツチング除去した後に現われる前記
シリコン基板表面は、前記二酸化珪素膜３６の形状をそ
のまま転写した形となシ開ロ部の中央と端部でゆるやか
な下に凸の段差が形成される。FIG. 3(d) shows a state in which the silicon dioxide film 36 has been etched away using an anisotropic etching technique. The surface of the silicon substrate that appears after the silicon dioxide film 36 is etched away has a shape that is a direct transfer of the shape of the silicon dioxide film 36, and a gradual downward convex step is formed at the center and end of the seam opening. be done.
第３図＋ｅ＋は、前記二酸化珪素膜３４′をエツチング
マスクとして異方性エツチング技術によシ、前記シリコ
ン基板３１をエツチング除去し溝Ｂを形成した状態を示
す。このエツチングによシエッチング前のシリコン基板
表面の形状はそのまま溝底のシリコン基板表面形状に転
写される。FIG. 3 +e+ shows a state in which the silicon substrate 31 is etched away to form a groove B by anisotropic etching technique using the silicon dioxide film 34' as an etching mask. By this etching, the shape of the silicon substrate surface before etching is directly transferred to the silicon substrate surface shape of the groove bottom.
第３図（ｆ）は、前記二酸化珪素膜３４′、窒化珪素ｉ
１負３３’および二酸化珪素膜３２′を順次除去した後
、少なくとも前記溝Ｂの内壁を被うように薄い絶縁膜３
７および導電性物質３８を形成した状態を示す。前記薄
い絶縁膜３７は、熱酸化法によって形成される二酸化珪
素膜あるいはＣＶＤ法によって形成される窒化珪素膜で
よい。さらに前記導電性物質はリン、ヌボロン等の不純
物原子を含んだ多結晶シリコンあるいは高融点金属でよ
い。FIG. 3(f) shows the silicon dioxide film 34', silicon nitride i
1 negative 33' and the silicon dioxide film 32', a thin insulating film 3 is formed so as to cover at least the inner wall of the groove B.
7 and a conductive material 38 are shown. The thin insulating film 37 may be a silicon dioxide film formed by a thermal oxidation method or a silicon nitride film formed by a CVD method. Further, the conductive material may be polycrystalline silicon containing impurity atoms such as phosphorus or nuboron, or a high melting point metal.
以上述べたように本発明の実施例では第３図（ａ）で示
したように、始めにシリコン基板上に形成する絶縁膜と
して二酸化珪素膜３２−窒化珪素膜３３−二酸化珪素膜
３４の三層構造をとっている。As described above, in the embodiment of the present invention, as shown in FIG. 3(a), the insulating film formed on the silicon substrate is made of three layers: silicon dioxide film 32, silicon nitride film 33, and silicon dioxide film 34. It has a layered structure.
しかしこの三層絶縁膜を厚い一層の二酸化珪素膜におき
かえてもよい。それは、第３図（ｅ）において二酸化珪
素膜３６を形成する際に、開口部でのシリコン基板表面
と厚い二酸化珪素膜で被われたシリコン基板の表面とで
は熱酸化速度に差が生じるために開口部端付近ではバー
ズビークと同様な形状が形成されるからである。However, this three-layer insulating film may be replaced with a thick single-layer silicon dioxide film. This is because when forming the silicon dioxide film 36 in FIG. 3(e), there is a difference in thermal oxidation rate between the surface of the silicon substrate at the opening and the surface of the silicon substrate covered with a thick silicon dioxide film. This is because a shape similar to a bird's beak is formed near the end of the opening.
（発明の効果）
本発明は、シリコン基板を異方性エツチング技術によシ
エッチング除去して溝を形成する時、エツチング前に容
量形成領績を酸化して容量形成領域の端部に意図的にバ
ーズビークを形成して、溝開口部端付近のシリコン基板
表面をなだらかな段差にしている。こうした後に異方性
エツチング技術によシ溝を形成すると、溝の上端部はか
シでなく同時に溝の底の端部での形状までが直角でなく
なだらかな鈍角となる。このように溝の端部形状を直角
からなだらかな鈍角にすることによシ容量を形成する絶
縁膜にかかる電界強度を弱めこれによシ耐圧を大幅に増
加させることができる。(Effects of the Invention) The present invention, when etching away a silicon substrate using anisotropic etching technology to form a groove, oxidizes the capacitance formation region before etching to intentionally remove the etching at the end of the capacitance formation region. A bird's beak is formed on the surface of the silicon substrate near the edge of the groove opening to create a gentle step. When a groove is formed by an anisotropic etching technique after this, the top end of the groove is not an edge, and at the same time, the shape of the bottom end of the groove is not a right angle but a gentle obtuse angle. By changing the shape of the end of the groove from a right angle to a gentle obtuse angle in this way, the electric field strength applied to the insulating film forming the capacitance can be weakened, thereby greatly increasing the withstand voltage.
以上述べた通シ、本発明によれば信頼性の高い溝容量を
形成する製造方法を容易に得ることができる。As described above, according to the present invention, a manufacturing method for forming a highly reliable groove capacitance can be easily obtained.
第１図は従来のＩＴＩＣセルの模式的断面図、第２図（
ａ） 、 （ｂｌ 、 （ｅ）は従来の溝容量部の製造
プロセス ゛を順を追って示した模式的断面図、第３図
（ａｌ〜（ｆ）は、本発明の一実施例をプロセスを追っ
て示した模式的断面図である。
図において各記号はそれぞれ次のものを示す。
１．２１，３１：シリコン基板、２：ワード線に接続し
たスイッチングトランジスタのゲート電極、３：キャパ
シタ電極、４：ビット線に接続された拡散層、５：絶縁
膜、６：反転層、７：分離領域、２２．２２’ 、３２
．３２’ 、３４．３４’ 、３６．３６’−二酸化珪
素膜、２３，３５．：フォトレジスト、２４，３７；薄
い絶縁膜、２５，２８４導電性物質、２６ 、２７：溝
の端部、Ａ、Ｂ＋溝。
笥１図
（α）
（ｂ）
第３図
（シ）Figure 1 is a schematic cross-sectional view of a conventional ITIC cell, and Figure 2 (
a), (bl, and (e) are schematic cross-sectional views showing the conventional manufacturing process of the groove capacitor section in order. It is a schematic cross-sectional view shown later. In the figure, each symbol indicates the following, respectively: 1.21, 31: silicon substrate, 2: gate electrode of switching transistor connected to word line, 3: capacitor electrode, 4 : Diffusion layer connected to bit line, 5: Insulating film, 6: Inversion layer, 7: Isolation region, 22.22', 32
．． 32', 34.34', 36.36'-silicon dioxide film, 23,35. : Photoresist, 24, 37; Thin insulating film, 25, 284 conductive material, 26, 27: Groove end, A, B+groove. Figure 1 (α) (b) Figure 3 (shi)
Claims (1)
の容量部を形成する半導体装置の製造方法において、溝
形成部およびその周辺の半導体基板表面を下に凸の円弧
形状に加工した後、異方性エッチング技術を用いて前記
加工部分の一部分をエッチング除去して溝を形成するこ
とを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which a groove is formed on a semiconductor substrate and the groove is used to form a capacitive portion of a memory cell, after the groove forming portion and the surface of the semiconductor substrate around the groove are processed into a downwardly convex arc shape. . A method of manufacturing a semiconductor device, comprising etching away a portion of the processed portion using an anisotropic etching technique to form a groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143022A JPS6122661A (en) | 1984-07-10 | 1984-07-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143022A JPS6122661A (en) | 1984-07-10 | 1984-07-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6122661A true JPS6122661A (en) | 1986-01-31 |
Family
ID=15329096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59143022A Pending JPS6122661A (en) | 1984-07-10 | 1984-07-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122661A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6444040A (en) * | 1987-08-11 | 1989-02-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH02286571A (en) * | 1989-02-09 | 1990-11-26 | Ind Grafica Meschi Srl | Service for high speed printer and its apparatus |
-
1984
- 1984-07-10 JP JP59143022A patent/JPS6122661A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6444040A (en) * | 1987-08-11 | 1989-02-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH02286571A (en) * | 1989-02-09 | 1990-11-26 | Ind Grafica Meschi Srl | Service for high speed printer and its apparatus |
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