JPS61263261A - Manufacture of mos type semiconductor element - Google Patents
Manufacture of mos type semiconductor elementInfo
- Publication number
- JPS61263261A JPS61263261A JP60105507A JP10550785A JPS61263261A JP S61263261 A JPS61263261 A JP S61263261A JP 60105507 A JP60105507 A JP 60105507A JP 10550785 A JP10550785 A JP 10550785A JP S61263261 A JPS61263261 A JP S61263261A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- region
- source
- semiconductor device
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 24
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 101100478187 Arabidopsis thaliana MOS4 gene Proteins 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＭＯＳｆｉ半導体素子の製造方法に関し、特
に中耐圧及び高耐圧ＭＯＳｔｉ半導体素子と低耐圧ＭＯ
Ｓｆｉ半導体素子と同一基板に同時に形成するＭＯＳ型
半導体素子の製造方法に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a MOSfi semiconductor device, and particularly to a method for manufacturing a MOSfi semiconductor device, and particularly a method for manufacturing a MOSfi semiconductor device, and a method for manufacturing a MOSfi semiconductor device.
The present invention relates to a method for manufacturing a MOS type semiconductor device, which is formed simultaneously on the same substrate as an Sfi semiconductor device.
従来、この種の中耐圧及び高耐圧ＭＯＳ型半導体素子と
低耐圧ＭＯＳｆｉ半導体素子とを同一基板に形成する場
合、中耐圧及び高耐圧ＭＯＳ臘半導体素子の低濃度ドレ
イン（ソース）を形成後、ゲート絶縁膜及びゲート電極
を形成しその後高濃度ドレイン（ソース）を形成してい
た。Conventionally, when forming this type of medium-voltage and high-voltage MOS type semiconductor devices and low-voltage MOS semiconductor devices on the same substrate, after forming the lightly doped drain (source) of the medium- and high-voltage MOS semiconductor devices, the gate An insulating film and a gate electrode were formed, and then a highly doped drain (source) was formed.
従来の製造方法について第２図を用いて説明する０第２
図（ａ）に示すように、ＬＯＣ０８法にて半導体基板２
１にフィールド酸化膜２３、チャンネルストッパー２２
を形成し、次いで中耐圧及び高耐圧ＭＯＳ型半導体素子
の低濃度ドレイン（ソース）領域２９を例えばフォトリ
ソグラフィー技術とイオン注入技術及び熱処理によｐ選
択的に形成する。The conventional manufacturing method will be explained using Fig. 2.
As shown in Figure (a), the semiconductor substrate 2 is
1, field oxide film 23, channel stopper 22
Then, the low concentration drain (source) regions 29 of the medium-voltage and high-voltage MOS type semiconductor elements are formed in a p-selective manner by, for example, photolithography, ion implantation, and heat treatment.
その後、中耐圧及び高耐圧ＭＯＳｆｉ半導体素子と低耐
圧ＭＯＳｆｉ半導体素子のゲート絶縁膜２４を例えば熱
酸化法によｐ形成する。次に、＄２図（ｂ）第２図（Ｃ
）に示すように中耐圧及び高耐圧ＭＯＳｆｉ半導体素子
の高濃度ドレイ／（ソース〕と低耐圧ＭＯＳｉＪ４半導
体素子のドレイ／（ソース）を形成すべく、この領域上
の酸化膜２４をフォトリソグラフィー技術を用い選択的
にエツチングを行なう。Thereafter, the gate insulating films 24 of the medium and high voltage MOSfi semiconductor devices and the low voltage MOSfi semiconductor devices are formed by, for example, a thermal oxidation method. Next, $2 figure (b) figure 2 (C
), the oxide film 24 on this region is removed using photolithography technology in order to form the highly concentrated drain/(source) of the medium-voltage and high-voltage MOSfi semiconductor devices and the drain/(source) of the low-voltage MOSiJ4 semiconductor device. selectively etching.
次Ｋ例えば熱拡散法により高濃度ドレイン（ソース）領
域２７を形成する。このあと、第１図（２）と同様、層
間絶縁膜及びアルミ引き出し電極を形成し、ＭＯＳｆｉ
半導体素子を得ることができる。Next, a highly doped drain (source) region 27 is formed by, for example, a thermal diffusion method. After this, as in FIG. 1 (2), an interlayer insulating film and an aluminum lead electrode are formed, and the MOSfi
A semiconductor element can be obtained.
上述した従来の中耐圧及び高耐圧ＭＯＳｆｉ半導体素子
と低耐圧ＭＯＳｆｉ半導体素子が同一基板上に形成され
ている半導体素子では次のような欠点がある。The above-described conventional semiconductor device in which the medium-voltage and high-voltage MOSfi semiconductor devices and the low-voltage MOSfi semiconductor devices are formed on the same substrate has the following drawbacks.
第１には、ゲート絶縁膜の厚さは中耐圧及び高耐圧ＭＯ
Ｓｆｉ半導体素子の耐圧を決定する１つの要因であり、
通常の低耐圧ＭＯｆ半導体素子のゲート絶縁膜に比べる
と非常に厚いゲート絶縁膜となる。したがって従来の製
造方法で得られる低耐圧ＭＯＳｆｉ半導体素子のＪｂは
非常に低いため高速動作に対して不利になるという欠点
を持っている。Firstly, the thickness of the gate insulating film is the same as for medium and high voltage MOs.
It is one of the factors that determines the breakdown voltage of Sfi semiconductor elements,
The gate insulating film is much thicker than the gate insulating film of a normal low voltage MOf semiconductor element. Therefore, the low breakdown voltage MOSfi semiconductor device obtained by the conventional manufacturing method has a very low Jb, which is disadvantageous for high-speed operation.
第２には、中耐圧及び高耐圧ＭＯＳｔｉ半導体素子にお
りては、低濃度ドレイン領域を形成し急後にゲート電極
を形成している丸め、ゲート［極とドレイン領域のオー
バーラツプ量が大きくなってしまい、グー）−ドレイ／
間の寄生容量が大きくなる。したがって高速動作に対し
ては非常に不利になるという欠点がある。Second, in medium-voltage and high-voltage MOS Ti semiconductor devices, the amount of overlap between the gate electrode and the drain region becomes large due to rounding, where the low concentration drain region is formed and the gate electrode is formed immediately after. , Goo) - Dray/
The parasitic capacitance between them increases. Therefore, it has the disadvantage of being extremely disadvantageous for high-speed operation.
以上、中耐圧及び高耐圧ＭＯＳｆｉ半導体素子と低耐圧
ＭＯＳｆｉ半導体素子では要求されるスピードはそれぞ
れ異なるが、従来の製造方法では両者とも高速動作に対
して不利になるという欠点を持っている。As mentioned above, although the required speeds are different for medium-voltage and high-voltage MOSfi semiconductor devices and low-voltage MOSfi semiconductor devices, conventional manufacturing methods have the disadvantage that they are disadvantageous for high-speed operation.
本発明は上記した従来の欠点を除去し、低耐圧ＭＯＳ屋
半導体素子のゲート酸化膜を中耐圧及び高耐圧のそれよ
り薄くすることにより９ｍの値の向上を計９、又低濃度
及び高濃度ドレイン（ソース）領域の形成後の熱処理を
少なく、かつセル７アライン方法を用いることにエフゲ
ートドレイン間容量を最小にすることにより、高速化さ
れ九中耐圧及び高耐圧ＭＯＳ４半導体素子と低耐圧１ｌ
ｄＯ８減半導体素子を同一基板に形成したＭＯＳ凰半導
体素子の製造方法を提供することを目的とする。The present invention eliminates the above-mentioned conventional drawbacks and improves the value of 9m by making the gate oxide film of a low voltage MOS semiconductor device thinner than that of a medium voltage and high voltage MOS semiconductor device. By minimizing the heat treatment after forming the drain (source) region and using the cell 7 alignment method to minimize the Efgate-drain capacitance, it is possible to increase the speed of MOS4 semiconductor devices with medium and high voltage withstand voltages and with low withstand voltage 1L.
It is an object of the present invention to provide a method for manufacturing a MOS semiconductor device in which a dO8 reduced semiconductor device is formed on the same substrate.
本発明のＭＯ５ＪＩＩ半導体素子の製造方法は、低濃度
ドレイン層と高ｆＩｋ度ドレイン膚を有する中耐圧及び
高耐圧ＭＯＳｆｉ半導体素子を、低耐圧ＭＯＳＯ８減俸
導体素子一基板上に同時に形成する半導体素子の製造方
法において、ゲート領域及びソース・ドレイン領域の絶
縁膜を中耐圧及び高耐圧ＭＯＳｆｉ半導体素子において
は、第１．第２の熱酸化にて形成し、低耐圧ＭＯＳｆｉ
半導体素子に）いては、前記第４の熱酸化後形成された
第１の酸化膜を選択的に除去後前記第２０熱酸化で形成
する第一の工程と、中耐圧及び高耐圧ＭＯＳ４半導体素
子と低耐圧ＭＯＳ凰半導体素子のゲート電極形成後、中
耐圧及び高耐圧ＭＯＳｆｉ半導体素子の低濃度ドレイン
（ソース）を選択的に複数回のイオン注入技術を用いて
形成する第二の工程と、中耐圧及び高耐圧ＭＯＳを半導
体素子の高濃度ドレイン（ソース）領域と低耐圧ＭＯＳ
型半導体素子のドレイン（ソース）領域の前記絶縁膜を
除去し、薄い絶縁膜を形成する第三の工程と、中耐圧及
び高耐圧ＭＯＳｆｉ半導体素子の高濃度ドレイン（ソー
ス）と低耐圧ＭＯＳｇ半導体素子のドレイン（ソース）
をイオン注入技術により形成する第四の工程とを含んで
構成される。The method for manufacturing a MO5JII semiconductor device of the present invention is to manufacture a semiconductor device in which medium and high voltage MOSfi semiconductor devices having a low concentration drain layer and a high fIk drain layer are simultaneously formed on a single substrate of a low voltage MOSO8 low voltage conductor element. In the method, the insulating films of the gate region and the source/drain regions are formed in the first step in the middle voltage and high voltage MOSfi semiconductor devices. Formed by second thermal oxidation, low voltage MOSfi
(for semiconductor devices), a first step of selectively removing the first oxide film formed after the fourth thermal oxidation, and then forming the 20th thermal oxidation; and a middle voltage and high voltage MOS4 semiconductor device. After forming the gate electrode of the low-voltage MOSfi semiconductor device, a second step of selectively forming the low-concentration drain (source) of the medium-voltage and high-voltage MOSfi semiconductor devices using multiple ion implantation techniques; High-concentration drain (source) region of semiconductor element and low-voltage MOS
A third step of removing the insulating film in the drain (source) region of the type semiconductor device and forming a thin insulating film, and a highly concentrated drain (source) of the medium and high voltage MOSfi semiconductor devices and the low voltage MOSg semiconductor device drain (source) of
and a fourth step of forming by ion implantation technology.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（２）〉は本発明の一実施例を説明する
ために工程順に示した断面図であり、本実施例としてＮ
チャンネルｄＭＯＳトツ／ジスタについて説明する。Figures 1 (a) to (2) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention.
Channel dMOS TOTS/JISTA will be explained.
まず、第１図（ａ）に示す工うに、Ｐ型半導体基板１に
チャンネルストッパー領域２を形成後、例えばＬＯＣＯ
８法にてフィールド酸化膜３を形成する。First, as shown in FIG. 1(a), after forming a channel stopper region 2 on a P-type semiconductor substrate 1, for example, a LOCO
A field oxide film 3 is formed using the 8 method.
このとき、チャンネルストッパー領域２は低耐圧ＭＯＳ
トランジスタにおいては従来通りドレイン（ソース）領
域にセルファラインで、中耐圧及び高耐圧ＭＯＳトラン
ジスタにおいてはある間隔（所望の耐圧で変わる〕を取
って形成する。次に能動領域に薄い絶縁膜１１を例えば
熱酸化法を用いて形成する。At this time, the channel stopper region 2 is a low voltage MOS
In transistors, a self-line is formed in the drain (source) region as before, and in medium and high voltage MOS transistors, a certain interval (varies depending on the desired voltage) is formed.Next, a thin insulating film 11 is formed in the active region, for example. Formed using a thermal oxidation method.
次に、第１図（ｂ）に示すように、低耐圧ＭＯＳトラン
ジスタとなる領域の薄い絶縁膜１１を、例えば７ｔ）！
Ｊングラフィー技術及びエツチング技術を用いて選択的
に除去する。Next, as shown in FIG. 1(b), the thin insulating film 11 in the region that will become the low voltage MOS transistor is coated, for example, 7t)!
It is selectively removed using etch technology and etching technology.
次に、第１図０に示すように、例えば熱酸化法によりゲ
ート酸化膜６及び４を形成する。ゲート酸化膜４の膜厚
は、前述の薄い絶縁膜１１をさらに熱酸化したものであ
り、ゲート酸化膜６よシも厚くすることができる。また
、薄い絶縁膜１１の膜厚を変えることにより、ゲート酸
化ｙＸ６と４の膜厚比は自由に決めることができる。Next, as shown in FIG. 1, gate oxide films 6 and 4 are formed by, for example, a thermal oxidation method. The thickness of the gate oxide film 4 is obtained by further thermally oxidizing the thin insulating film 11 described above, and can be made thicker than that of the gate oxide film 6. Furthermore, by changing the thickness of the thin insulating film 11, the ratio of the film thicknesses of the gate oxidations yX6 and 4 can be determined freely.
次に、第１図＠）に示すように、例えばＬＰＣＵＤ法に
より多結晶シリコン膚を形成し、例えばフォトリングラ
フイー技術及びエツチング技術によりゲート多結晶シリ
コン電極５を形成する。次に中耐圧及び高耐圧ＭＯＳ）
ランジスタに、ゲート多結晶シリコン電極５にセルファ
ラインでｎ［低濃度ドレイン（ソース）領域９を、例え
ばフォトリングラフイー技術とイオン注入技術により形
成する。このとき、ｒＮＪＬ低濃度低濃度ドレイ−ス）
領域９は、高濃度ドレイン（ノース）領域に比べ深さを
必要とし、一定濃度で深さを得るために１エネルギーの
異なっ九条件で＊ａ回イオン注入を例えばリン原子で行
なう。ここで１２はイオン注入用のマスクとして使用す
るフォトレジスト膜である０
次に、第１図（ｅ）に示すように、低耐圧ＭＯＳトラン
ジスタのドレイン（ソース）と、中耐圧及び高耐圧ＭＯ
Ｓトランジスタの高濃度ドレイン（ソース）を形成する
ために、フォトリングラフイー技術及びエツチング技術
を用いこの領域の酸化膜を選択的に除去する。次に薄い
酸化膜を例えば熱酸化法によシ形成する。Next, as shown in FIG. 1@), a polycrystalline silicon layer is formed by, for example, the LPCUD method, and a gate polycrystalline silicon electrode 5 is formed by, for example, photophosphorography and etching techniques. Next, medium voltage and high voltage MOS)
In the transistor, an n[low concentration drain (source) region 9] is formed on the gate polycrystalline silicon electrode 5 by self-line, for example, by photophosphorography technology and ion implantation technology. At this time, rNJL low concentration low concentration drase)
The region 9 requires more depth than the highly doped drain (north) region, and in order to obtain the depth at a constant concentration, ion implantation is performed *a times with phosphorus atoms, for example, under nine conditions with one energy difference. Here, 12 is a photoresist film used as a mask for ion implantation. Next, as shown in FIG.
In order to form the highly doped drain (source) of the S transistor, the oxide film in this region is selectively removed using photophosphorography and etching techniques. Next, a thin oxide film is formed by, for example, a thermal oxidation method.
次に、第１図（ｆ）に示すように、例えばヒ素原子のイ
オン注入技術及び熱処理により、低耐圧ＭＯＳトランジ
スタのドレイン（ソース）領域７と中耐圧及び高耐圧Ｍ
ＯＳトランジスタの高濃度ドレイ／（ソースン領域７を
選択的に形成する。この領域は、低濃度ドレイン領域よ
りも浅く濃度の高いイオ／注入を行なう。Next, as shown in FIG. 1(f), the drain (source) region 7 of the low voltage MOS transistor and the medium voltage and high voltage
A heavily doped drain/source region 7 of the OS transistor is selectively formed. This region is shallower than the lightly doped drain region and is implanted with a higher concentration of ions.
次に、第１図（ロ））に示すように、例えばＣＶＤ法に
より層間絶縁膜１０を形成し、例えばフォトリングラフ
イー技術及びエツチング技術によりコンタクトを開口し
、例えばスパッタ法にょクアルミ膜層を形成し、例えば
フォトリソグラフィー技術及びエツチング技術により、
アルミ引き出し電極８を形成する。このようにして、本
発明の一実施例のＭＯＳ凰半導体素子の製造が可能とな
る。Next, as shown in FIG. 1(b), an interlayer insulating film 10 is formed by, for example, a CVD method, contacts are opened by, for example, a photophosphorography technique and an etching technique, and an aluminum film layer is formed by, for example, a sputtering method. For example, by photolithography technology and etching technology,
An aluminum lead electrode 8 is formed. In this way, a MOS semiconductor device according to an embodiment of the present invention can be manufactured.
伺、一実施例としてＮｆｉのＭＯＳトランジスタについ
て説明したが、ＰｆｉＭＯＳ）ランジスタ、あるいはＬ
Ｓ、ＩとしてＣ−ＭＯＳタイプのＷ底でおっても、まっ
たく同様の効果を得ることができる。I have explained Nfi MOS transistor as an example, but PfiMOS) transistor or L
Even if S and I are C-MOS type W bottoms, exactly the same effect can be obtained.
以上説明したように本発明は、中耐圧ＭＯ５ｔＪｌ半導
体と低耐圧ＭＯＳｆｉ半導体素子を同一基板に形成する
時に、低耐圧ＭＯＳ４半導体素子のゲート酸化膜を、中
耐圧及び高耐圧ＭＯａ凰半導体素子のそれより薄くする
ことにより、胛値の向上を図９高速化が可能となる。ま
た、中耐圧及び高耐圧ＭＯＳ型半導体素子の低濃度ドレ
イン（ソース）領域を、ゲート電極形成後ゲート電極に
セルファラインでイオン注入によシ行ない、かつ一定濃
度で所望の深さを得る之めに、イオン注入を数回性なう
。さらに高濃度ドレイン（ソース）領域もイオン注入で
行なう。これによシ、ゲート絶縁膜形成後の熱処理はイ
オン注入領域のアニールだけとなるため、オーバーラツ
プは最小にでき、ゲート・ドレイン間容量を最小にでき
るのでＭＯＳ製半導体素子の高速化ができる効果がある
０As explained above, the present invention, when forming a medium-voltage MO5tJl semiconductor and a low-voltage MOSfi semiconductor element on the same substrate, makes the gate oxide film of the low-voltage MOS4 semiconductor element smaller than that of the medium-voltage and high-voltage MOa oxide semiconductor elements. By making it thinner, it is possible to increase the speed of improvement in the thread value. In addition, the low concentration drain (source) regions of medium and high voltage MOS type semiconductor devices are implanted by ion implantation into the gate electrode using a self-alignment line after the formation of the gate electrode, and the desired depth is obtained at a constant concentration. Then, ion implantation was performed several times. Furthermore, the highly doped drain (source) region is also implanted by ion implantation. As a result, the heat treatment after forming the gate insulating film is only for annealing the ion implanted region, so the overlap can be minimized and the gate-drain capacitance can be minimized, which has the effect of increasing the speed of MOS semiconductor devices. Some 0
第１図（ａ）〜Ｉｇ）は、本発明の一実施例を説明する
ために工程順に示した断面図、第２図−）〜（Ｃ）は従
来のＭＯＳＯ８半体導体素子造方法を説明するために工
程順に示した断面図である。
１．２１・・・・・・半導体基板、２．２２・・・・・
・チャンネルストッパー、３．２３・・・・・・フィー
ル）’ ｆｉ 化膜、４．６．２４・・・・・・ゲート
絶縁膜、５，２５・・・・・・ゲート電極、９，２９・
・・・・・低濃度ドレイ／層、７゜２７・・・・・・高
濃度ドレイン、８・・・・・・アルミ引き出し電極、１
０・・・・・・層間絶縁膜、１１・・・・・・絶縁膜、
１２・・・・・・フォトレジスト膜。
第１図
躬／図Figures 1(a) to Ig) are cross-sectional views shown in order of steps to explain an embodiment of the present invention, and Figures 2-) to (C) illustrate a conventional MOSO8 semiconductor device manufacturing method. FIG. 1.21... Semiconductor substrate, 2.22...
・Channel stopper, 3.23...Fi film, 4.6.24...Gate insulating film, 5,25...Gate electrode, 9,29・
...Low concentration drain/layer, 7゜27...High concentration drain, 8...Aluminum extraction electrode, 1
0... Interlayer insulating film, 11... Insulating film,
12...Photoresist film. Figure 1/Figure
Claims (1)
び高耐圧ＭＯＳ型半導体素子を低耐圧ＭＯＳ型半導体素
子と同一基板上に同時に形成するＭＯＳ型半導体素子の
製造方法において、ゲート領域及びソース・ドレイン領
域の絶縁膜を中耐圧及び高耐圧ＭＯＳ型半導体素子にお
いては第１、第２の熱酸化にて形成し、低耐圧ＭＯＳ型
半導体素子においては前記第１の熱酸化後形成された第
１の酸化膜を選択的に除去後前記第２の熱酸化で形成す
る第一の工程と、中耐圧及び高耐圧ＭＯＳ型半導体素子
と低耐圧ＭＯＳ型半導体素子のゲート電極形成後、中耐
圧及び高耐圧ＭＯＳ型半導体素子の低濃度ドレイン（ソ
ース）を選択的に複数回のイオン注入技術を用いて形成
する第二の工程と、中耐圧及び高耐圧ＭＯＳ型半導体素
子の高濃度ドレイン（ソース）領域と低耐圧ＭＯＳ型半
導体素子のドレイン（ソース）領域の前記絶縁膜を除去
し、薄い絶縁膜を形成する第三の工程と、中耐圧及び高
耐圧ＭＯＳ型半導体素子の高濃度ドレイン（ソース）と
低耐圧ＭＯＳ型半導体素子のドレイン（ソース）をイオ
ン注入技術により形成する第四の工程とを含むことを特
徴とするＭＯＳ型半導体素子の製造方法。In a method for manufacturing a MOS type semiconductor device, in which medium and high voltage MOS semiconductor devices having a low concentration drain layer and a high concentration drain layer are simultaneously formed on the same substrate as a low voltage MOS semiconductor device, gate regions and source/drain regions are formed. In medium-voltage and high-voltage MOS type semiconductor devices, the insulating film in the region is formed by first and second thermal oxidation, and in low-voltage MOS type semiconductor devices, the first thermal oxidation film is formed after the first thermal oxidation. A first step of selectively removing the oxide film and then forming it by the second thermal oxidation; and after forming gate electrodes of medium and high voltage MOS semiconductor devices and low voltage MOS semiconductor devices; A second step of selectively forming a low concentration drain (source) of a MOS type semiconductor device using multiple ion implantation techniques, and a high concentration drain (source) region of a medium voltage and high voltage MOS type semiconductor device. a third step of removing the insulating film in the drain (source) region of the low voltage MOS type semiconductor device and forming a thin insulating film; A method for manufacturing a MOS type semiconductor device, comprising a fourth step of forming a drain (source) of a voltage resistant MOS type semiconductor device using an ion implantation technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105507A JPS61263261A (en) | 1985-05-17 | 1985-05-17 | Manufacture of mos type semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105507A JPS61263261A (en) | 1985-05-17 | 1985-05-17 | Manufacture of mos type semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61263261A true JPS61263261A (en) | 1986-11-21 |
Family
ID=14409511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60105507A Pending JPS61263261A (en) | 1985-05-17 | 1985-05-17 | Manufacture of mos type semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263261A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173748A (en) * | 1987-12-28 | 1989-07-10 | Matsushita Electron Corp | Semiconductor integrated circuit device |
| JPH036855A (en) * | 1989-06-05 | 1991-01-14 | Takehide Shirato | Semiconductor device |
| JPH04324973A (en) * | 1991-04-09 | 1992-11-13 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| JPH0536719A (en) * | 1990-11-05 | 1993-02-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH05102478A (en) * | 1991-10-09 | 1993-04-23 | Nec Corp | Semiconductor device |
| JPH06216380A (en) * | 1992-10-07 | 1994-08-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP2006140318A (en) * | 2004-11-12 | 2006-06-01 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit and method of manufacturing the same |
| JP2006173642A (en) * | 2000-12-05 | 2006-06-29 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| JP2006190831A (en) * | 2005-01-06 | 2006-07-20 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2006295008A (en) * | 2005-04-13 | 2006-10-26 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus and its manufacturing method |
| JP2011181694A (en) * | 2010-03-01 | 2011-09-15 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
-
1985
- 1985-05-17 JP JP60105507A patent/JPS61263261A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173748A (en) * | 1987-12-28 | 1989-07-10 | Matsushita Electron Corp | Semiconductor integrated circuit device |
| JPH036855A (en) * | 1989-06-05 | 1991-01-14 | Takehide Shirato | Semiconductor device |
| JPH0536719A (en) * | 1990-11-05 | 1993-02-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04324973A (en) * | 1991-04-09 | 1992-11-13 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| JPH05102478A (en) * | 1991-10-09 | 1993-04-23 | Nec Corp | Semiconductor device |
| JPH06216380A (en) * | 1992-10-07 | 1994-08-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP2006173642A (en) * | 2000-12-05 | 2006-06-29 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| JP2006140318A (en) * | 2004-11-12 | 2006-06-01 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit and method of manufacturing the same |
| JP2006190831A (en) * | 2005-01-06 | 2006-07-20 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2006295008A (en) * | 2005-04-13 | 2006-10-26 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus and its manufacturing method |
| JP2011181694A (en) * | 2010-03-01 | 2011-09-15 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
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