JPS60122447A - Battery backup circuit - Google Patents

Battery backup circuit

Info

Publication number
JPS60122447A
JPS60122447A JP58230318A JP23031883A JPS60122447A JP S60122447 A JPS60122447 A JP S60122447A JP 58230318 A JP58230318 A JP 58230318A JP 23031883 A JP23031883 A JP 23031883A JP S60122447 A JPS60122447 A JP S60122447A
Authority
JP
Japan
Prior art keywords
circuit
power supply
memory circuit
power
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58230318A
Other languages
Japanese (ja)
Inventor
Hideaki Tokuji
徳地　秀昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58230318A priority Critical patent/JPS60122447A/en
Publication of JPS60122447A publication Critical patent/JPS60122447A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2015—Redundant power supplies

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To prevent the destruction of a memory circuit by turning off a power supplied to an open collector gate circuit and controlling the selection of the memory circuit and input/output of an address or the like when the power of the memory circuit is backed up by an auxiliary power supply circuit. CONSTITUTION:A transistor (TR) 19 is provided which is inserted between a power supply and a power supply terminal 15 of the memory circuit 16 and applying on/off control of power supply to the circuit 16, and a voltage detecting circuit 17 is provided which controls the turning-on of TRs 19, 20 when a power supply ovoltage VCC is a prescribed value or over and controlling turning-off when the VCC is a prescribed value or below. If the power supply is interrupted or decreased to a prescribed voltage or below due to any cause, since the circuit 17 detects it and turns off the TRs 19, 20, the voltage VCC is disconnected. Then the power of an auxiliary power circuit 18 is applied to a terminal 15 of the circuit 16, the power of an open collector gate circuit 13 is interrupted so as to bring a CS terminal of the circuit 16 and OE terminals 21, 22 of tri-state buffer circuits 21, 22 to a high impedance input state.

Description

【発明の詳細な説明】 本発明はメモリ回路の電源をバックアップするバッテリ
バックアップ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a battery backup circuit for backing up the power supply of a memory circuit.

メモリ回路の電源断あるいは異常な電圧低下時、その記
憶内容を保護するためにバッテリバックアップ回路が用
いられている。A battery backup circuit is used to protect the memory contents when the power of the memory circuit is cut off or the voltage drops abnormally.

第１図は従来のバッテリバック７２１回路の構成を示す
回路図である。バツテリバツクアツ−２− ブ回路はＣ８入力端子２より電圧Ｖｃｃが印加されてい
るとき、開いてＣ８入力端子１よりのＣ８信号をメモリ
回路６のＣ８端子４に入力可能とし、電圧Ｖｃｃが断と
々つだときハイインピーダンス状態となってＣ８信号を
阻止するオープンコレクタゲート回路３と、電源電圧を
検出する電圧検出回路２と、この電圧検出回路２の出力
によりオンオフ制御され、Ｖｃｃ入力端子２よりの電力
をメモリ回路のＶｃｃ端子５に供給するｆｃめのトラン
ジスタ９と、電源のバックアップをする補助電源回路８
より構成されている。FIG. 1 is a circuit diagram showing the configuration of a conventional battery back 721 circuit. The battery backup circuit opens when voltage Vcc is applied from C8 input terminal 2, allowing the C8 signal from C8 input terminal 1 to be input to C8 terminal 4 of memory circuit 6, and voltage Vcc is disconnected. An open collector gate circuit 3 that enters a high impedance state and blocks the C8 signal when the voltage is high, a voltage detection circuit 2 that detects the power supply voltage, and an on/off control controlled by the output of this voltage detection circuit 2, and a Vcc input terminal 2. An fc transistor 9 supplies more power to the Vcc terminal 5 of the memory circuit, and an auxiliary power supply circuit 8 backs up the power supply.
It is composed of

電圧検出回路７は例えば電源電圧が４．７５Ｖ〜５．２
５Ｖのとき、トランジスタ９をオン状態に制御している
ので、この範囲の電源電圧値の場合、メモリ回路６はＶ
ｃｃ入力端子より電力が供給されている。For example, the voltage detection circuit 7 has a power supply voltage of 4.75V to 5.2V.
Since the transistor 9 is controlled to be in the ON state when the voltage is 5V, the memory circuit 6 is controlled to be in the ON state when the power supply voltage is in this range.
Power is supplied from the cc input terminal.

停電、その他の原因によりＶｃｃが断、まだは４．７５
Ｖ未満に低下した場合は、電圧検出回路はＶｃｃの異常
を検出し、トランジスタ９′ｆ：オフ状態に制御するの
で、Ｖｃｃ入力端子２からの電力は断たれ、代わりに補
助電源回路８の電力が供給される。Vcc is disconnected due to power outage or other causes, still 4.75
If the voltage drops below V, the voltage detection circuit detects an abnormality in Vcc and controls the transistor 9'f to turn off, so the power from the Vcc input terminal 2 is cut off and the power from the auxiliary power supply circuit 8 is turned off instead. is supplied.

補助電源回路８はＶｃｃ以下のもの、例えば３Ｖ程度の
ものが使用され、Ｖｃｃ入力端子２より電力が供給され
ているとき、バッチＩＪ８ａの放電を防止し、長寿命化
が図られている。The auxiliary power supply circuit 8 uses a voltage lower than Vcc, for example, about 3V, and when power is supplied from the Vcc input terminal 2, it prevents the batch IJ 8a from discharging and extends its life.

ところで、メモリ回路６はＶｃｃが４．５Ｖ程度に低下
した場合、その動作は保証されておらず、Ｃ８端子４が
イネーブルになったとき外部から入力される信号（例え
ばアドレス信号）によシ誤動作し、メモリ内容の破壊や
供給電流の増加が起こる。By the way, the operation of the memory circuit 6 is not guaranteed when Vcc drops to about 4.5V, and malfunction may occur due to signals input from the outside (for example, address signals) when the C8 terminal 4 is enabled. However, the memory contents may be destroyed or the supply current may increase.

したがって、Ｖｃｃがある程度低下し、オープンコレク
タゲート回路３が開いている状態で、補助電源回路８よ
り電力の供給を受けている場合は上記の問題が生じ、メ
モリ内容の保持の信頼性およびバッテリの長寿命化を損
うという欠点があった。Therefore, when power is being supplied from the auxiliary power supply circuit 8 while Vcc has decreased to some extent and the open collector gate circuit 3 is open, the above-mentioned problem will occur, reducing the reliability of memory content retention and the battery life. This had the disadvantage of impairing longevity.

本発明の目的は上述の問題全解決できるバッテリバック
アップ回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a battery backup circuit that can solve all of the above problems.

前記目的全達成するために本発明によるバッテリバック
アップ回路はデータ全記憶するメモリ回路の電源をバッ
クアップするバッテリバックアップ回路において、電源
とメモリ回路の電源端子との間に挿入され、メモリ回路
への電力供給ノオンオフ制？ｆｆｆｌｅする第１のトラ
ンジスタと、前記電源に接続された第２のトランジスタ
と、電源電圧値が一定値以上のときは第１および第２の
トランジスタ金オン制御し、一定値以下のときけオフ制
御する電圧検出回路と、第１のトランジスタとメモリ回
路との接続点に接続されており、メモリ回路に電源の電
力が供給されて論ないときはメモリ回路に供給せず、メ
モリ回路に電源の′電力が供給されているときはメモリ
回路に供給する、前記電源の使用可能電圧値より低い電
圧値の補助電源回路と、メモリ回路に入力されるアドレ
ス信号と入出力データをイネーブル、ディスエーブルす
るスリーステートバスバッファ回路と、前記′ｉＡ２の
トランジスタに接続されており、第２のトランジスタの
オフでメモリ回路のＣ８端子およびスリーステートバス
バッファ回路のＯＥ端子をハイインピーダンス入力状態
とするオープンコレクタゲート回路とからなり、電源電
圧断または低下時に、・補助電源回路の電力をメモリ回
路に供給するとともにメモリ回路のアドレスの入力、デ
ータの入出力およびメモリ回路の選択を禁止するように
構成しである。In order to achieve all of the above objects, a battery backup circuit according to the present invention is inserted between a power source and a power terminal of the memory circuit in a battery backup circuit that backs up the power of a memory circuit that stores all data, and supplies power to the memory circuit. No-on-off system? ffffle first transistor, a second transistor connected to the power supply, and when the power supply voltage value is above a certain value, the first and second transistors are turned on, and when the power supply voltage value is below the certain value, they are turned off. The voltage detection circuit is connected to the connection point between the first transistor and the memory circuit, and when it is not necessary to supply power to the memory circuit, the power is not supplied to the memory circuit, and the power is not supplied to the memory circuit. an auxiliary power supply circuit with a voltage lower than the usable voltage value of the power supply, which supplies the memory circuit when power is supplied; a state bus buffer circuit; and an open collector gate circuit that is connected to the transistor 'iA2 and puts the C8 terminal of the memory circuit and the OE terminal of the three-state bus buffer circuit in a high impedance input state when the second transistor is turned off. When the power supply voltage is cut off or decreased, power from the auxiliary power supply circuit is supplied to the memory circuit, and address input to the memory circuit, data input/output, and selection of the memory circuit are prohibited.

前記構成によれば誤動作によるメモリ回路の内容の破壊
とバッテリの供給電流の増加を防止でき本発明の目的は
完全に達成できる。According to the above configuration, the destruction of the contents of the memory circuit and the increase in the supply current of the battery due to malfunction can be prevented, and the object of the present invention can be completely achieved.

以下、図面を参照［２，て本発明をさらに詳しく説明す
る。第２図は本発明によるバッテリバックアップ回路の
実施例を示す回路図である。The present invention will be described in more detail below with reference to the drawings. FIG. 2 is a circuit diagram showing an embodiment of the battery backup circuit according to the present invention.

１１Ｅ　源電圧Ｖｃｃ　カ許容範囲（４，７５Ｖ　〜５
．２５Ｖ　）を満たしている場合、電圧検出回路１７の
ＶＩＮ入力端子にＶｃｃが印加されているので、電圧検
出回路１７は第１のトランジスタ１９および第２のトラ
ンジスタ２０をオン状態に制御している。11E Source voltage Vcc tolerance range (4,75V ~ 5
．． 25V), Vcc is applied to the VIN input terminal of the voltage detection circuit 17, so the voltage detection circuit 17 controls the first transistor 19 and the second transistor 20 to be in the on state.

したがってメモリ回路１６のＶｃｃ端子１５にはＶｃｃ
入力端子１２、トランジスタ１９を介して電源が接続さ
ねており、さらにオーブンコレクタゲート回路１３はＣ
８信号のメモリ回路１６のＣ８端子１４への入力を可能
としており、スリ−スケートバスバッファ回路２１，２
２のｏＥ端子はイネーブル状態となっている。Therefore, Vcc is applied to the Vcc terminal 15 of the memory circuit 16.
A power supply is connected through the input terminal 12 and the transistor 19, and the oven collector gate circuit 13 is connected to the C
It is possible to input 8 signals to the C8 terminal 14 of the memory circuit 16, and the three-skate bus buffer circuits 21, 2
The oE terminal No. 2 is in an enabled state.

これはメモリ回路１６の動作可能状態で、メモリ回路１
６にＣ８信号、メモリ・ライト信号、メモリ・リード信
号、アドレス信号、データ信号を与えることにより所定
のアドレス（（任意のデータ全書き込んだり、読み出し
たりすることが可能である。This is the operable state of the memory circuit 16, and the memory circuit 1
By supplying the C8 signal, memory write signal, memory read signal, address signal, and data signal to 6, it is possible to write or read all arbitrary data at a predetermined address.

次に電源電圧Ｖｃｃが何等かの原因で断、または４．７
５Ｖ以下に低下した場合、電圧検出回路１７はこれを検
出してトランジスタ１９．２０’（ｉ７オフ状態にする
ので、電源箱；圧Ｖｃｃはトランジスタ１９　、２０に
よって切断される。これによりメモリ回路１６の電源端
子１５には補助電源回路１８の電力が供給されるととも
に、オーブンコレクタゲート回路１３は電源を断たれる
ため、メモリ回路２１　、２２のＯＥ端子２１　、２２
を］・イインピーダンス入力状態にする。したがって、
メモリ回路１６のＣ８端子てはｃ　ｓ　４Ｂ号は供給さ
れず、仮にＣ８入力端子１１がイネーブル状態になって
も、メモリ回路１６は選択されず、アドレス。Next, the power supply voltage Vcc is disconnected for some reason, or 4.7
When the voltage drops below 5V, the voltage detection circuit 17 detects this and turns off the transistors 19 and 20' (i7), so the voltage Vcc is cut off by the transistors 19 and 20. As a result, the memory circuit 16 The power of the auxiliary power circuit 18 is supplied to the power supply terminal 15 of the memory circuits 21 and 22, and the power of the oven collector gate circuit 13 is cut off.
]・Set to impedance input state. therefore,
The C8 terminal of the memory circuit 16 is not supplied with the CS4B signal, and even if the C8 input terminal 11 is enabled, the memory circuit 16 is not selected and the address is not supplied.

データの入力もスリースケートバスバッファ回路２１　
、２２によって禁止され、メモリ回路１６の誤動作によ
る内容の破壊と、補助電源回路１８の電流の増加を防ぐ
ことができる。Three-skate bus buffer circuit 21 also inputs data.
, 22, it is possible to prevent the contents from being destroyed due to malfunction of the memory circuit 16 and an increase in the current of the auxiliary power supply circuit 18.

以上、詳しく説明したように本発明によるバッテリバッ
クアップ回路はメモリ回路の電源が補助電源回路にバッ
クアップされたとき、オーブンコレクタゲート回路に印
加されている電源をオフにし、メモリ回路の選択、アド
レスおよびデータの入出力を禁止するように構成しであ
るので、従来回路に比してメモリ内容保持の信頼性およ
び、補助電源回路のバッテリの長寿命化が実現できる。As described above in detail, the battery backup circuit according to the present invention turns off the power applied to the oven collector gate circuit when the power of the memory circuit is backed up by the auxiliary power circuit, and selects the memory circuit, addresses and data. Since the input/output of the auxiliary power supply circuit is configured to be prohibited, it is possible to achieve more reliable memory content retention and a longer battery life of the auxiliary power supply circuit than in conventional circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図は従来のメモリ回路のバッテリバックアップ回路
の回路図、第２図は本発明によるバッテリバックアップ
回路の実施例を示す回路図である。 １　、１１・・・ＣＳ入力端子・ ２．１２・・・Ｖｃｃ入力端子 ３．１３・・・オーブンコレクタゲート回路４．１４・
・・メモリ回路のＣ８端子 ５．１５・・・メモリ回路の電源端子 ６．１６・・・メモリ回路 ７．１７・・・電圧検出回路 ８．１８・・・補助電源回路 ９　、１９　、２０・・・トランジスタ２１　、２２・
・・スリーステートバスバッファ回路特許出願人　日本
電気株式会社 代理人　弁理士　井ノロ　壽Figure 1 is a circuit diagram of a conventional battery backup circuit for a memory circuit, and Figure 2 is a circuit diagram showing an embodiment of the battery backup circuit according to the present invention. 1, 11...CS input terminal・2.12...Vcc input terminal 3.13...Oven collector gate circuit 4.14・
... C8 terminal of the memory circuit 5.15 ... Power supply terminal of the memory circuit 6.16 ... Memory circuit 7.17 ... Voltage detection circuit 8.18 ... Auxiliary power supply circuit 9, 19, 20.・Transistor 21, 22・
...Three-state bus buffer circuit patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

【特許請求の範囲】 データを記憶するメモリ回路の電ｉｔバックアップする
バッテリバックアップ回路において、電源とメモリ回路
の電源端子との間に挿入され、メモリ回路への電力供給
のオンオフ制御をする第ｌのトランジスタと、前記電源
に接続された第２のトランジスタと、電源電圧値が一定
値以上のときは第１および第２のトランジスタをオフ制
御し４、一定値以下のときはオフ制御する電圧検出回路
と、第１のトランジスタとメモリ回路との接続点に接続
されており、メモリ回路に電源の電力が供給されていな
いときはメモリ回路に供給せず、メモリ回路に電源の電
力が供給されているときはメモリ回路に供給する、前記
電源の使用可能電圧値より低い電圧値の補助電源回路と
、メモリ回路に入力されるアドレス信−１−−９′２ 号と入出力データをイネーブル、ディスエーブルするス
リーステートバスバッファ回路ト、前記第２のトランジ
スタに接続されており、第２のトランジスタのオフでメ
モリ回路のＣ８端子オヨヒスリーステートバスバツフ了
回路のＯＥ端子をハイインピーダンス入力状態とするオ
ーブンコレクタゲート回路とからなり、電源電圧断また
は低下時に、補助電源回路の電力をメモリ回路に供給す
るとともにメモリ回路のアドレスの入力、データの入出
力およびメモリ回路の選択を禁止するように構成したこ
とを特徴とするバッチ９フ９２１２フ回路。[Scope of Claims] In a battery backup circuit that backs up the power of a memory circuit that stores data, a battery is inserted between a power source and a power terminal of the memory circuit to control on/off of power supply to the memory circuit. a transistor, a second transistor connected to the power supply, and a voltage detection circuit that controls the first and second transistors to turn off when the power supply voltage value is above a certain value, and turns off when the power supply voltage value is below the certain value. is connected to the connection point between the first transistor and the memory circuit, and when power is not being supplied to the memory circuit, the power is not supplied to the memory circuit, but the power is supplied to the memory circuit. In this case, the auxiliary power supply circuit that supplies the memory circuit with a voltage lower than the usable voltage value of the power supply, and the address signals and input/output data that are input to the memory circuit are enabled and disabled. A three-state bus buffer circuit is connected to the second transistor, and when the second transistor is turned off, the C8 terminal of the memory circuit and the OE terminal of the three-state bus buffer circuit are brought into a high impedance input state. It consists of an oven collector gate circuit, and is configured to supply power from the auxiliary power supply circuit to the memory circuit when the power supply voltage is interrupted or decreased, and to prohibit address input, data input/output, and memory circuit selection of the memory circuit. A batch 9F9212F circuit characterized by:
JP58230318A 1983-12-06 1983-12-06 Battery backup circuit Pending JPS60122447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58230318A JPS60122447A (en) 1983-12-06 1983-12-06 Battery backup circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58230318A JPS60122447A (en) 1983-12-06 1983-12-06 Battery backup circuit

Publications (1)

Publication Number Publication Date
JPS60122447A true JPS60122447A (en) 1985-06-29

Family

ID=16905946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58230318A Pending JPS60122447A (en) 1983-12-06 1983-12-06 Battery backup circuit

Country Status (1)

Country Link
JP (1) JPS60122447A (en)

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