JPS5998547A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5998547A
JPS5998547A JP57206173A JP20617382A JPS5998547A JP S5998547 A JPS5998547 A JP S5998547A JP 57206173 A JP57206173 A JP 57206173A JP 20617382 A JP20617382 A JP 20617382A JP S5998547 A JPS5998547 A JP S5998547A
Authority
JP
Japan
Prior art keywords
thickness
inner lead
etching
substrate
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57206173A
Other languages
Japanese (ja)
Inventor
Hideki Kosaka
小坂　秀樹
Hajime Murakami
元 村上
Masachika Masuda
正親 増田
Tokuji Toida
戸井田　徳次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57206173A priority Critical patent/JPS5998547A/en
Publication of JPS5998547A publication Critical patent/JPS5998547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to ultrafinely form a wiring pattern, to reduce the size of a semiconductor device, to increase the number of pins and to reduce the thickness of the device by reducing in thickness at least part of inner leads of leads connected to a bonding pad as compared with the other part. CONSTITUTION:A substrate 1 is formed of a conductor metal such as copper or the like, and inner leads 2 which are, for example, formed in thickness 1/2 of the original thickness as compared with the other part by stepwisely etching the conductor metal of the substrate 1 from the lower surface side is disposed at the central side. On the other hand, the outer connecting terminal 3 outside the inner leads 2 remains the original thickness of the substrate 1 (0.15mm. or 0.25mm.), and has sufficient mechanical strength. After the inner leads 2 are reduced in thickness by stepwise etching, an inner lead wiring pattern is ultrafinely formed by ordinary etching. The substrate 1 is constructed to form an ultrafine wiring pattern on the thin inner leads 2, and the connecting terminal 3 is constructed in 2- step structure for maintaining the required mechanical strength.

Description

【発明の詳細な説明】 本発明は半導体装置、特に、インナーリード部のパター
ンの微細化の可能な半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the pattern of an inner lead portion can be miniaturized.

最近、半導体装置の製造においては、集積度の向上への
要求が１す１す高１っており、小型化、多ビン化の傾向
が進んでいる。Recently, in the manufacturing of semiconductor devices, there has been an increasing demand for higher integration, and there is a trend towards smaller sizes and larger numbers of bins.

ところで、従来の半導体装置では、ベレットををり付け
るための基板として用いられるリードフレーふけコバー
ル、４２７０イの如き、鉄系又ケ、リン青銅、８ｎ入シ
銅の如き銅系の材料で作られており、その厚さは０．１
５ｗｍあるいは０．２５ｍというかなり厚いものになっ
てし１う。By the way, in conventional semiconductor devices, the lead flakes used as substrates for attaching pellets are made of copper-based materials such as iron-based materials such as Kovar and 4270I, phosphor bronze, and 8N-containing copper. and its thickness is 0.1
It will be quite thick at 5wm or 0.25m.

その結果、リードフレームのインナーリード部をエツチ
ング加工又はプレス加工で形成する場合、リードフレー
ム自体の厚さの次めに微細加工が困難であり、位置精度
の良いインナーリード配線パターンを得ることはできな
かった。そのため、ワイヤボンディングの不良が発生（
、小型化や多ビン化が困難になるという問題があった。As a result, when forming the inner lead portion of a lead frame by etching or press processing, microfabrication is difficult next to the thickness of the lead frame itself, and it is impossible to obtain an inner lead wiring pattern with good positional accuracy. There wasn't. As a result, wire bonding defects occur (
However, there was a problem in that it was difficult to downsize and increase the number of bins.

さらに１従来、たとえばチップキャリアパッケージのよ
うにセラミックやガラス入り樹脂ケ用いた基板にベレッ
トををり付ける場合もあるが、その場合でも多ピン化の
ためにはインナーリード部の微細加工が必要で、その加
工が困難である上に、製品の小型化、薄型化にも自ずか
ら限界がある。Furthermore, in the past, for example, a bullet was attached to a substrate made of ceramic or glass-filled resin, such as in a chip carrier package, but even in that case, microfabrication of the inner lead part was required to increase the number of pins. In addition to being difficult to process, there are inherent limits to miniaturization and thinning of products.

本発明の目的は、前記従来技術の問題点を解決し、イン
ナーリード部の配線パターンの微細加工が可能で、小型
化、多ピン化を実現することができ、あるいは薄型化を
可能にする半導体装置を提供することにある。It is an object of the present invention to solve the problems of the prior art, to enable fine processing of the wiring pattern of the inner lead part, to realize miniaturization, to increase the number of pins, or to make it possible to reduce the thickness of the semiconductor. The goal is to provide equipment.

以下、本発明を図面に示す実施例にしたがって詳細に欽
明する。Hereinafter, the present invention will be explained in detail according to embodiments shown in the drawings.

第１図は本発明による半導体装置の一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

この実施例における半導体装置にいわゆるチップキャリ
ア形パッケージよりなるものである。この半導体装置の
パッケージを構成する基板Ｉ　Ｆｉ錐（Ｏｕ）等の導体
金属よシな）、その中央側には、下面側から該基板１の
導体金属を段状にエツチングすることにより他の部分よ
シも薄い厚さ例えば本来の厚さの１７２の厚さに形成さ
れたインナーリード部２が位置【、ている。一方、イン
ナーリード部２の外側の外部接続端子部３は基板１の本
来の厚さく０．１５ｍ’！７ｔは０．２５ｍ）のｔ１で
あり、十分な機械的強度を有している。The semiconductor device in this embodiment is a so-called chip carrier type package. On the center side of the substrate 1 (such as a conductive metal such as an I Fi cone (Ou)) constituting the package of this semiconductor device, other parts are formed by etching the conductive metal of the substrate 1 in steps from the bottom side. The inner lead portion 2, which is formed to have a relatively thin thickness, for example, 172 mm thick, is located at the inner lead portion 2. On the other hand, the external connection terminal section 3 on the outside of the inner lead section 2 has the original thickness of the board 1, which is 0.15 m'! 7t is t1 (0.25m), and has sufficient mechanical strength.

前記インナーリード部２は段エツチングで薄くした後、
インナーリード配線パターンを通常のエツチングによシ
微細加工されている。After the inner lead part 2 is made thinner by step etching,
The inner lead wiring pattern is finely processed by ordinary etching.

エツチング液としては、いづれも塩化第２鉄の溶液を用
いる。また、エツチングの方法としては、ノズルを用い
てエツチング液を所望の領域に噴射する方法が用いられ
る。ノズルの径を小さくし、その位置等を制御すること
によって、微細加工が可能とがる。また、必要な領域を
覆うマスクを用いてエツチングを行うこともできる。マ
スクの形成はホトエツチングなどによればよい。これに
より、基板１は、厚さの薄いインナーリード部２に微細
配線パターンを形成すると共に、その外側の外部接続端
子部３は要求される機械的強度を維持する２段構造とな
っている。As the etching solution, a ferric chloride solution is used in each case. Further, as an etching method, a method is used in which a nozzle is used to spray an etching liquid onto a desired area. Fine processing becomes possible by reducing the diameter of the nozzle and controlling its position. Etching can also be performed using a mask that covers the required area. The mask may be formed by photoetching or the like. As a result, the substrate 1 has a two-tiered structure in which a fine wiring pattern is formed on the thin inner lead portion 2, and the external connection terminal portion 3 on the outside thereof maintains the required mechanical strength.

前記インナーリード部２の中心部には開口部が形成され
、この開口部の中にはペレット４が収容され、該ペレッ
ト４のポンディングパッドとインナーリード部２との間
でワイヤ５のボンディングを行なう。このワイヤボンデ
ィング時には、ペレット４は下方から適宜の支持手段（
図示せず）により真空吸引力で支持しながらポンディン
グ作業金石なう。An opening is formed in the center of the inner lead part 2, a pellet 4 is accommodated in this opening, and a wire 5 is bonded between the bonding pad of the pellet 4 and the inner lead part 2. Let's do it. During this wire bonding, the pellet 4 is supported from below by appropriate support means (
(not shown) allows the pounding operation to be carried out while being supported by vacuum suction force.

また、前記インナーリード部２の上下両面および外部接
続端子部３の上面には、前記ワイヤ５のボンディングに
必要な場所等を除いて、インナーリードが動かないよう
に絶縁テープ６が貼着されている。この絶縁テープ６は
たとえばポリイミドまたけボリアきド系の樹脂で作られ
ている。Furthermore, insulating tape 6 is pasted on both the upper and lower surfaces of the inner lead portion 2 and the upper surface of the external connection terminal portion 3 to prevent the inner lead from moving, except for areas necessary for bonding the wire 5. There is. This insulating tape 6 is made of, for example, a polyimide-covered boriyad resin.

前記ペレット４はワイヤ５のボンディングを行なった後
、ボッティングレジン７によシ封止され、そのボッティ
ングレジン７の上からキャップ８で押え付けることにニ
ジ封止が完了する。After the pellet 4 is bonded with the wire 5, it is sealed with a botting resin 7, and the sealing is completed by pressing the cap 8 onto the botting resin 7.

本実施例によれば、チップキャリア形パッケージを構成
する基板１のインナーリード部２が段エツチングによっ
て外部接続端子部３１）も薄く加工されるので、インナ
ーリード配線パターンの微細加工が可能である上に１外
部接続端子部３は元の厚さの１１であるので、必要な機
梯的強度を得ることができる。According to this embodiment, since the inner lead portion 2 of the substrate 1 constituting the chip carrier type package is also processed to be thin by step etching, the external connection terminal portion 31) is also made thinner, making it possible to finely process the inner lead wiring pattern. Since the external connection terminal portion 3 has the original thickness of 11, the necessary mechanical strength can be obtained.

第２図は本発明による半導体装置の他の実施例を示す。FIG. 2 shows another embodiment of the semiconductor device according to the present invention.

この実施例では、半導体装置のペレット取付基板として
のリードフレーム１０ｉｊインナート部１１とタブ１２
とが上下両側あるいけ片面から段エツチングすることに
より薄く（本来の厚さの数分の−）加工され、アウター
リード部１３はその１１の厚さく０．１５削または０．
２５ｍ）である。In this embodiment, a lead frame 10ij, an inner part 11 and a tab 12 are used as a pellet mounting board for a semiconductor device.
The outer lead part 13 is thinned by step etching from one side (a few minutes of the original thickness) on both the top and bottom sides, and the outer lead part 13 is made thin by 0.15 or 0.
25m).

段エツチングに工り薄くな−）たインナーリード部１１
は通常のエツチングによって微細なインナーリード配線
パターンを加工される。Inner lead part 11 made thinner by step etching
A fine inner lead wiring pattern is processed by normal etching.

また、タブ１２の上には、ペレット１４が接合材１５で
をり付けられ、このペレット１４のポンディングパッド
は前記インナーリード部１１の各配線パターンとワイヤ
１６でボンディングされ、電気的に接続されている。Further, a pellet 14 is attached onto the tab 12 with a bonding material 15, and the bonding pads of the pellet 14 are bonded to each wiring pattern of the inner lead portion 11 with wires 16 to be electrically connected. ing.

その後、ペレット１４、インナーリード部１１お↓びワ
イヤ１６等はレジンモールドに工）パッケージ１７内に
封止される。Thereafter, the pellet 14, inner lead portion 11, wire 16, etc. are molded into a resin mold and sealed in a package 17.

第２図の実施例においても、リードフレーム１０のイン
ナーリード部１１を段エツチングにより薄く加工したこ
とにニジ、インナーリード配線パターンの微細加工が可
能であり、パターン精度の向上、／Ｊ−型化、多ピン化
が度られる上に、アクタ−リード部１３はその１１の厚
さであるので、を扱い等のために必要が機棹的強度は十
分維持される。In the embodiment shown in FIG. 2 as well, since the inner lead portion 11 of the lead frame 10 is thinned by step etching, it is possible to finely process the inner lead wiring pattern, improving pattern accuracy, and making it J-shaped. In addition to increasing the number of pins, the actor lead portion 13 has a thickness of 11, so that the mechanical strength necessary for handling etc. can be maintained sufficiently.

第３図は本発明による半導体装置の他の実施例を示す断
面図である。FIG. 3 is a sectional view showing another embodiment of the semiconductor device according to the present invention.

この実施例においては、リードフレーム２０のインナー
リード部２１は上側から段エツチングされ、アウターリ
ード部２２の厚さく０．１５ｍ’Ｆたけ０．２５ｍ）よ
りも薄く（例えば１／２の厚さ）加工されている。この
インナーリード部２１はその後のエツチングによりイン
ナーリード配置パターンを微細加工されるが、その微細
リードの補強のため、インナーリード部２１の下面側に
は、フィルム２３が貼夛付けられている。In this embodiment, the inner lead part 21 of the lead frame 20 is etched in steps from the upper side, and is thinner (for example, 1/2 the thickness) than the outer lead part 22 (0.15 m'F x 0.25 m). Processed. This inner lead portion 21 is subjected to subsequent etching to finely process the inner lead arrangement pattern, and a film 23 is pasted on the lower surface side of the inner lead portion 21 to reinforce the fine leads.

このフィルム２３で補強されたインナーリード部の上に
はペレット２４が接着剤２５で取シ付けられ、該ペレッ
ト２４のポンディングパッドはワイヤ２６でインナーリ
ード部２１の配線パターンとボンディングされる。その
後、ペレット２４、ワイヤ２６、フィルム２３等ｔｉレ
ジンモールドによシハッケージ２７内に封止される。A pellet 24 is attached to the inner lead portion reinforced with the film 23 with an adhesive 25, and the bonding pad of the pellet 24 is bonded to the wiring pattern of the inner lead portion 21 with a wire 26. Thereafter, the pellet 24, wire 26, film 23, etc. are sealed in the housing cage 27 using a Ti resin mold.

したがって、この実施例でも、インナーリード部２１が
段エツチングで薄く加工されているので、インナーリー
ド配線パターンの微細化が可能であり、パターン精度が
向上し、小型化、多ビン化を実現でき、またアウターリ
ード部２２の機械的強度は十分に維持される。Therefore, in this embodiment as well, since the inner lead portion 21 is processed to be thin by step etching, it is possible to miniaturize the inner lead wiring pattern, improve pattern accuracy, and realize miniaturization and multi-bin. Further, the mechanical strength of the outer lead portion 22 is maintained sufficiently.

なお、本発明は前記実施例に限定されるものではなく、
他の様々な変形が可能である。Note that the present invention is not limited to the above embodiments,
Various other variations are possible.

以上説明したように１本発明によれば、ペレットを何基
板のインナーリード配線パターンを微細化でき、パター
ン精度の向上、小型化、多ピン化が可能である。As explained above, according to the present invention, it is possible to miniaturize the inner lead wiring pattern of any substrate using pellets, and it is possible to improve pattern accuracy, downsize, and increase the number of pins.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による半導体装置の一実施例の断面図、 第２図は本発明の他の１つの実施例を示す断面図、 第３図は本発明のさらに他の１つの実施例を示す断面図
である。 １・・・基板、２・・・インナーリード部、３・・・外
部接続端子部、４・・・ペレット、１０・・・リードフ
レーム、１１・・・インナーリード部、１３・・・アク
タ−リードｍ、１４・・・ペレット、２０・・・リード
フレーム、２１・・・インナーリード部、２２・・・ア
ウターリード部、２４・・・ペレット。 第　　１　　図 第　　２　図 第　　３　図FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, and FIG. 3 is a cross-sectional view of yet another embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Board, 2... Inner lead part, 3... External connection terminal part, 4... Pellet, 10... Lead frame, 11... Inner lead part, 13... Actor Lead m, 14... Pellet, 20... Lead frame, 21... Inner lead part, 22... Outer lead part, 24... Pellet. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 １、半導体ベレットのポンディングパッドト接続される
リードのインナーリード部の少なくとも一部を他の部分
よりも薄くしたことを特徴とする半導体装置。 ２、半導体ペレットのポンディングパッドと接続される
リードのインナーリード部をエツチングにより他の部分
より薄く加工することを特徴とする半導体装置の製造方
法。Claims: 1. A semiconductor device characterized in that at least a portion of an inner lead portion of a lead connected to a bonding pad of a semiconductor pellet is made thinner than the other portion. 2. A method for manufacturing a semiconductor device, characterized in that the inner lead portion of the lead connected to the bonding pad of the semiconductor pellet is processed to be thinner than other portions by etching.
JP57206173A 1982-11-26 1982-11-26 Semiconductor device and manufacture thereof Pending JPS5998547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57206173A JPS5998547A (en) 1982-11-26 1982-11-26 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206173A JPS5998547A (en) 1982-11-26 1982-11-26 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5998547A true JPS5998547A (en) 1984-06-06

Family

ID=16519012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206173A Pending JPS5998547A (en) 1982-11-26 1982-11-26 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5998547A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994411A (en) * 1988-03-10 1991-02-19 Hitachi, Ltd. Process of producing semiconductor device
JPH0472751A (en) * 1990-07-13 1992-03-06 Nippon Steel Corp Semiconductor lead frame and manufacture thereof
JPH04219965A (en) * 1990-03-15 1992-08-11 Internatl Business Mach Corp <Ibm> Lead frame for semiconductor
JPH08162558A (en) * 1994-12-07 1996-06-21 Fujitsu Ltd Semiconductor device
US5834831A (en) * 1994-08-16 1998-11-10 Fujitsu Limited Semiconductor device with improved heat dissipation efficiency
WO2011083368A1 (en) * 2010-01-05 2011-07-14 Nxp B.V. Delamination resistant semiconductor devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994411A (en) * 1988-03-10 1991-02-19 Hitachi, Ltd. Process of producing semiconductor device
JPH04219965A (en) * 1990-03-15 1992-08-11 Internatl Business Mach Corp <Ibm> Lead frame for semiconductor
JPH0472751A (en) * 1990-07-13 1992-03-06 Nippon Steel Corp Semiconductor lead frame and manufacture thereof
US5834831A (en) * 1994-08-16 1998-11-10 Fujitsu Limited Semiconductor device with improved heat dissipation efficiency
JPH08162558A (en) * 1994-12-07 1996-06-21 Fujitsu Ltd Semiconductor device
WO2011083368A1 (en) * 2010-01-05 2011-07-14 Nxp B.V. Delamination resistant semiconductor devices

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