JPH04322435A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH04322435A
JPH04322435A JP3090509A JP9050991A JPH04322435A JP H04322435 A JPH04322435 A JP H04322435A JP 3090509 A JP3090509 A JP 3090509A JP 9050991 A JP9050991 A JP 9050991A JP H04322435 A JPH04322435 A JP H04322435A
Authority
JP
Japan
Prior art keywords
metal
leads
semiconductor chip
semiconductor device
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3090509A
Other languages
Japanese (ja)
Inventor
Kozo Nishino
西野　弘三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP3090509A priority Critical patent/JPH04322435A/en
Publication of JPH04322435A publication Critical patent/JPH04322435A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device and a method for manufacturing the same in which strengths of metal leads for connecting a semiconductor chip to outer leads are increased. CONSTITUTION:A semiconductor chip 1 placed in a lead frame 2 is connected to outer leads 2b via metal leads 5, and the frame 2, a region except a surface protective film 3 of the chip 2 and the leads 5 are formed with a metal film 6.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体チップと外部リー
ドとを接続した金属リードを補強した半導体装置および
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which metal leads connecting a semiconductor chip and external leads are reinforced, and a method for manufacturing the same.

【０００２】0002

【従来の技術】通常、半導体チップと外部リードとの電
気的接続は金属細線を用いたワイヤボンディングにより
行われる。2. Description of the Related Art Generally, electrical connections between semiconductor chips and external leads are made by wire bonding using thin metal wires.

【０００３】以下に従来の半導体装置について説明する
。図２は従来の半導体装置の要部断面図である。図２に
示すように、半導体チップ１はリードフレーム２のダイ
パッド２ａにダイボンドされている。半導体チップ１の
表面には、保護膜３が形成されており、その保護膜３の
一部が開口されて電極パッド４が露出している。この電
極パッド４と外部リード２ｂが金属リード（この場合は
金属細線）５により接続されている。A conventional semiconductor device will be explained below. FIG. 2 is a sectional view of a main part of a conventional semiconductor device. As shown in FIG. 2, the semiconductor chip 1 is die-bonded to a die pad 2a of a lead frame 2. As shown in FIG. A protective film 3 is formed on the surface of the semiconductor chip 1, and a portion of the protective film 3 is opened to expose the electrode pads 4. This electrode pad 4 and external lead 2b are connected by a metal lead (in this case, a thin metal wire) 5.

【０００４】0004

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、金属リード５の強度が弱く、全体を樹脂
封止する際に金属リード５が封止用樹脂の動圧により流
されて、金属リード５の断線やショートが発生するとい
う課題を有していた。近年、半導体装置の小型化を進め
るために電極パッド４の縮小化が望まれているが、その
ために金属リード５となるワイヤボンディング用の金属
細線を細くしなければならず、ますます断線、ショート
の危険性が増大している。However, in the above-described conventional structure, the strength of the metal lead 5 is weak, and when the whole is sealed with resin, the metal lead 5 is washed away by the dynamic pressure of the sealing resin, and the metal lead 5 is washed away by the dynamic pressure of the sealing resin. There was a problem in that the leads 5 were broken or shorted. In recent years, it has been desired to reduce the size of the electrode pad 4 in order to advance the miniaturization of semiconductor devices, but for this reason, the thin metal wire for wire bonding that becomes the metal lead 5 has to be made thinner, which increases the risk of disconnections and short circuits. The risk of

【０００５】本発明は上記の従来の課題を解決するもの
で、金属リードの強度を増強した半導体装置およびその
製造方法を提供することを目的とする。The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor device in which the strength of metal leads is increased and a method for manufacturing the same.

【０００６】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置は、基板に搭載された半導体チッ
プと外部リードとが金属リードで接続されており、かつ
基板の少なくとも一部と、半導体チップの表面の保護膜
の上を除いた領域と、金属リードとに金属被膜が形成さ
れている構成を有している。[Means for Solving the Problems] In order to achieve this object, a semiconductor device of the present invention has a semiconductor chip mounted on a substrate and an external lead connected by a metal lead, and at least a part of the substrate. The device has a structure in which a metal film is formed on the surface of the semiconductor chip except for the area above the protective film and on the metal leads.

【０００７】[0007]

【作用】この構成によって、細い金属リードを用いても
その強度を増大させることができ、金属リードの断線や
ショートによる不良が減少する。[Operation] With this structure, even if a thin metal lead is used, its strength can be increased, and defects due to disconnection or short circuit of the metal lead can be reduced.

【０００８】[0008]

【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図１は本発明の一実施例における半
導体装置の要部断面図である。なお図２に示す従来例と
同一箇所には同一符号を付して、詳細説明を省略した。 図１に示す本実施例が図２に示す従来例と異なる点は、
半導体チップ１の保護膜３を除く領域、リードフレーム
２の表面および金属リード５の表面に金属被膜６が形成
されていることである。この時、半導体チップ１のエッ
ジ部分１ａには保護膜３が形成されているので、金属被
膜６は形成されない。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. Note that the same parts as in the conventional example shown in FIG. 2 are given the same reference numerals, and detailed explanations are omitted. The difference between this embodiment shown in FIG. 1 and the conventional example shown in FIG. 2 is as follows.
A metal coating 6 is formed on the area of the semiconductor chip 1 excluding the protective film 3, the surface of the lead frame 2, and the surface of the metal lead 5. At this time, since the protective film 3 is formed on the edge portion 1a of the semiconductor chip 1, the metal coating 6 is not formed.

【０００９】このような半導体装置は次の工程により製
造される。まず半導体チップ１をリードフレーム２のダ
イパッド２ａに合金法、はんだ付けまたは接着剤法を用
いてダイボンドする。次に電極パッド４と外部リード２
ｂとの間を金属細線を用いたワイヤボンディングにより
接続して金属リード５を形成する。次にリードフレーム
２を一方の電極として金、銅、クロム等を電気めっきす
る。この時、金属部分には金属被膜は形成されるが、半
導体チップ１の上に形成されている保護膜３の上には金
属被膜６は形成されない。したがって半導体チップ１の
エッジ部分１ａには金属被膜６は形成されないが、必要
ならば金属被膜６が形成されては困る部分にめっきレジ
ストを形成しておけば良い。金属被膜６の形成方法は、
めっき法以外にも蒸着等でも良いし、金属被膜６は特に
金、銅またはクロムに限るものではない。なお金属被膜
６は金属リード５の表面にのみ形成されても同様の効果
は得られる。[0009] Such a semiconductor device is manufactured by the following steps. First, the semiconductor chip 1 is die-bonded to the die pad 2a of the lead frame 2 using an alloy method, soldering, or adhesive method. Next, electrode pad 4 and external lead 2
A metal lead 5 is formed by connecting to b by wire bonding using a thin metal wire. Next, gold, copper, chromium, etc. are electroplated using the lead frame 2 as one electrode. At this time, a metal film is formed on the metal portion, but a metal film 6 is not formed on the protective film 3 formed on the semiconductor chip 1. Therefore, the metal coating 6 is not formed on the edge portion 1a of the semiconductor chip 1, but if necessary, a plating resist may be formed in the area where the formation of the metal coating 6 would be a problem. The method for forming the metal coating 6 is as follows:
In addition to plating, vapor deposition or the like may be used, and the metal coating 6 is not limited to gold, copper, or chromium. Note that the same effect can be obtained even if the metal coating 6 is formed only on the surface of the metal lead 5.

【００１０】0010

【発明の効果】以上のように本発明は、少なくとも金属
リードの表面に金属被膜を形成した構成とすることによ
り、金属リードの強度を増大させた優れた半導体装置を
実現できるものである。As described above, the present invention makes it possible to realize an excellent semiconductor device in which the strength of the metal leads is increased by forming a metal film on at least the surface of the metal leads.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の一実施例における半導体装置の要部断
面図FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention.

【図２】従来の半導体装置の要部断面図[Figure 2] Cross-sectional view of main parts of a conventional semiconductor device

【符号の説明】[Explanation of symbols]

１　　半導体チップ ２　　リードフレーム（基板） ２ｂ　　外部リード ３　　保護膜 ５　　金属リード ６　　金属被膜 1 Semiconductor chip 2 Lead frame (board) 2b External lead 3 Protective film 5 Metal lead 6 Metal coating

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】　　基板に搭載された半導体チップと外部
リードとが金属リードで接続されており、前記基板の少
なくとも一部と、前記半導体チップの表面の保護膜の上
を除いた領域と、前記金属リードとに金属被膜が形成さ
れている半導体装置。1. A semiconductor chip mounted on a substrate and an external lead are connected by a metal lead, and at least a part of the substrate, a region on the surface of the semiconductor chip except for a protective film, and A semiconductor device in which a metal film is formed on the metal leads. 【請求項２】　　基板の上に搭載された半導体チップの
電極パッドと外部リードとを金属リードで接続した後、
前記基板の少なくとも一部と、前記半導体チップの表面
の保護膜の上を除いた領域と、前記金属リードとに金属
被膜を形成する半導体装置の製造方法。[Claim 2] After connecting the electrode pads of the semiconductor chip mounted on the substrate and the external leads with metal leads,
A method of manufacturing a semiconductor device, comprising forming a metal coating on at least a portion of the substrate, a region of the surface of the semiconductor chip except for a top surface of a protective film, and the metal lead.
JP3090509A 1991-04-22 1991-04-22 Semiconductor device and manufacture thereof Pending JPH04322435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3090509A JPH04322435A (en) 1991-04-22 1991-04-22 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3090509A JPH04322435A (en) 1991-04-22 1991-04-22 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04322435A true JPH04322435A (en) 1992-11-12

Family

ID=14000448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3090509A Pending JPH04322435A (en) 1991-04-22 1991-04-22 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04322435A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010197165A (en) * 2009-02-24 2010-09-09 Mitsubishi Materials Corp Thin-film temperature sensor and method for manufacturing the same
US8030744B2 (en) 2005-06-22 2011-10-04 Infineon Technologies Ag Arrangement for electrically connecting semiconductor circuit arrangements to an external contact device and method for producing the same
JP2016042587A (en) * 2015-10-29 2016-03-31 アピックヤマダ株式会社 Dummy frame, evaluation method of resin mold, evaluation method of molding metal die, and manufacturing method of molding metal die

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030744B2 (en) 2005-06-22 2011-10-04 Infineon Technologies Ag Arrangement for electrically connecting semiconductor circuit arrangements to an external contact device and method for producing the same
DE102005028951B4 (en) 2005-06-22 2018-05-30 Infineon Technologies Ag Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device
JP2010197165A (en) * 2009-02-24 2010-09-09 Mitsubishi Materials Corp Thin-film temperature sensor and method for manufacturing the same
JP2016042587A (en) * 2015-10-29 2016-03-31 アピックヤマダ株式会社 Dummy frame, evaluation method of resin mold, evaluation method of molding metal die, and manufacturing method of molding metal die

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